1

1 (a) How many address lines does an 8086 have? How many memory addresses does
this number of address lines allow the 8086 to access directly?

8086 has 20 address lines (A0 to A19).​

With 20 address lines, it can directly access 2²⁰ = 1,048,576 memory locations (or 1 MB of
memory).

1 (b) List the major steps in developing an assembly language programming.

1.​ Define the problem and algorithm.

2.​ Write the code using mnemonics.
3.​ Use an assembler to convert the code to machine language.
4.​ Debug and test the program.
5.​ Execute and verify the output.

1 (c) Why are the port lines of programmable port devices automatically put in the input
mode when the device is first powered up or reset?

Port lines are set to input mode by default during reset to avoid damage due to conflicts. If
multiple devices try to output on the same line, it could cause short circuits. Input mode is safe
and prevents such issues until proper initialization.

1 (d) What do you understand by the term Multiprogramming? Explain briefly.

Multiprogramming is a technique where multiple programs reside in memory at the same

time, and the CPU executes them concurrently by switching between them. It improves CPU
utilization and system throughput.

1 (e) List and describe in general terms the steps an 8086 will take when it responds to an
interrupt.

1.​ Completes current instruction.

2.​ Pushes FLAGS register onto the stack.
3.​ Disables INTR (if applicable).
4.​ Pushes CS and IP onto the stack.
5.​ Loads the new IP and CS from the interrupt vector table.
6.​ Begins execution of the interrupt service routine (ISR).

1 (f) Which register bank conflicts with the stack in 8051? Justify your answer.

Register Bank 1 (addresses 08H to 0FH) conflicts with the stack, because the default stack
starts at address 07H. If the stack grows beyond 07H and Bank 1 is used, it can overwrite
register values, causing conflicts.
 2

1 (g) Explain MOV A,@R0 instruction of 8051. Which addressing mode is used in this
instruction?

This instruction moves the content of the internal RAM memory location pointed by register
R0 into the accumulator (A).​
Addressing mode used: Register Indirect Addressing Mode.

—------------

2 (a) What do you understand by memory segmentation in 8086? Explain in

detail.

Memory Segmentation in 8086 refers to dividing the memory into small, manageable sections
or segments. Each segment can be up to 64 KB in size. This technique allows the processor to
access a large address space (1 MB) using only 16-bit registers.

8086 uses four segment registers:

1.​ CS (Code Segment): Stores the base address of the code (instructions).
2.​ DS (Data Segment): Stores the base address of the data.
3.​ SS (Stack Segment): Stores the base address of the stack.
4.​ ES (Extra Segment): Used for additional data.

To calculate the physical address:

Physical Address = Segment Register × 10H + Offset

Advantages:

●​ Modular programming (separates code, data, and stack).

●​ Efficient memory use.
●​ Allows multiple programs or procedures to run safely.

2 (b) Show the 8086 instruction or group of instructions which will:

(i) Initialize the stack segment register to 4000H and the stack pointer to 8000H

assembly

MOV AX, 4000H

MOV SS, AX

MOV SP, 8000H

 3

(ii) Call a near procedure named FIXIT

assembly

CALL FIXIT

(iii) Save BX and BP at the start of a procedure and restore them at the end

assembly

PUSH BX

PUSH BP

; Procedure code here

POP BP

POP BX

(iv) Return from a procedure and automatically increment the stack pointer by 8

Use:

assembly

RET 8

This instruction pops the return address and increments SP by 8 bytes.

3 (a) With the help of a neat diagram, explain the block diagram of 8086
microprocessor.

8086 Block Diagram Components:

1.​ Bus Interface Unit (BIU):

○​ Responsible for interfacing with memory and I/O.
○​ Contains: Instruction queue, segment registers (CS, DS, SS, ES), instruction
pointer.
2.​ Execution Unit (EU):
○​ Executes instructions fetched by BIU.
○​ Contains: ALU, general-purpose registers (AX, BX, CX, DX), flags, control unit.
3.​ Instruction Queue:
○​ Pre-fetches up to 6 bytes of instructions to increase speed (pipelining).
 4

4.​ Control System:

○​ Decodes and manages instruction execution and control signals.

Simple diagram (text form):

-------------------------

| Bus Interface Unit |

|-------------------------|

| Instruction Pointer (IP)|

| Segment Registers |

| Instruction Queue |

-------------------------

-------------------------

| Execution Unit |

|-------------------------|

| ALU, Flags |

| General Registers |

| Control Circuit |

-------------------------
 5

Here is the assembly language program to find the largest number in an array of 8-bit
numbers for 8086 microprocessor:

🔧 Program: Find the Largest Number in an Array

asm
.model small
.data
array db 25h, 89h, 3Ah, 7Dh, 9Ch ; Example array of 8-bit numbers
count db 05h ; Number of elements in the
array
max db ? ; Variable to store maximum

.code
main:
mov ax, @data ; initialize data segment
mov ds, ax

lea si, array ; SI points to the first element of array

mov cl, count ; Load count into CL
mov al, [si] ; Load first number in AL as max
inc si ; Move to next element
dec cl ; One element already taken

next:
cmp al, [si] ; Compare max (AL) with current element
jnc skip ; If AL >= [SI], skip update
mov al, [si] ; Else, update max with [SI]

skip:
inc si ; Move to next element
dec cl ; Decrease count
jnz next ; Repeat till all elements are checked

mov max, al ; Store result in variable

mov ah, 4ch ; Exit to DOS

int 21h

end main
 6

📌 Explanation:
●​ The program loads an array of 8-bit numbers.
●​ Initializes AL with the first value as the maximum.
●​ Compares each remaining value using CMP.
●​ If a larger value is found, AL is updated.
●​ Finally, the largest number is stored in the max variable.

Unit II questions from your 8086 Microprocessor paper:

4 (a) Explain the following signals of 8086: ALE, M/IO, TEST, INTA, LOCK

1.​ ALE (Address Latch Enable):

○​ Used to demultiplex the address and data bus.
○​ High during T1 cycle to latch the address from multiplexed lines (AD0–AD15).
2.​ M/IO (Memory/Input-Output):
○​ Indicates whether the operation is memory-related (M/IO = 1) or I/O-related
(M/IO = 0).
3.​ TEST:
○​ Input signal used in WAIT instruction.
○​ Processor waits until TEST = 1.
4.​ INTA (Interrupt Acknowledge):
○​ Output signal.
○​ Used to acknowledge hardware interrupt requests.
5.​ LOCK:
○​ Output signal.
○​ Makes the bus signals exclusive to the processor.
○​ Prevents other processors from accessing memory during critical instructions.

4 (b) Explain the 8086 bus activity during a read machine cycle with the
help of a neat diagram.

Steps in a Read Machine Cycle:

1.​ T1 Cycle:
○​ Address is placed on the address/data bus (AD0–AD15).
○​ ALE goes high to latch the address.
2.​ T2 Cycle:
○​ Read (RD) control signal is activated.
 7

○​ Bus is prepared for data input.

3.​ T3 Cycle:
○​ Data from memory or I/O device is placed on the bus.
○​ Processor reads the data.
4.​ T4 Cycle:
○​ Control signals are deactivated.
○​ Bus returns to idle or next operation.

Diagram :

sql
Time → T1 T2 T3 T4
ALE ──┐
└──────
AD Bus Addr ---- Data ----
RD ──────── ----

Label signals properly to fetch full marks.

5 (a) Difference between Standard Microprocessor and Coprocessor

Feature Microprocessor Coprocessor

Function General-purpose Specialized (e.g., math operations)

processing

Independenc Works independently Works along with microprocessor

e

Control Executes full programs Needs control from

microprocessor

Examples Intel 8086, 8051 Intel 8087 (Math coprocessor)

Task type Logical/Control tasks Floating point/math operations

 8

5 (b) Closely Coupled vs Loosely Coupled Configurations

1.​ Closely Coupled:

○​ Processors share the same memory and I/O resources.
○​ Fast communication.
○​ Used in multiprocessor systems.
○​ Example: Dual-core systems.
2.​ Loosely Coupled:
○​ Processors have separate memory and I/O.
○​ Connected through a network or bus.
○​ Used in distributed systems.
○​ Example: Clustered systems.

Feature Closely Coupled Loosely Coupled

Memory Sharing Shared memory Separate memory

Speed Faster Slower (via network)

communication

Cost High Less expensive

Application Multiprocessors Distributed systems

—-----------------

Unit III (14 marks each) based on your image:

Q6. Draw and explain 8086 based traffic light control system in detail. (14
marks)

Traffic Light Control System using 8086:

The 8086 microprocessor can control traffic lights at a 4-way intersection (North, South, East,
West) by interfacing with LEDs using an 8255 Programmable Peripheral Interface (PPI).

Block Diagram:

Draw the following components and connect them logically:

●​ 8086 Microprocessor
●​ 8255 PPI (connected to Port A, B, C)
●​ LEDs (Red, Yellow, Green) for each direction
●​ Power Supply​
 9

●​ Timer / Delay logic (Software Delay)

Working:

●​ The LEDs for each direction are turned ON/OFF using instructions sent from 8086 via
8255 ports.
●​ A sequence is followed (e.g., North → East → South → West), giving Red-Yellow-Green
signals.
●​ A software delay is used to provide timing (e.g., 10 sec for Green, 2 sec for Yellow).

Example Code (Brief):

asm
MOV AL, 90H ; Turn on North Green
OUT PORTA, AL
CALL DELAY

MOV AL, 30H ; North Yellow

OUT PORTA, AL
CALL DELAY

MOV AL, 09H ; East Green

OUT PORTA, AL
CALL DELAY

; And so on...

Software Delay:
asm
DELAY: MOV CX, FFFFH
LOOP1: LOOP LOOP1
RET

Q7. Explain the 8279 Keyboard/Display controller with neat block diagram.

8279 Keyboard/Display Controller:

The Intel 8279 is a programmable device used to interface keyboards and displays with a
microprocessor.
 10

Block Diagram:

Draw the following blocks:

●​ Keyboard Interface
●​ FIFO/RAM for keycodes
●​ Display Interface
●​ Display RAM
●​ Control & Timing Logic
●​ CPU Interface
●​ Scan Lines / Return Lines

Key Features:

●​ Interfaces 64-key keyboard (8×8 matrix)

●​ Debounce & key lockout features
●​ Handles 16-character 7-segment LED display
●​ Programmable scan, debounce, and display formats

Explanation:

1.​ Keyboard Section:

○​ Scans rows & columns for key presses.
○​ Stores keycode in FIFO buffer.
○​ Supports 2-key lockout or N-key rollover.
2.​ Display Section:
○​ Sends data to 7-segment displays.
○​ Uses multiplexing via scan lines.
3.​ Modes of Operation:
○​ Encoded/Decoded Scan
○​ Left Entry/Right Entry for display
○​ Auto-increment of address
4.​ Programming:
○​ Control words are sent from CPU to configure scan rate, debounce time, etc.

Example Usage:
asm
MOV AL, 16H ; Command to configure 8279
OUT CONTROL, AL
 11

Unit IV (7 marks each) based on the questions:

8(a) Explain the RAM structure of 8051 in detail. (7 Marks)

The 8051 microcontroller has 128 bytes of internal RAM and 128 bytes of Special Function
Registers (SFR).

Internal RAM (00H to 7FH – 128 Bytes):

1.​ 00H to 1FH – Register Banks (32 Bytes):

○​ 4 Register Banks: Bank 0 to Bank 3
○​ Each bank has 8 registers (R0–R7)
○​ Only one bank active at a time (selected via PSW bits)
2.​ 20H to 2FH – Bit-Addressable Area (16 Bytes):
○​ 128 bits (bit-addressable memory from 20H to 2FH)
○​ Each bit can be accessed individually (e.g., SETB 20H)
3.​ 30H to 7FH – General Purpose RAM (80 Bytes):
○​ Used for variable storage, stack, etc.

SFR Area (80H to FFH):

●​ Includes registers like ACC, B, PSW, SP, DPL, DPH, TMOD, TCON, IE, etc.
●​ Some are bit-addressable (e.g., PSW, TCON, IE)

Diagram (optional for 7 marks):

yaml
00H - 1FH : Register Banks
20H - 2FH : Bit-Addressable Area
30H - 7FH : General Purpose RAM
80H - FFH : SFRs

8(b) Discuss all the Jump instructions of 8051 microcontroller. (7 Marks)

Jump instructions allow changing the flow of program execution.

Types of Jump Instructions:

1.​ SJMP (Short Jump):

○​ 2-byte instruction
○​ Jump within ±127 bytes from current PC
2.​ LJMP (Long Jump):
○​ 3-byte instruction
○​ Jumps anywhere within 64KB memory
 12

3.​ AJMP (Absolute Jump):

○​ 2-byte instruction
○​ Jumps within 2KB page
4.​ JC (Jump if Carry):
○​ Conditional jump if Carry = 1
5.​ JNC (Jump if No Carry):
○​ Conditional jump if Carry = 0
6.​ JZ (Jump if Accumulator = 0):
7.​ JNZ (Jump if Accumulator ≠ 0):
8.​ DJNZ (Decrement and Jump if Not Zero):
○​ Decrements a register and jumps if result ≠ 0
9.​ CJNE (Compare and Jump if Not Equal):
○​ Compares two operands and jumps if not equal

Example:
asm
MOV A, #00H
JZ ZERO_LABEL
; jumps to ZERO_LABEL if A = 0

9(a) Discuss various addressing modes of 8051 taking a suitable example.

Addressing modes define how the operand is accessed.

Types of Addressing Modes:

1.​ Immediate Addressing:

○​ Operand is constant.
○​ Example: MOV A, #55H
2.​ Register Addressing:
○​ Operand is a register.
○​ Example: MOV A, R1
3.​ Direct Addressing:
○​ Directly accesses RAM or SFR.
○​ Example: MOV A, 30H
4.​ Indirect Addressing:
○​ Uses register (R0/R1) as a pointer.
○​ Example: MOV A, @R0
5.​ Indexed Addressing:
○​ Used for accessing data from code memory.
○​ Example: MOVC A, @A+DPTR
 13

Example Summary Table:

Mode Example

Immediate MOV A, #0AH

Register MOV A, R2

Direct MOV A, 30H

Indirect MOV A, @R0

Indexed MOVC A,
@A+DPTR

9(b) Write shortly on the various operating modes for serial port of 8051
microcontroller.

8051 has 4 serial communication modes controlled by SCON register (SM0 and SM1 bits):

Mode Description Baud Rate

0 Shift Register Mode (8-bit) Fixed (Oscillator/12)

1 8-bit UART, Start/Stop bits Variable (Timer 1)

2 9-bit UART, Fixed baud rate Oscillator/64 or /32

3 9-bit UART, Variable baud rate Timer 1

Explanation:

●​ Mode 0:
○​ Data transferred through RXD pin
○​ TXD used for clock
●​ Mode 1:
○​ Standard 8-bit UART
○​ Start and stop bits
○​ Baud rate is set by Timer 1
●​ Mode 2:
○​ 9-bit UART (includes TB8, RB8)
○​ Fixed baud rate
●​ Mode 3:
○​ Same as Mode 2 but with variable baud rate
 14

Example Configuration (Mode 1):

asm
MOV TMOD, #20H ; Timer1 in Mode 2
MOV TH1, #FDH ; Set baud rate
MOV SCON, #50H ; Mode 1, REN enabled
SETB TR1 ; Start Timer1
 15

UNIT-I: THE 8086 MICROPROCESSOR, covering all listed topics in paragraph format:

1. Introduction to 8086

The Intel 8086 is a 16-bit microprocessor introduced by Intel in 1978. It marked the beginning of
the x86 architecture, which later became the foundation of most modern PCs. The 8086 has a
20-bit address bus, which allows it to access 1 MB of memory (2²⁰ bytes). It operates at a clock
speed between 5 MHz to 10 MHz and has a 16-bit data bus, which means it can process 16 bits
of data simultaneously. The 8086 supports pipelining using a 6-byte instruction queue, which
increases execution speed. It uses segmented memory to separate code, data, and stack
areas, making memory management flexible and efficient.

2. Microprocessor Architecture

The architecture of the 8086 microprocessor is split into two main units:

●​ Bus Interface Unit (BIU): This unit is responsible for fetching instructions from memory,
reading/writing data, and calculating the physical address. It includes the instruction
queue (6 bytes), segment registers (CS, DS, SS, ES), and the instruction pointer (IP).
●​ Execution Unit (EU): This unit decodes and executes instructions fetched by the BIU. It
contains the Arithmetic and Logic Unit (ALU), general-purpose registers (AX, BX, CX,
DX), pointer registers (SP, BP), index registers (SI, DI), flag register, and control logic.
The EU cannot directly access memory; it must request the BIU.​

3. Addressing Modes

Addressing modes define how operands are accessed in memory or registers. The 8086
supports several addressing modes:

1.​ Immediate Addressing: Operand is specified in the instruction (e.g., MOV AX, 05H).
2.​ Register Addressing: Operand is a register (e.g., MOV AX, BX).
3.​ Direct Addressing: Memory address is directly specified (e.g., MOV AX, [1234H]).
4.​ Register Indirect Addressing: Memory address is held in a register (e.g., MOV AX,
[BX]).
5.​ Based Addressing: Uses base register (BX or BP) plus a displacement.
6.​ Indexed Addressing: Uses index register (SI or DI) plus a displacement.
7.​ Based-Indexed Addressing: Combines base and index registers (e.g., MOV AX,
[BX+SI]).
8.​ Relative Addressing: Used in control transfer instructions like JMP, with the offset
relative to current IP.​
 16

4. Instruction Set and Assembler Directives

The 8086 instruction set is rich and categorized into:

●​ Data transfer instructions: MOV, XCHG, IN, OUT, etc.

●​ Arithmetic instructions: ADD, SUB, MUL, DIV, INC, DEC.
●​ Logical instructions: AND, OR, XOR, NOT, TEST.
●​ Control transfer instructions: JMP, CALL, RET, INT, IRET.
●​ String instructions: MOVS, LODS, STOS, SCAS, CMPS.
●​ Bit manipulation and shift instructions: SHL, SHR, ROL, ROR.

Assembler Directives are not executable but tell the assembler how to process the code.
Examples include:

●​ DB, DW, DD – Define byte, word, and double word

●​ SEGMENT, ENDS – Define start and end of a segment
●​ ASSUME – Informs assembler about segment usage
●​ ORG – Sets the starting offset

5. Assembly Language Programming

Assembly language allows programmers to write instructions in symbolic form (mnemonics)

rather than binary. It provides control over hardware and is used for writing efficient, low-level
programs. A typical assembly program includes defining segments, declaring variables, and
writing code using mnemonics. Programs must include directives like .MODEL, .DATA, .CODE,
and use instructions properly within a procedure, ending with RET or INT 21H.

6. Modular Programming

Modular programming involves dividing a large program into small, manageable modules or
procedures. Each module performs a specific task and can be compiled separately. In 8086,
procedures are used to achieve modularity. These are defined using PROC and ENDP directives.
Modular programming improves program organization, debugging, testing, and reusability of
code.

7. Linking and Relocation

Linking combines multiple object files into one executable. It resolves references between
separately compiled modules. Relocation allows a program to be loaded into any memory
location by adjusting address references. The 8086 supports relocation through its segmented
memory system, where logical addresses are converted to physical addresses using
segment:offset combination (e.g., physical address = segment × 16 + offset).
 17

8. Stacks

The stack is a portion of memory used for temporary storage. It operates in a Last-In-First-Out
(LIFO) manner. The stack is accessed using the SP (Stack Pointer) and SS (Stack Segment)
registers. Instructions like PUSH, POP, CALL, and RET use the stack. For example, when a
subroutine is called, the return address is pushed to the stack, and retrieved during return.

9. Procedures

A procedure is a set of instructions grouped together to perform a specific task. It can be

invoked using the CALL instruction and exited using RET. Procedures can be near (within the
same segment) or far (different segment). They help in code reusability and modular
programming. Example:

asm
CopyEdit
MYPROC PROC
; procedure code
RET
MYPROC ENDP

10. Macros

Macros are reusable code snippets defined using the MACRO directive and substituted inline
during assembly. Unlike procedures, macros do not use CALL and RET, thus avoiding overhead.
However, they increase code size. Example:

asm
CopyEdit
PRINT_MSG MACRO
MOV AH, 09H
INT 21H
ENDM

Whenever PRINT_MSG is used, the macro code is expanded in place.

11. Interrupts and Interrupt Service Routines (ISRs)

Interrupts are events that cause the microprocessor to pause its current task and execute a
predefined subroutine (ISR). The 8086 supports 256 interrupt types, each associated with a
4-byte entry in the Interrupt Vector Table (IVT). Interrupts are of two types:
 18

●​ Hardware Interrupts: Triggered by external devices (e.g., keyboard).

●​ Software Interrupts: Triggered by instructions like INT.​
Common interrupts include:
●​ INT 21H: DOS function calls
●​ INT 10H: Video services​
ISRs are routines that handle interrupts and must end with IRET.

12. Byte and String Manipulation

The 8086 offers specialized instructions for string operations, which work with the SI, DI, and
CX registers:

●​ MOVSB, MOVSW: Move byte/word from source to destination.

●​ LODSB, LODSW: Load byte/word from string into accumulator.
●​ STOSB, STOSW: Store accumulator into string.
●​ CMPSB, CMPSW: Compare source and destination bytes/words.
●​ SCASB, SCASW: Scan a string for a value in AL/AX.​
These can be combined with the REP prefix to repeat operations based on CX. For
example, REP MOVSB copies a block of bytes.

UNIT-II: 8086 SYSTEM BUS STRUCTURE,

1. 8086 Signals

The Intel 8086 microprocessor uses a variety of signals to communicate with memory, I/O
devices, and other components. These signals are categorized as:

●​ Address/Data Lines (AD0–AD15): These are time-multiplexed and used to send

addresses during the first part of a bus cycle and data during the second part.
●​ Address Lines (A16–A19): These lines carry the higher 4 bits of the 20-bit address.
●​ Control Signals: These include RD (Read), WR (Write), ALE (Address Latch Enable),
DT/R (Data Transmit/Receive), and DEN (Data Enable), used for data and address flow
control.
●​ Status Signals (S0, S1, S2): Provide information about the current operation.
●​ Interrupt Signals: Include INTR (Interrupt Request), NMI (Non-Maskable Interrupt), and
INTA (Interrupt Acknowledge).
●​ Clock and Reset: CLK provides timing to synchronize operations, while RESET
initializes the processor.
●​ MN/MX (Minimum/Maximum mode): Decides how control signals are
managed—internally (min) or with external bus controller (max).
 19

2. Basic Configurations

The 8086 can be configured in two modes:

●​ Minimum Mode: Used for single-processor systems. The processor generates all
necessary control signals internally. Ideal for simple designs.
●​ Maximum Mode: Designed for multiprocessor environments. The 8086 relies on an
external bus controller (Intel 8288) to generate control signals. This mode supports
co-processors and other CPUs, enabling multitasking or distributed processing.

3. System Bus Timing

System bus timing defines how data and instructions move across the buses during read/write
cycles. Each bus cycle consists of at least four clock periods:

●​ T1: The processor places the address on the bus and asserts ALE.
●​ T2: The control signal (RD or WR) is activated.
●​ T3: Data is transferred (read or write) from memory or I/O device.
●​ T4: The bus is idle or prepared for the next operation.​
Wait states (Tw) may be added between T3 and T4 if a slow device is involved.

4. System Design Using 8086

Designing a microprocessor system involves connecting the 8086 to memory and I/O devices
through buses and control logic. Key components include:

●​ Latch (e.g., 74LS373): Used to separate address from the multiplexed AD0–AD15 lines.
●​ Transceiver (e.g., 74LS245): Allows bidirectional data flow between CPU and
memory/I/O.
●​ Decoder (e.g., 74LS138): Selects memory or I/O devices based on address.
●​ Clock generator (8284): Provides synchronized clock pulses.​
Designers must ensure proper address decoding, control signal timing, and data
routing.
 20

5. I/O Programming

Input/output programming involves interacting with external devices using software. The 8086
supports:

●​ Isolated I/O: Uses IN and OUT instructions with a separate 64K I/O address space.
●​ Memory-mapped I/O: Uses regular memory instructions to access I/O devices. Devices
are assigned memory addresses.​
I/O programming involves polling (checking device status in a loop) or interrupts (device
signals processor when ready), depending on application requirements.

6. Introduction to Multiprogramming

Multiprogramming is a technique where multiple programs share CPU time and memory.
Although the 8086 doesn’t support true multitasking, it can implement multiprogramming using
software techniques. By storing the state of one program (register values, stack) and switching
to another, the CPU can give the illusion of concurrent execution. It improves CPU utilization
and response time in systems with frequent I/O operations.

7. System Bus Structure

The system bus is a group of wires that carry data, addresses, and control signals between the
processor, memory, and I/O devices. It has three main parts:

●​ Address Bus: Carries the address of the memory or I/O device (8086 has 20-bit
address bus, so it can access 1MB memory).
●​ Data Bus: Transfers actual data (16-bit in 8086).
●​ Control Bus: Carries control signals like read/write, interrupt requests, and clock pulses.​
This shared bus structure ensures coordinated communication in a
microprocessor-based system.

8. Multiprocessor Configurations

Multiprocessor systems use multiple processors to perform tasks in parallel, improving speed
and reliability. In 8086 maximum mode:

●​ One 8086 can act as the master, while others are slaves.
●​ Communication occurs over the system bus.
●​ Control signals and arbitration logic determine which processor accesses memory or I/O
at a given time.​
Shared memory or message-passing techniques manage inter-processor
communication and resource allocation.
 21

9. Coprocessor

A coprocessor is an additional processor that works alongside the main CPU to handle
specialized tasks. The Intel 8087 is the coprocessor for the 8086 and performs complex
arithmetic operations, especially floating-point calculations. The 8086 identifies coprocessor
instructions through a special escape opcode (ESC), and the 8087 executes them concurrently.
This parallelism enhances computational efficiency, particularly in scientific and engineering
applications.

10. Closely Coupled and Loosely Coupled Configurations

●​ Closely Coupled Systems: Multiple processors share the same memory and are tightly
integrated with a common clock and bus. Communication is fast and synchronization is
easier, but complexity and cost increase.
●​ Loosely Coupled Systems: Each processor has its own memory and communicates
via messages over a bus or network. These systems are more flexible and fault-tolerant,
commonly used in distributed computing environments.

11. Introduction to Advanced Processors

After the 8086, Intel introduced more advanced processors with enhanced capabilities:

●​ 80286: Introduced protected mode and better memory management.

●​ 80386: A 32-bit processor supporting multitasking and virtual memory.
●​ 80486: Integrated math coprocessor (FPU) and pipelining for faster execution.
●​ Pentium series: Introduced superscalar architecture and parallel instruction execution.​
Advanced processors provide improved speed, multitasking, power efficiency, and
support for modern operating systems, far surpassing the 8086 in terms of architecture
and performance.

H
 22

UNIT - III: I/O INTERFACING

1. Memory Interfacing and I/O Interfacing

Memory interfacing refers to connecting RAM or ROM to the 8086 microprocessor so it can read
from or write to memory locations. This requires address decoding to ensure that specific
address ranges access particular memory chips. Control signals like RD and WR are used to
manage data transfer. I/O interfacing allows the microprocessor to interact with peripheral
devices such as switches, LEDs, displays, or sensors. The 8086 supports two types of I/O
interfacing: Isolated I/O, where separate instructions (IN and OUT) are used to access I/O ports
with a separate address space; and Memory-Mapped I/O, where I/O devices are treated as
memory locations, allowing regular memory instructions to be used.

2. Parallel Communication Interface

Parallel communication transfers multiple bits of data simultaneously across multiple data lines.
The Intel 8255 Programmable Peripheral Interface (PPI) is widely used for parallel data
communication with 8086. It has three 8-bit ports (Port A, Port B, and Port C) that can be
configured for input or output in different modes. It is particularly useful for applications that
require fast data transfer, such as controlling displays, motors, or sensors. Mode 0 is basic I/O,
Mode 1 provides handshaking, and Mode 2 allows bidirectional data transfer. Proper
programming of the control word register allows flexible I/O control.

3. Serial Communication Interface

In serial communication, data is sent one bit at a time through a single data line. The Intel 8251
USART (Universal Synchronous/Asynchronous Receiver Transmitter) is used to manage
serial communication with the 8086. It supports both synchronous (with a clock) and
asynchronous (without clock) modes. Serial communication is slower than parallel but suitable
for long-distance and low-pin applications like modem interfaces, RS232 connections, and
inter-computer communication. Data framing, baud rate control, and status checking are
handled by the 8251 chip.

4. D/A and A/D Interface

The 8086 microprocessor can only process digital data. To interface with the analog world,
Digital-to-Analog Converters (DACs) and Analog-to-Digital Converters (ADCs) are used.
DACs (like DAC0808) convert digital data from the microprocessor into corresponding analog
voltage or current. ADCs (like ADC0804 or ADC0809) take analog input (like from a temperature
sensor) and convert it into digital format for processing by the microprocessor. Control signals
like Start Conversion (SC), End of Conversion (EOC), and Output Enable (OE) are used during
the A/D conversion process.
 23

5. Timer

Timers are essential for tasks that require accurate time delays or counting events. The Intel
8253/8254 Programmable Interval Timer has three independent 16-bit counters and can be
used in applications like generating time delays, producing waveforms, or counting pulses. Each
counter can operate in six different modes, such as interrupt on terminal count, hardware
retriggerable one-shot, or square wave generator. It is clocked by an external clock signal and
controlled using control words programmed by the CPU.

6. Keyboard/Display Controller

The Intel 8279 is a special-purpose chip designed to handle keyboard and display interfacing. It
relieves the CPU from the tasks of scanning and refreshing. The chip can scan up to 64-key
keyboards and control up to 16-digit 7-segment LED displays. It handles key debouncing, key
code generation, and provides FIFO buffers for storing keystrokes. For display, it continuously
refreshes the display using time-multiplexing without CPU intervention, making it efficient for
digital clocks, calculators, and embedded displays.

7. Interrupt Controller

Interrupts allow devices to get the processor’s attention asynchronously. The Intel 8259
Programmable Interrupt Controller (PIC) manages multiple interrupt sources and prioritizes
them. It supports eight interrupt inputs and can be cascaded to handle up to 64 interrupts. It
sends an interrupt request (INTR) to the CPU and receives an interrupt acknowledge (INTA)
in response. It supports programmable priority levels, masking of interrupts, and vectoring
(providing the address of the interrupt service routine). It is essential for responsive systems
handling multiple I/O devices.

8. DMA Controller

The Direct Memory Access (DMA) technique allows peripherals to directly read/write memory
without CPU involvement, increasing data transfer efficiency. The Intel 8237 DMA Controller is
commonly used with the 8086 for this purpose. It allows block data transfer between I/O and
memory. The controller takes over the system buses during transfer and signals the CPU via
HOLD and HLDA pins. Modes include block, demand, and single transfer, which are useful for
high-speed devices like hard drives and sound cards.

9. Programming and Applications

Programming for I/O interfacing includes writing assembly routines to configure and control
interface devices like the 8255, 8279, or 8253. Programs involve setting control words,
reading/writing ports, and managing handshaking. Applications may include automation,
measurement systems, and communication devices. The programs typically involve initializing
devices, polling or using interrupts to handle data, and storing or displaying results. Efficient I/O
 24

programming enables responsive and robust embedded systems.

10. Case Studies

●​ Traffic Light Control: A common application where the 8086, in conjunction with 8255
and timers, controls Red, Yellow, and Green LEDs in a sequence with time delays. This
simulates a real traffic light system.
●​ LED Display Interface: Uses 8255 to control LED matrices or 7-segment displays by
sending appropriate patterns to illuminate segments or pixels.
●​ LCD Display Interface: LCDs require control signals (RS, RW, EN) and data input. The
microprocessor sends commands (like clear, display on) and characters to display. LCDs
can show alphanumeric messages and are widely used in embedded systems.
●​ Keyboard Display Interface: Using 8279, a keyboard is scanned and inputs are stored
in FIFO. The same chip controls display output, allowing the creation of interactive
embedded systems.
●​ Alarm Controller: Interfaces sensors with the microprocessor to detect faults or
abnormal conditions (like smoke or heat). When triggered, it can activate an alarm using
a relay, buzzer, or siren. Interrupts can be used to signal the CPU immediately when
danger is detected.

Unit IV | Part A: MICROCONTROLLER – 8051

1. Architecture of 8051

The 8051 microcontroller, developed by Intel, is an 8-bit microcontroller widely used in

embedded systems. It has a Harvard architecture, meaning separate memory for program and
data. The 8051 consists of 128 bytes of internal RAM, 4KB of ROM (on-chip), two 16-bit timers,
four parallel I/O ports (each 8-bit wide), a full-duplex serial port, and five interrupt sources. It has
an 8-bit ALU, a program counter, a stack pointer, and several special function registers (SFRs)
to manage internal operations. The crystal oscillator is usually 11.0592 MHz, making it
compatible with standard baud rates.

2. Special Function Registers (SFRs)

SFRs are registers used to control internal operations of the 8051. These include:

●​ ACC (Accumulator) and B register for arithmetic.

●​ PSW (Program Status Word) for flags.
●​ SP (Stack Pointer), DPTR (Data Pointer) for addressing.
●​ TCON, TMOD for timer control.
●​ SCON, SBUF for serial communication.
●​ IE, IP for interrupts.
 25

●​ Port registers: P0, P1, P2, P3.​

These are memory-mapped to the upper 128 bytes of the internal RAM (addresses 80H
to FFH).

3. I/O Pins, Ports and Circuits

The 8051 has 4 I/O ports (P0 to P3), each 8-bit wide. These ports can be programmed as input
or output:

●​ Port 0 (P0) is open-drain and requires external pull-up resistors.

●​ Port 1 (P1) is used for general I/O.
●​ Port 2 (P2) is also used for I/O or as high byte of address bus.
●​ Port 3 (P3) has alternate functions like RxD, TxD, INT0, INT1, T0, T1, WR, and RD.​
Each pin uses a latch and buffer system to control input/output behavior. Proper logic
levels and direction settings are crucial for interfacing.

4. Instruction Set

The 8051 instruction set is classified into:

●​ Data transfer instructions (MOV, XCH, PUSH, POP),

●​ Arithmetic instructions (ADD, SUBB, INC, DEC),
●​ Logical instructions (ANL, ORL, XRL, CLR, CPL),
●​ Branching instructions (SJMP, LJMP, AJMP, JC, JNC),
●​ Bit manipulation instructions (SETB, CLR, MOV C).​
The instruction set is simple and optimized for control-based applications. Instructions
range from 1 to 3 bytes in size and vary in execution cycles.

5. Addressing Modes

8051 supports the following addressing modes:

●​ Immediate: Operand is given in the instruction (e.g., MOV A, #25H).

●​ Register: Operand in a register (e.g., MOV A, R0).
●​ Direct: Address of operand is directly given (e.g., MOV A, 30H).
●​ Indirect: Uses registers (e.g., MOV A, @R0).
●​ Indexed: Used for accessing look-up tables in code memory (e.g., MOVC A, @A+DPTR).​
Understanding these modes is crucial for efficient assembly programming.
 26

6. Assembly Language Programming

Assembly programming in 8051 involves:

●​ Initializing ports, timers, and peripherals.

●​ Using labels, instructions, and assembler directives (e.g., ORG, END, DB, DW).
●​ Writing control loops using JMP, CALL, RET, etc.​
Programs should be efficient, with well-defined comments and structure. Examples
include LED blinking, counter, keypad reading, and serial data handling.

Part B: INTERFACING MICROCONTROLLER

7. Programming 8051 Timers

The 8051 has two timers: Timer 0 and Timer 1, each of 16 bits. They can work in different
modes (Mode 0, 1, 2, 3):

●​ Mode 1: 16-bit timer mode

●​ Mode 2: 8-bit auto-reload​
Timers are initialized using TMOD and controlled via TCON. They can be used for delay
generation, waveform creation, and clock event timing.

8. Serial Port Programming

Serial communication is handled using SCON and SBUF registers. 8051 supports full-duplex
communication using UART. Mode 1 (8-bit UART) is the most common. The baud rate is set
using Timer 1 in auto-reload mode. For example, to transmit "A", we write to SBUF and wait for
the TI (Transmit Interrupt) flag.

9. Interrupts Programming

8051 has five interrupt sources: two external (INT0, INT1), two timers (T0, T1), and one
serial. The IE (Interrupt Enable) and IP (Interrupt Priority) registers are used to configure
them. Interrupts can be used to execute a routine when an event occurs, such as keypress,
timer overflow, or incoming data, improving program efficiency.

10. LCD and Keyboard Interfacing

LCDs (e.g., 16x2) are interfaced using data lines (D0-D7) and control lines (RS, RW, EN).
Commands (clear, shift, cursor) and data (characters) are sent through ports. Keyboards
(typically 4x4 matrix) are scanned by sending rows low and reading columns. Debouncing and
 27

scanning logic are implemented in software.

11. ADC, DAC and Sensor Interfacing

ADC interfacing allows analog signals (from sensors) to be converted to digital values readable
by the 8051. ADC0804 is a commonly used chip, interfaced via 8255 or ports. DACs convert
digital values from 8051 to analog output, useful for generating audio signals or voltage levels.
Sensors like temperature, light, or motion sensors are used with ADCs to provide input to the
microcontroller system.

12. External Memory Interface

The 8051 can be connected to external program or data memory when internal memory is
insufficient. Port 0 and Port 2 are used for address/data multiplexing. The ALE signal is used to
latch the lower address byte. External RAM or ROM chips like 6264 (RAM) or 2764 (EPROM)
are commonly used.

13. Stepper Motor and Waveform Generation

Stepper motors are used in precise motion control applications. The 8051 can control a
stepper motor by sending a sequence of pulses to the driver circuit (ULN2003 or L293D).
Proper timing and direction control are handled in code. For waveform generation, timers and
DACs are used to produce square, triangular, or sine waves. This is useful in signal generation
or testing applications.