Module1-Lecture14-15

Inverter-Static Characteristics

SIT 1 8/23/2020
Bhubaneswar
 Introduction (1)
 Logic symbol & truth  Ideal voltage transfer
table characteristic (VTC)

2 SIT Bhubaneswar
 nMOS Inverter: Schematic & VTC

 VOH : VOUT,MAX when the output level is logic "1“

 VOL : VOUT,MIN when the output level is logic "0“
 VIL : VIN,MAX which can be interpreted as logic "0“
 VIH : VIN,MIN which can be interpreted as logic "1"
3 SIT Bhubaneswar
 Noise Margin

NM L  VIL  VOL
NM H  VOH  VIH

4 SIT Bhubaneswar
 nMOS Inverter: Power & Area
 Power Considerations
PDC  VDD  I DC
VDD
PDC    I DC Vin  low  I DC Vin  high  
2

5 SIT Bhubaneswar
 Resistive-Load Inverter
 Resistive-load inverter circuit & its VTC

1) Vin<VT0, nMOS off

2) Vin>VT0, nMOS in sat. 3) Vout<VDSAT, nMOS in lin.
kn 1
(Vin  VT 0 )2 IR   2  (Vin  VT 0 ) Vout  Vout 2 
I R  W  vsat  Cox  2  Vout 
(Vin  VT 0 )  EC L  1  
 EC Ln 

6 SIT Bhubaneswar
VOH, VOL Calculation of Resistive-Load Inverter
 VOH calculation
Vin<VT0, nMOS off
Vout  VDD  RL  I R VOH  VDD

 VOL calculation
Vin=VOH, nMOS in lin.
VDD  Vout VDD  VOL kn 1
IR    2  (VDD  VT 0 ) VOL  VOL 2 
RL RL 2  VOL 
 1  
 EC Ln 
VDD  VOL kn  1  2
  2  (VDD  VT 0 ) VOL  VOL 
2
V 2
OL  2  
 DD T 0
V V   VOL  VDD  0
RL 2  kn RL  kn RL

2
1  1  2VDD
VOL  VDD  VT 0    VDD  VT 0   
kn RL  kn RL  kn RL

7 SIT Bhubaneswar
VIL, VIH Calculation of Resistive-Load Inverter (1)
 VIL calculation (nMOS in sat.)
VDD  Vout (Vin  VT 0 )2
 W  vsat  Cox 
RL (Vin  VT 0 )  EC L

≒
VDD  Vout kn
  (Vin  VT 0 )2
RL 2
-1
Diff. 1 dVout
   kn  Vin  VT 0 
RL dVin

1
   1  kn  VIL  VT 0 
RL
1
VIL  VT 0 
kn RL

8 SIT Bhubaneswar
VIL, VIH Calculation of Resistive-Load Inverter (2)
 VIH calculation VDD  Vout kn 1
  2  (Vin  VT 0 ) Vout  Vout 2 
nMOS in lin. RL 2  Vout 
1   small (5.24)
 EC Ln 
VDD  Vout kn
  2  (Vin  VT 0 ) Vout  Vout 2 
RL 2
-1
Diff. 1 dVout kn  dV dV 
     2  Vin  VT 0   out 2Vout  2Vout  out 
RL dVin 2  dVin dVin 
(5.27)
1 1
   1  kn  VIH  VT 0    1  2Vout  VIH  VT 0  2Vout 
RL kn RL

VDD  Vout kn   1  
into (5.24)    2   VT 0  2Vout   VT 0  Vout  Vout
2

RL 2   kn RL  

2 VDD
Vout Vin  VIH   
3 kn RL
8 VDD 1
into (5.27) VIH  VT 0   
3 kn RL kn RL

9 SIT Bhubaneswar
 VTC, Power & Chip Area
 VTC of the resistive-load  Power & chip area
inverter for different (kn∙RL)
VDD  VOL
ID  IR 
RL
VDD VDD  VOL
P DC  average   
2 RL

10 SIT Bhubaneswar
 Example 5.1 - Inverter Design
 Resistive-load inverter circuit
 VDD=1.2V, kn’=98.2μA/V2, ECL=0.45V, VT0=0.53V
 VOL=80mV
 Determine ① (W/L) ratio of the driver Tr. ② RL
VDD  VOL kn'  W
  2  (VDD  VT 0 )  VOL  VOL 2  Assuming VOL = 80 mV
 1
  
RL 2 L   VOL 
1  
 EC Ln 
1.2  0.08 98.2  106 W
RL

2
 
1
L 1  0.08
 
 2  0.67  0.08  0.082 W
 RL  2.63  105 
L
0.45
(W/L)-Ratio Load resistor (RL[kΩ]) DC power consumption (PDC,avg.[μW])
1 263.0 2.56
2 131.5 5.11
3 87.7 7.67
4 65.8 10.2
5 52.6 12.8
6 43.8 15.3

11 SIT Bhubaneswar
 Example 5.2 - Inverter Design
 Resistive-load inverter circuit
 VDD=1.2V, kn’=102μA/V2
 VT0=0.48V, RL=20kΩ, W/L=4
 Calculate (VOL, VOH, VIL, VIH)
 Find the noise margins

VOH  VDD  1.2V kn = kn' (W/L) = 408 μA/V2, (kn∙RL) = 8.16 V-1.
2
1  1  2VDD 1 1
VOL  VDD  VT 0    VDD  VT 0    VIL  VT 0   0.48   0.603V
kn RL  kn RL  kn RL kn RL 8.16

 1  2 1.2
2 8 VDD 1 8 1.2 1
 1.2  0.48 
1
 1.2  0.48  VIH  VT 0     0.48     0.984V
  3 kn RL kn RL 3 8.16 8.16
8.16  8.16  8.16

NM L  VIL  VOL  0.603  0.198  0.405V Poor noise immunity

 0.198V

NM H VOH  VIH  1.2  0.984  0.216V < 0.3V = 25% of VDD

12 SIT Bhubaneswar
 Inverters with MOSFET Load
 Enhancement-load
nMOS inverter

VDD

 Pseudo-nMOS Inverter
IL

ID Vout = VDS,driver

+
Vin = VGS,driver

13 SIT Bhubaneswar
 Pseudo-nMOS Inverter
 Operating mode of the pMOS transistor
 Vout : small → Vout < -VT0,p → |VDS,p | ≥ |VDSAT,p| (Saturation)

   
2 2
VSG , p  VT 0, p VDD  VT 0, p
I D , p  W  vsat  Cox   W  vsat  Cox 
V SG , p 
 VT 0, p  EC Lp V
DD 
 VT 0, p  EC Lp

 Vout : larger → Vout > VDD + VT,load (Linear region)

 
kp 1
I D, p   2  VDD  VT 0, p  VDD  Vout   VDD  Vout 2 
2  VDD  Vout  
1  
 EC Ln 

 ID,n=ID,p, VGS,n=Vin, and VDS,n = Vout

14 SIT Bhubaneswar
VOH, VOL Calculation of Pseudo-nMOS Inverter
VDD

 VOH calculation : VOH = VDD

IL

+
Vout VDS,driver

 VOL calculation
=
ID

+
Vin = VGS,driver

 
2
VDD  VT 0, p
 2  VOH  VT 0,n  VOL  VOL 2   W  vsat  Cox 
kn 1
2 
1 
VOL 


small

 
VDD  VT 0, p  EC , p Lp
 EC ,n Ln 

 
2
k  VDD  VT 0, p
V  VT 0,n    p
2
VOL  VOH  VT 0,n    EC , p  Lp 
OH
 kn   
VDD  VT 0, p  EC , p Lp

 nMOS size > pMOS size → VOL : lower → good noise margin
( NM L  VIL  VOL )

15 SIT Bhubaneswar
 VIL, VIH Calculation of Pseudo-nMOS Inverter
V  VT 0,n 
2

Wn  vsat  Cox 
in

 VIL calculation
EC ,n Ln

 
kp
   2 VDD  VT 0, p  VDD  Vout   VDD  Vout  
2

2  
V  VT 0,n  Diff.
2

Wn  vsat  Cox  -1
in

Vin  VT 0,n   EC ,n Ln kn  Vin  VT 0,n 

  dV   dVout  

kp

2  VDD  Vout
1

 
  2 VDD  VT 0, p  VDD  Vout   VDD  Vout  

2

 
 k p   VDD  VT 0, p   1   out   VDD  Vout    
  dVin   dVin  
1  
 EC , p Lp 
VDD

 
kp
VIL  VT 0,n   Vout  VT 0, p
kn

 VIH calculation IL

ID Vout = VDS,driver

 
2
VDD  VT 0, p +
 2  Vin  VT 0,n  Vout  Vout 2   W  vsat  Cox 
kn 1
 
 
Vin = VGS,driver
2  Vout  VDD  VT 0, p  EC , p Lp
1  
 EC ,n Ln  -1
Diff.   dV   dV
kn  Vin  VT 0,n    out   Vout  Vout   out

 
k
 2  Vin  VT 0,n  Vout  Vout 2   p  VDD  VT 0, p   0
kn 2

2  2   dVin   dVin 

VIH  VT 0,n  2Vout

16 SIT Bhubaneswar
 Design of Pseudo nMOS Inverters
& Power/Area Considerations
 Design of pseudo nMOS inverters
W 
kn'  
  
2
kn VDD  VT 0, p k L n
kR   kR  n 
k p 2  VOH  VT 0,n  VOL  VOL 2 kp W 
k p'   
L p
 Power and area considerations
V 
VDD
2
DD  VT 0, p
I DC (Vin  VDD )  W  vsat  Cox 
V 
pMOS

 VT 0, p  EC , p Lp
transistor
n-well
DD

 2  VOH  VT 0,n  VOL  VOL 2 

kn 1
  
2  VOL  Output

1  
 EC ,n Ln 
nMOS
transistor

V 
2
VDD DD  VT 0, p
PDC  W  vsat  Cox  Input

2  
VDD  VT 0, p  EC , p Lp GND

17 SIT Bhubaneswar
Example 5.3 Pseudo-nMOS Inverter Circuit (1)

 Calculate VOL, VOH, VIL, VIH.

 Find the noise margins.
 VDD=1.2V, VT0,n=0.58V, VT0,p=–0.56V, vsat,n=124340m/s
 (W/L)n = 12, (W/L)p = 3, Ln=Lp=40nm, Cox,n=2.20X10-2F/m2
 kn’= 94.3μA/V2, kp’=41μA/V2, EC,pLp=1.8V, EC,nLn=0.4V

V 
2
k  DD  VT 0, p
VOH=VDD=1.2 V V  VT 0,n    p
2
VOL  VOH  VT 0,n    EC , p  Lp 
OH
 kn   
VDD  VT 0, p  EC , p Lp

0.12 (1.2  0.56)2

 1.2  0.58  (1.2  0.58)  2
 1.8   0.028V
1.08 (1.2  0.56)  1.8

 
kp
VIL  VT 0,n   Vout  VT 0, p
kn
 0.518  0.111Vout Vout  9VIL  4.66

18 SIT Bhubaneswar
Example 5.3 Pseudo-nMOS Inverter Circuit (2)
V  VT 0,n 
2

 
kp
Wn  vsat  Cox     2 VDD  VT 0, p  VDD  Vout   VDD  Vout  
in 2

EC ,n Ln 2  

3.28 103  Vin  0.58   6 105   2 1.2  0.56   1.2  9VIL  4.66   1.2  9VIL  4.66  
0.517V
VIL  
2 2
 
0.644V

VIH  VT 0,n  2Vout Vout  0.5 VIH  0.5VT 0,n  0.5VIH  0.29

 
2
VDD  VT 0, p
 2  Vin  VT 0,n  Vout  Vout 2   W  vsat  Cox 
kn 1
2 
 1 
Vout 


small


VDD  VT 0, p  EC , p Lp 
 EC ,n Ln 
 
k
 2  Vin  VT 0,n  Vout  Vout 2   p  VDD  VT 0, p
kn 2

2   2

0.334V
5.4 10   2  VIH  0.58    0.5VIH  0.29    0.5VIH  0.29    6 105  1.2  0.56 
4

2

2
VIH  
0.826V
NM H  VOH  VIH  1.2  0.826  0.374 V
NM L  VIL  VOL  0.644  0.029  0.615V

19 SIT Bhubaneswar
 CMOS Inverter

 Circuit operation
VGS ,n  Vin VSG , p  VDD  Vin
VDS ,n  Vout VSD , p  VDD  Vout

I D,n  I D, p  0 Vout  VOH  VDD

Vout  VOL  0

Saturation p/nMOS for Vin & Vout

VDS ,n  VDSAT ,n  Vout  VDSAT ,n

VSD, p  VDSAT , p  VDD  Vout  VDSAT , p

20 SIT Bhubaneswar
 VIL Calculation of CMOS Inverter
V GS , n  VT 0, n 
2

 VIL calculation Wn  vsat  Cox 

V  VT 0,n   EC ,n Ln
GS , n

 
  2 VSG , p  VT 0, p  VSD , p  VSD , p  
kp 1 2
 
2  VSD , p   
1  
V  VT 0,n 
2

 E L 
Wn  vsat  Cox 
in C , p p

V
in  VT 0,n   EC ,n Ln

 
kp 1
    2 VDD  Vin  VT 0, p  VDD  Vout   VDD  Vout  
2

2  VDD  Vout   
1  
 EC , p Lp 
-1
Diff.   dV
kn  Vin  VT 0,n   k p  Vin  VDD  VT 0, p    out

 Vin  VT 0,n    Vout  VDD 
kn 2

2   dVin 
 
k
 p   2 VDD  Vin  VT 0, p  VDD  Vout   VDD  Vout  
2
 dV  
2    Vout  VDD    out  
 dVin  

2Vout  VT 0, p  VDD  k RVT 0,n

kn  VIL  VT 0,n   k p   2Vout  VIL  VT 0, p  VDD  VIL 
1  kR

21 SIT Bhubaneswar
 VIH Calculation of CMOS Inverter

 VIH calculation
  2  VGS ,n  VT 0,n   VDS ,n  VDS ,n 2    2  Vin  VT 0,n   Vout  Vout 2 
kn 1 kn 1
 
2  Vout  2  Vout 
1   1  
 EC ,n Ln   EC ,n Ln 
   
2 2
VSG , p  VT 0, p VDD  Vin  VT 0, p
 W  vsat  Cox   W  vsat  Cox 
V
SG , p 
 VT 0, p  EC , p Lp V
DD 
 Vin  VT 0, p  EC , p Lp

-1
Diff.   dV   dV  
kn  Vin  VT 0,n    out   Vout  Vout   out  
 
k
  2  Vin  VT 0,n  Vout  Vout 2   p  VDD  Vin  VT 0, p
kn 2

2 2   dVin   dVin  

 k p  VDD  Vin  VT 0, p 

VDD  VT 0, p  k R   2Vout  VT 0,n 

kn   VIH  VT 0,n  2Vout   k p  VIH  VDD  VT 0, p  VIH 
1  kR

22 SIT Bhubaneswar
Vth Calculation of CMOS Inverter: Method 1

 Vth calculation Definition : Vth = Vin = Vout

 
Wn  Cox  VGS ,n  VT 0,n  VDS ,sat ,n   vsat ,n  Wp  Cox  VSG , p  VT 0, p  VSD,sat , p  vsat , p

 
Wn  Cox  Vin  VT 0,n  VDS ,sat ,n   vsat ,n  Wp  Cox  VDD  Vin  VT 0, p  VSD,sat , p  vsat , p


Vin  1     VT 0,n  VDS , sat ,n    VDD  VT 0, p  VSD,sat , p  where    
vsat , p
vsat ,n

k p  EC , p
kn  EC ,n

1 EC , p

kR EC ,n
W
,  p
Wn

VT 0,n  VDS , sat ,n 

1 EC , p

k R EC ,n

 VDD  VT 0, p  VSD , sat , p  V  VT 0,n   EC ,n  Ln
Vth  where VDS ,sat ,n  th

 1 EC , p
1  


V th  VT 0,n   EC ,n  Ln
 k R EC ,n 

VSD , sat , p 
V DD 
 Vth  VT 0, p  EC , p  Lp

V DD  Vth  VT 0, p  E C, p  Lp

23 SIT Bhubaneswar
Vth Calculation of CMOS Inverter: Method 2

 Vth calculation for easier hand analysis

V  VT 0,n  V  VT 0,n   
2 2
VDD  Vin  VT 0, p
2

Wn  vsat ,n  Cox 
in
Wn   Wp 
in

V
in  VT 0,n   EC ,n Ln EC ,n Ln EC , p Lp

V 
2
DD  Vin  VT 0, p
 Wp  vsat , p  Cox 
V DD 
 Vin  VT 0, p  EC , p Lp

 
Vin  1    VT 0,n    VDD  VT 0, p  
Wp EC ,n  Ln Wp  EC ,n
where   
Wn EC , p  Lp Wn  EC , p

VT 0,n 
1
kR

 VDD  VT 0, p 
Vth 
 1 
 1  
 kR 

24 SIT Bhubaneswar
 Design of CMOS Inverters (1)
 Designing CMOS inverter : Setting Vth to a desired voltage value
Vth  VT 0,n  VDS , sat ,n

Vth  VT 0,n  VDS , sat ,n    VDD  VT 0, p  VSD,sat , p  Vth  
VDD  VT 0, p  VSD , sat , p  Vth

1 EC , p

kR EC ,n
1
Vth,ideal  VDD
kn  VDD  VT 0, p  VSD , sat , p  Vth   EC , p  2  kn   0.5VDD  VT 0, p  VSD , sat , p   EC , p 
        
k p  Vth  VT 0,n  VDS , sat ,n   EC ,n    EC ,n
   p ideal  0.5VDD  VT 0,n  VDS ,sat ,n
k
 

W  W 
nCox    n   
 kn  E kn L n L n EC , p
   C, p , kp

W 

W 

EC ,n
 kp inverter
symmetric EC ,n
 p Cox    p  
L p L p

W 
 
 L n  p  EC , p W  n  EC ,n  W 
     
W  n  EC ,n  L  p  p  EC , p  L n
 
 L p

25 SIT Bhubaneswar
 Design of CMOS Inverters (2)
 If symmetric CMOS inverter with VT0,n = |VT0,p| and kR = 1,

VIL    3VDD  2VT 0,n 

1
8

VIH    5VDD  2VT 0,n 

1
8

VIL  VIH  VDD

in a symmetric inverter

NM L  VIL  VOL  VIL

NM H  VOH  VIH  VDD  VIH

NM L  NM H  VIL

26 SIT Bhubaneswar
 Example 5.4 - CMOS Inverter (1)

 Calculate the noise margins

 VDD=1.2V, VT0,n=0.48V, VT0,p=–0.46V
 kn=982µA/V2, kp=653µA/V2, vsat,n=124340m/s
 EC,nLn=0.4V, EC,pLp=1.8V

kR = 1.503, VT0,n ≠ |VT0,p| → not a symmetric inverter

2Vout  VT 0, p  VDD  k R VT 0,n
VIL 
1 kR
VOL=0 & VOH=1.2 V
2Vout  0.46  1.2  1.503  0.48
  0.799Vout  0.375
1  1.503

9.82×10-4 6.53×10-4 é 2ù
( ) ( )( ) ( )
2
× 0.799Vout -0.375- 0.48 @ × ê2 1.2 - 0.799Vout + 0.375- 0.46 × 1.2 - Vout - 1.2 - Vout ú
2 2 ë û

-0.322V
2
0.362Vout  0.306Vout  0.137  0 Vout  

1.171V

27 SIT Bhubaneswar
 Example 5.4 - CMOS Inverter (2)
VIL  0.799 1.171  0.375  0.560V

VDD  VT 0, p  k R   2Vout  VT 0, n 
VIH 
1 kR
1.2  0.46  1.503  2Vout  0.48 
 1.201Vout  0.584
1  1.503

1.5  2  1.201Vout  0.584  0.48  Vout  Vout 2   1.2 1.201Vout  0.584  0.46 
2

1.068V

0.665Vout 2  0.687Vout  0.024  0 Vout  

0.034V

VIH  1.201 0.034  0.584  0.625V

NM L  VIL  VOL  0.560V

NM H  VOH  VIH  0.575V

28 SIT Bhubaneswar
 Sizing Trends of CMOS Inverter w/ Small
Geometry Devices (2)
0.62
0.61
0.60

Vth (V)
0.59
 = 2.58
0.58
0.57
0.56

Propagation delay (ps)

28
26
tPHL
24
tP
22
 = 2.19
20
 = 1.4
18 tPLH
16
14

60
Rise & fall time (ps)

55
50
tfall
45
40  = 2.02
35
30
trise
25

0.55
0.54
Noise Margin (V)

0.53
0.52 NMH
0.51  = 2.48
0.50
0.49
0.48 NML
0.47
0.46
0.45
1.0 1.5 2.0 2.5 3.0 3.5 4.0
 ratio

29 CMOS Digital Integrated Circuits – 4th Edition

SIT Bhubaneswar
 Supply Voltage Scaling in CMOS Inverters
 Effects of VDD scaling upon the static VTC of CMOS inverters
kT
VDD ,min  4
q

Hysteresis behavior for very low VDD

30 SIT Bhubaneswar
 Power and Area Considerations
 DC power dissipation : leakage
 Dynamic power dissipation : Ch. 6 & 11

 Layouts of CMOS inverters

 Comparison with other general inverters

 Advantages : Don't occupy significantly more area.
 Drawbacks : Added Complexity of the fabrication process
(n-well diffusion, separate p-type and n-type source, drain diffusions, etc.)

 Comparison of CMOS random logic with nMOS random logic

 Advantages : low power dissipation & low heat generation
 Drawbacks : more transistors

31 SIT Bhubaneswar