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Noise Margin

This document describes the design and analysis of three types of inverter circuits: CMOS, Pseudo-NMOS, and resistive load. It involves calculating the noise margins and performing power analysis. Schematics are presented for each inverter along with their voltage transfer characteristics and critical voltage values. Noise margins are calculated using the high and low output voltages and input voltage thresholds. Power consumption is analyzed and tabulated for each inverter circuit when connected to different resistive loads. The aim is to design and analyze the inverters to calculate noise margins and perform power analysis.

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Harreni
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319 views6 pages

Noise Margin

This document describes the design and analysis of three types of inverter circuits: CMOS, Pseudo-NMOS, and resistive load. It involves calculating the noise margins and performing power analysis. Schematics are presented for each inverter along with their voltage transfer characteristics and critical voltage values. Noise margins are calculated using the high and low output voltages and input voltage thresholds. Power consumption is analyzed and tabulated for each inverter circuit when connected to different resistive loads. The aim is to design and analyze the inverters to calculate noise margins and perform power analysis.

Uploaded by

Harreni
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EXP NO: CALCULATION OF NOISE MARGIN AND POWER ANALYSIS

DATE:

AIM:
To design the following circuits to calculate noise margin and perform power analysis.
1. CMOS inverter
2. Pseudo-NMOS inverter
3. Resistive Load inverter

TOOL USED:
Cadence Virtuoso v2016.1_14.11

CALCULATION OF NOISE MARGIN


1. CMOS INVERTER
1.1 SCHEMATIC OF CMOS INVERTER

Fig 1.1 Schematic of CMOS Inverter

1
1.2 VTC CHARACTERISTICS OF CMOS

Fig 1.2 Output Waveform of CMOS inverter

1.3 TABULATION OF CRITICAL VOLTAGE

VOLTAGES V0H VOL VIH VIL


VALUES in V

Fig 1.3 Critical voltages of CMOS inverter

1.4 CALCULATION OF NOISE MARGIN

NMH = VOH-VIH

NML = VIL-VOL

2
2. PSEUDO-NMOS INVERTER
2.1. SCHEMATIC PSEUDO-NMOS INVERTER

Fig 2.1 Schematic of Pseudo-NMOS Inverter


2.2 VTC CHARACTERISTICS OF PSEUDO-NMOS INVERTER

Fig 2.2 Output Waveform of Pseudo-NMOS Inverter

3
2.3 TABULATION OF CRITICAL VOLTAGE

VOLTAGES V0H VOL VIH VIL


VALUES in V

Fig 1.3 Critical voltages Pseudo-NMOS Inverter

2.4 CALCULATION OF NOISE MARGIN

NMH = VOH-VIH

NML = VIL-VOL

3. RESISTIVE LOAD INVERTER


3.1. SCHEMATIC RESISTIVE LOAD INVERTER

Fig 2.1 Schematic of Resistive Load Inverter

4
3.2 VTC CHARACTERISTICS OF RESISTIVE LOAD INVERTER

Fig 2.2 Output Waveform of Resistive Load Inverter


3.3 TABULATION OF CRITICAL VOLTAGE

VOLTAGES V0H VOL VIH VIL


VALUES in V

Fig 1.3 Critical voltages Resistive Load Inverter


2.4 CALCULATION OF NOISE MARGIN

NMH = VOH-VIH

NML = VIL-VOL

5
POWER ANALYSIS
4. CMOS INVERTER
4.1 SCHEMATIC OF CMOS INVERTER

Fig 4.1 Schematic of CMOS Inverter with resistive load

4.2. TABULATION OF POWER FOR INVERTERS

INVERTER R1 R2 R3 R4
CMOS
PSEUDO-NMOS
RESISTIVE LOAD

RESULTS
Thus, the inverter circuits have been designed and calculation of noise margin and power
analysis is performed.

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