CMOS DIGITAL VLSI DESIGN
CMOS INVERTER BASICS - I
SUDEB DASGUPTA
DEPARMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
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Outline
• Basic idea of CMOS inverter
• Switch model of inverter
• Static behavior
• Voltage transfer characteristics
• Switching threshold
• Noise margin
• Gain calculation
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CMOS INVERTER - Basic Idea
Figure : A static inverter with capacitive load
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CMOS INVERTER – switch model
When, Vin = Vdd, When, Vin = 0,
NMOS is on, NMOS is off,
PMOS is off, PMOS is on,
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CMOS INVERTER – static behavior
• High Noise margin, ideally equal to supply voltage
• Ratio-less logic level
• Low output impedance - less prone to noise
• High impedance - improve fanout
• No static power consumption
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CMOS INVERTER – voltage-transfer characteristics
I Dnmos
• CMOS Voltage- transfer characteristics can be
achieved by superimposing of drain current of
NMOS and PMOS onto a common co-ordinate
plot.
Assuming Vdd = 2.5
Vout
IDpmos Mirroring IDnmos Horizontal IDnmos
around x Vin=0 shift over Vin=0
axis Vdd
V =1.5 Vin=1.5
V DSpmos V DSpmos Vout
VGSp=-1 IDnmos = - IDpmos
Vin = 2.5 + VGSp Vout = 2.5 + VDSp
VGSp=-2.5
Transforming the PMOS I-V transfer characteristics onto same coordinate
CMOS INVERTER – voltage-transfer characteristics
ID n
Vin = 0 Vin = 2.5
PMOS Vin = 0.5 Vin = 2 NMOS
Vin = 1 Vin = 1.5
Vin = 1.5 Vin = 1
Vin = 1.5 Vin = 1
Vin = 2 Vin = 0.5
Vin = 2.5 Vin = 0
Vout
Source: Digital Integrated Circuits (2nd Edition)- Jan M. Rabaey
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CMOS INVERTER – voltage-transfer characteristics
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CMOS INVERTER – switching threshold
• Switching threshold VM can be obtained from the VTC graph, where Vin = Vout
• At this point both transistors are in saturation region.
• By ignoring channel length modulation, we can equate the transistor currents
VDSATn VDSATp
knVDSATn (VM VTn ) k pVDSATp (VM VDD VTp )0
2 2
VDSATn V k pVDSATp satpWp
(VTn ) r(VDD VTp DSATp )
2 2 Where, r k V
satnWn
VM n DSATn
1 r
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CMOS INVERTER – noise margin
• The characteristic of inverter which defines the allowable noise voltage on the
input of gate so that output will not be affected.
• The noise margin of an inverter is defined by Noise Margin Low (NML) and Noise
Margin High (NMH).
In this case,
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CMOS INVERTER – calculation of VIL
By Definition, when Vin = VIL , NMOS is in saturation region and PMOS is in linear region.
Kn Kp
dVout
1 I I (V V ) 2
[2(V V )V V 2
DSp ]
Also, dVin and Dn Dp
So, 2 GSn Tn
2
GSp Tp DSp
We know, VGSp Vin VDD and VDSp Vout VDD
Kn Kp
(Vin VTn )
2
[2(Vin VDD VTp )(Vout VDD ) (Vout VDD ) 2 ]
2 2
Taking derivative w.r.t Vin in both side to satisfy VIL condition.
Kn Kp dV dV
(Vin VTn ) [(Vin VDD VTp )( out ) (Vout VDD ) (Vout VDD )( out )]
2 2 dVin dVin
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CMOS INVERTER – calculation of VIL
Kn Kp dV dV
(Vin VTn ) [(Vin VDD VTp )( out ) (Vout VDD ) (Vout VDD )( out )]
2 2 dVin dVin
dVout
Putting, Vin VIL and dV 1
in
Kn
(VIL VTn ) K p (2Vout VIL VTp VDD )
2
2Vout VTp VDD K R VTn ) Kn
VIL Where, KR
1 KR Kp
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CMOS INVERTER – calculation of VIH
Similarly, when Vin = VIH , NMOS is in linear region and PMOS is in saturation region.
Kp Kp
(VGSp VTp )2 [2(VGSn VTn )VDSn VDSn 2 ]
2 2
Kp Kn
(Vin VDD VTp )2 [2(Vin VTn )Vout Vout 2 ]
2 2
Taking derivative w.r.t Vin in both side to satisfy VIH condition.
dVout dV
K p (Vin VDD VTp ) K n [(Vin VTn )( ) Vout Vout ( out )]
dVin dVin
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CMOS INVERTER – calculation of VIH
dVout dVout
K p (Vin VDD VTp ) K n [(Vin VTn )( ) Vout Vout ( )]
dVin dVin
dV
Putting, Vin VIH and dV 1
out
in
K p (VIH VDD VTp ) K n ( VIH VTn 2Vout )
VDD VTp K R (2Vout VTn )
VIH
1 KR
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CMOS INVERTER – VTC w.r.t process variation parameter
2.5
2
Good PMOS
Bad NMOS
1.5
Vout (V) KR<1
Nominal
1 Good NMOS KR=1
Bad PMOS
KR>1 Kn
0.5 Where, KR
Kp
0
0 0.5 1 1.5 2 2.5
Vin (V)
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CMOS INVERTER – voltage gain
• During transition region, both NMOS and PMOS are in saturation region.
• In order to calculate the gain in this region , channel length modulation can not
be ignored.
Differentiating and solving for
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CMOS INVERTER – voltage gain
Ignoring second order term and setting Vin=VM
• Gain is almost purely determined by the technology parameter
• It is slightly depends on the transistor sizing ratio.
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CMOS INVERTER – voltage gain
2.5 0.2
2
0.15
1.5
(V)
(V)
0.1
out
out
V
V
0.05
0.5
0
0 0 0.05 0.1 0.15 0.2
0 0.5 1 1.5 2 2.5 V (V)
V (V) in
in
Adapted from Digital Integrated Circuits (2nd Edition)- Jan M. Rabaey
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Recapitulation
• CMOS inverter consists of pull-up PMOS block and pull-down NMOS
block.
• A ideal inverter exhibits high input impedance and low output
impedance, typically in kilo ohm.
• The logic swing is equal to supply voltage and does not depends upon
device relative device size.
• Gain of inverter is function of technology parameter.
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Thank You
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