CSE_2323

Combinational
Logic

Course Teacher: Mujibur Rahman Maruf 1

 Digital Logic Design
Course code: CSE-2323
Credit Hour: 3
Md. Mujibur Rahman Maruf
ASSISTANT LECTURER,
Dept. of CSE, IIUC
Mujiburmaruf.cuet17@gmail.com

International Islamic University

) Chittagong(IIUC)
Course Teacher: Mujibur Rahman Maruf 2
 Combinational Circuits
• Logic circuits for digital systems may be combinational or sequential.
• A combinational circuit consists of input variables, logic gates, and output variables.

Course Teacher: Mujibur Rahman Maruf 3

Examples of Combinational Circuits
▪ Addition:
▪ Half Adder (HA).
▪ Full Adder (FA).
▪ BCD(Decimal) Adder.
▪ Subtraction:
▪ Half Subtractor.
▪ Full Subtractor.
▪ Multiplication:
▪ Binary Multipliers.
▪ Comparator:
▪ Magnitude Comparator.
Course Teacher: Mujibur Rahman Maruf 4
Examples of Combinational Circuits

▪ Multiplexers
▪ Demultiplexers
▪ Encoders
▪ Decoders
▪ Converters
• Binary to Gray Code
• Gray to Binary Code
• Binary to BCD Code
Course Teacher: Mujibur Rahman Maruf 5
Designing Combinational Circuits

In general we have to do following steps:

1. Problem description
2. Input/output of the circuit
3. Define truth table
4. Simplification for each output
5. Draw the circuit

Course Teacher: Mujibur Rahman Maruf 6

 Half Adder
▪ Adding two single-bit binary values, A, B produces a sum S
bit and a carry out C-out bit.
▪ This operation is called half addition and the circuit to
realize it is called a half adder. X Half S
B Adder C

Half Adder Truth Table

Input Outputs
Sum Y Y’ Y YZ C YZ’ Y Y’ Y YZ YZ’
X 0 1 11 10 X 0 1 11 10
X’ 0 0 1 0 1X’ 0 0 0 0 1
X 1 1 0 1 0X 1 0 1 1 0
S = XY’+X’ Y
S = X Y C = XY
Course Teacher: Mujibur Rahman Maruf 7
 Half Adder
S = XY’+X’ Y C = XY
S = XY

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 Full Adder

Full Adder Truth Table

Inputs Outputs X Y

Full
C- Z
Adder

Think of Z as a carry in

Course Teacher: Mujibur Rahman Maruf 9

 Full Adder
 A combinational circuit that adds 3 input bits to generate a
Sum bit and a Carry bit
Sum YZ Y’Z’ Y’Z YZ YZ’
X 00 01 11 10
X’ 0 0 1 0 1 S = X’Y’Z + X’YZ’ + XY’Z’ +XYZ
X 1 1 0 1 0

Carry
YZ Y’Z’ Y’Z YZ YZ’
X 00 01 11 10
X’ 0 0 0 1 0
C = XY + XZ + YZ
X 1 0 1 1 1
Course Teacher: Mujibur Rahman Maruf 10
 Full Adder
Implementation of full adder in sum of products
S= xy z+x yz +xy z +xyz

C= xy +xz +yz

Course Teacher: Mujibur Rahman Maruf 11

 Implementation of full adder with two half-adders and
an OR gate
Manipulating the Equations:
Carry YZ Y’Z’ Y’Z YZ YZ’
Sum X 00 01 11 10
YZ Y’Z’ Y’Z YZ YZ’
X 00 01 11 10 X’ 0 0 0 1 0
X’ 0 0 1 0 1 X 1 0 1 1 1
X 1 1 0 1 0 C = XY’Z + XYZ + X’YZ+XYZ’
=Z(XY’+X’Y) +XY(Z+Z’)
S= xy z+x yz +xy z +xyz =XY+Z(X  Y )
= xy z  +x yz + xyz+ xy z
= z (xy  +x y) +z ( xy+ xy )
= z (xy)+ z(xy) 
= z  (x  y)

Think of
Z as a
carry in Course Teacher: Mujibur Rahman Maruf 12
 Binary Parallel Adder
 To add n-bit numbers:
• Use n Full-Adders in parallel
• The carries propagates as in addition by hand

• For example to add A= 1011 and B= 0011

subscript i: 3 2 1 0
Input carry: 0 1 1 Ci
Augend: 1 0 1 1 Ai
Addend: 0 0 1 1 Bi
Sum: 1 1 1 0 Si
Output carry: 0 0 1 1
Course Teacher: Mujibur Rahman Maruf 13
 Binary Parallel Adder
 To add n-bit numbers:
• Use n Full-Adders in parallel
• The carries propagates as in addition by hand

Src: Mano’s Book

This adder is called ripple carry adder
Course Teacher: Mujibur Rahman Maruf 14
Subtraction (2’s Complement)
 How to build a subtractor using 2’s complement?

1 0 1 0 Borrow
A 13 1 1 0 1
B - 6 1’s 1 0 01
7 10 1 1 0
+1
00 1 1 1

Course Teacher: Mujibur Rahman Maruf 15

Subtraction (2’s Complement)
 How to build a subtractor using 2’s complement?

S = A + ( -B)
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 Half Subtractor
▪ Subtracting a single-bit binary value B from anther A(I.e.A-B ) produces a
difference bit D and a borrow out bit B-out.
▪ This operation is called half subtraction and the circuit to realize it is called a half subtractor.
Half Adder Truth Table D = A’B + AB’
Inputs Outputs B-out = A’B

A B D B-out
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Course Teacher: Mujibur Rahman Maruf 17

 Half Subtractor
D = A’B + AB’
B-out = A’B
A Difference
D
B

B-out

Course Teacher: Mujibur Rahman Maruf 18

 Full Subtractor
▪ Subtracting two single-bit binary values, B, B-in from a single-bit value A produces a
difference bit D and a borrow out B-out bit. This is called full subtraction.
Full Subtractor Truth Table
Inputs Outputs

A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
D(A,B, B-in) =  (1,2,4,7) 1 0 0 1 0
B-out(A, B, Bin) =  (1,2,3,7) 1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Course Teacher: Mujibur Rahman Maruf 19

 Full Subtractor

Full Subtractor Truth Table

Inputs Outputs

A B B-in D B-out
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1 D = A’B’(B-in) + AB’(B-in)’+ A’B(B-in)’+
0 1 1 0 1 AB(B-in)
1 0 0 1 0 D= A  B  (B-in)
1 0 1 0 0
1 1 0 0 0 D(A,B, B-in) =  (1,2,4,7)
1 1 1 1 1 Bout(A, B, B-in) =  (1,2,3,7)

Course Teacher: Mujibur Rahman Maruf 20

 Full Subtractor

Bout = A’B + A’(B-in) + B(B-in)

Course Teacher: Mujibur Rahman Maruf 21

 Full Subtractor Using half
substractor
B-out = A’B’Bin + A’BB'in + ABBin +A’BBin
B-out = Bin(A’B’ + AB) + A’B(B’in +Bin)
D= A  B  (B-in) B-Out= Bin(AB’ + A’B)’ + A’B

Course Teacher: Mujibur Rahman Maruf 22

 CODE Converter
A code converter is a combinational circuit that makes the two systems compatible even
though each uses a different binary code.

Binary Binary
Code A Code Converter Code B

Course Teacher: Mujibur Rahman Maruf 23

 Binary to Gray CODE Converter
truth table explaining the operation of a 4-bit binary-to-gray code converter.

Binary Code Gray Code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
 Binary to Gray CODE Converter
The K-Map simplification for the gray code bit G0 The K-Map simplification for the gray code bit G1

the logic circuit diagram of a 4-bit binary code to gray code converter −

The K-Map simplification for the gray code bit G2 The K-Map simplification for the gray code bit G3
 Problem-1
A committee of three individuals decide issues for an organization. Each individual votes either
yes or no for each proposal that arises. A proposal is passed if it receives at least two yes
votes. Design a circuit that determines whether a proposal passes

Course Teacher: Mujibur Rahman Maruf 26

 Problem-2
Design a combinational circuit with three inputs and one output. The output is 1 when the binary value of the inputs is
less than 3. The output is 0 otherwise

Course Teacher: Mujibur Rahman Maruf 27

 Problem-3
Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and C.
When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When
the binary input is 4, 5, 6, or 7, the binary output is less than the input.

B= xy z+x yz + xy z + xyz

= xy z  +x yz + xyz+ xy z
= z (xy  +x y) +z ( xy+ xy )
= z (xy)+ z(xy) 
= z  (x  y)

Course Teacher: Mujibur Rahman Maruf 28

Problem-4

Course Teacher: Mujibur Rahman Maruf 29

 Problem-5
A microwave oven requires that the main power supply be on, the door be latched, and
timer set other than zero before the oven will function. Draw a logic diagram for the
operation of the oven.
Input Output

A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

Course Teacher: Mujibur Rahman Maruf 30

 Problem-6
1.Construct a truth table for a circuit that will accept 3 bit numbers and generate
the 2's complement of these numbers.

Course Teacher: Mujibur Rahman Maruf 31

 Problem-7
Design a combinational circuit that converts 3-bit binary number to Gray code

Course Teacher: Mujibur Rahman Maruf 32

 NAND and NOR Implementations

• NAND & NOR gates are universal gates.

• Digital circuit are frequently constructed with NAND or NOR gates rather than AND and OR
gates.
• NAND and NOR gates are easier to fabricate with electronic components and are the basic gates
used in all IC digital logic families.(covering AND,OR,NOT)

Course Teacher: Mujibur Rahman Maruf 33

NAND Gate Equivalent to AOI Gates
NAND Gate as an Inverter Gate NAND Gate as an And Gate
X• X = X (Before Bubble)
XY
X Z=X X
Z = X Y=XY
Y

NAND Gate as an Or Gate NAND Gate Inverter

X Y
Z= XY= X+Y= X+Y
Y

Inverters NAND Gate

Course Teacher: Mujibur Rahman Maruf 3 34

4
NAND Gate Equivalent to AOI Gates

AND OR INVERTER

3
Course Teacher: Mujibur Rahman Maruf 5 35
 Process for NAND Implementation
1. If starting from a logic expression, implement the design with AOI
logic.
2. In the AOI implementation, identify and replace every AND,OR, and
INVERTER gate with its NAND equivalent.
3. Redraw the circuit.
4. Identify and eliminate any double inversions (i.e., back-to-back
inverters).
5. Redraw the final circuit.

Course Teacher: Mujibur Rahman Maruf 36

 NAND Implementation
Example:
Step:2 Identify and replace every AND,OR, and
Design a NAND Logic Circuit that is equivalent to INVERTER gate with its NAND equivalent.
the AOI circuit shown below.

= B C' + A C

Course Teacher: Mujibur Rahman Maruf 37

 NAND Implementation
Step 3: Redraw the circuit. Step 4:Identify and eliminate any double inversions.

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 NAND Implementation
Step 5: Redraw the circuit.

Course Teacher: Mujibur Rahman Maruf 39

 NAND Implementation
• Simplify Boolean function and implement with nand gate Sum YZ Y’Z’ YZ’
Y’Z YZ
X 00 01 11 10

• Y(X,Y,Z) = ∑ m(1,3,7)
X’ 0 0 1 1 0
X 1 0 0 1 0

Y =X’Z+YZ

Self Task

• Implement the this Boolean express using only

NAND gates
Course Teacher: Mujibur Rahman Maruf 40
NOR Implementation

Class work

Course Teacher: Mujibur Rahman Maruf 41

 Consensus Theorem
Redundancy theorem is used as a Boolean algebra trick in Digital Electronics. It is also
known as the Consensus Theorem:
Conditions for applying Redundancy theorem are:
1.Three variables must present in the expression.Here A, B and C are used as variables.
2.Each variables is repeated twice. After applying this theorem we can only take
3.One variable must present in complemented form. those terms which contains the complemented
variable
Consensus Theorem
In SOP form
AB+B’C+AC = AB+B’C

In POS form
(A+B)(B’+C)(A+C) = (A+B)(B’+C)
Course Teacher: Mujibur Rahman Maruf 42
 Fault in Logic Circuit
Stack at 0 and stack at 1 gate
Stack at 1
The output of a given point will stay 1 no matter what is the circuit connection
1

Stack at 0
The output of a given point will stay 0 no matter what is the circuit connection

Course Teacher: Mujibur Rahman Maruf 43

 Minimum Two input Nand gate for multi input
Nand gate

Two input NAND to implement n input AND : 2(n-1)

Ex: how many two input NAND gate required to imolement 3 input AND gate ? Ans:4

Two input NAND to implement n input NAND: (2n-3)

how many two input NAND gate required to imolement 3 Input NAND
gate ? Ans:3

Course Teacher: Mujibur Rahman Maruf 44

 Self-duality
A function is said to be Self dual if and only if its dual is equivalent to the given function, i.e., if a given function is f(X, Y,
Z) = (XY + YZ + ZX) then its dual is, fd(X, Y, Z) = (X + Y).(Y + Z).(Z + X) (fd = dual of the given function) = (XY +
YZ + ZX), it is equivalent to the given function. So function is self dual.
number of Self-dual functions possible for a given function.
Let, a function has n variables then,
Number of pairs possible = 2n/2 = 2(n-1)

the number of Self-dual functions is possible with n variables = 22^(n-1)

What is the total number of self-duals of a function which has 3 variables X, Y, and Z?

= 22^(3-1)
= 22^2
= 24
= 16
Course Teacher: Mujibur Rahman Maruf 45