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Design of High Stability and Low Power 7T SRAM Cell in 32-NM CNTFET
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Article in Journal of Circuits, Systems and Computers · May 2022

DOI: 10.1142/S0218126622502334

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Journal of Circuits, Systems, and Computers
Vol. 31, No. 13 (2022) 2250233 (23 pages)
.c World Scienti¯c Publishing Company
#
DOI: 10.1142/S0218126622502334

Design of High Stability and Low Power 7T

SRAM Cell in 32-NM CNTFET Technology¤

M. Elangovan†,§ and M. Muthukrishnan‡

Department of Electronics and Communication Engineering,
Government College of Engineering,
Srirangam, Trichy, Tamilnadu, India
†
m.elangovan@gcebargur.ac.in
‡
muthurhetor@gmail.com

Received 25 May 2021

Accepted 2 April 2022
Published 20 May 2022

A novel 7T carbon nanotube ¯eld e®ect transistor (CNTFET)-based static random-access

memory (SRAM) cell is proposed in this paper. Power and noise margin performances of the
proposed SRAM cell is observed for write, hold and read operations. The power consumption
and noise margin of the proposed SRAM cell is compared with the conventional 6T and 8T
CNTFET-based SRAM cells. From the simulation, it is noted that the proposed 7T SRAM cell
consumes lesser power and o®ers high static noise margin (SNM) compared to that of con-
ventional 6T and 8T SRAM cells. The introduction of diode-based transistor structure improves
the power and noise performance of the proposed SRAM cell. The e®ect of variation of para-
meters such as gate oxide thickness, dielectric constant, pitch, temperature, number of carbon
nanotubes (CNT) and supply voltage on power and noise performance of proposed 7T SRAM
cell is studied. Simulations were carried out with HSPICE simulation tool using Stanford
University 32-nm CNTFET model.

Keywords: SRAM; CNTFET; SNM; low power and process variation.

1. Introduction
Moore's law-based miniaturization of metal oxide semiconductor ¯eld e®ect tran-
sistors (MOSFETs) and leakage power are con°icting.1 MOSFET has reached its
down scaling limit. The reduction of MOSFET size to nanoscale range causes many
problems such as high leakage power, easy in°uence of PVT variations in device
performance and second-order e®ects. So very large-scale integration (VLSI) in-
dustries have been looking for a device alternative to MOSFET. In 1971, graphitized
carbon was created for the ¯rst time from carbon ¯ber. Sumio Iijima introduced

*This paper was recommended by Regional Editor Giuseppe Ferri.

§ Corresponding author.

2250233-1
M. Elangovan & M. Muthukrishnan

carbon nanotubes (CNTs) and 4-nm multi walled CNT (MWCNT), and later
published a research article on 1-nm single walled CNT (SWCNT).2 A transistor
made out of CNT is termed as CNT ¯eld e®ect transistor (CNTFET) has notable
electrical characteristics, like high current density, near ballistic transport, high
transconductance and high thermal stability. As a result, CNTFET is recognized as
the most appropriate alternative for MOSFET.3,4 Bulk channel of an MOSFET is
replaced with a single or multiple CNTs and thus, the structure of CNTFET is as
shown in Fig. 2.5 The chiral vectors, also known as chirality (m, nÞ, is an important
factor in CNT, as they determine the current °ow in CNT. Based on the chiral
vectors used, the CNT is categorized into three types, i.e., armchair structure
(m ¼ nÞ, chiral structure (m 6¼ nÞ, and zig-zag structure (n ¼ 0) (Fig. 3). CNT
behaves as a conductor when m ¼ n or jm  nj ¼ 3i (where i is an integer), otherwise
as a semiconductor.6,7 SWCNT and MWCNT are two types of CNTs classi¯ed based
on the number of layers of graphene layers as shown in Fig. 1.8 The quantum ca-
pacitance of a CNTFET system is reduced when the channel length is reduced below
10 nm, while the quantum capacitance of an MOSFET increases. Thus, CNTFET
has a much lesser propagation delay than MOSFET which improves the performance
of CNTFET-based circuits.9 The reduction of channel length below 10 nm makes
MOSFETs unstable, while CNTFETs preserve interface stability well below 10 nm.
As a result, CNTFET follows Moore's law even in the submicron range VLSI de-
sign.10 CNT conducts 70 times more electricity than copper conductors.11 The width
of channel in a CNTFET (WCNT Þ is given by
WCNT ¼ ðN  1ÞS þ DCNT : ð1Þ

Fig. 1. Structure of graphene sheet, SWCNT and MWCNT.

2250233-2
 High Stability and Low Power 7T SRAM Cell IN 32-nm CNTFET

Fig. 2. Structure of CNTFET.

Here, N is the number of CNTs used, S is the distance between parallel CNTs also
called pitch value of CNTFET, and DCNT is the diameter of CNTs. The diameter of
CNT is given by
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
a n 2 þ nm þ m 2
DCNT ¼ ; ð2Þ

where a is carbon–carbon bonding length (a ¼ 2:49 Å). The threshold voltage (Vth Þ
of CNTFET is inversely proportional to the DCNT and positively proportional to the
bandgap energy (Eg Þ. The Vth is described as
pffiffiffi
Eg 3 aV
Vth ¼ ¼ ; ð3Þ
2e 3 eDCNT

Fig. 3. Honeycomb structure of a graphene sheet, armchair, zigzag and chiral types.

2250233-3
M. Elangovan & M. Muthukrishnan

where e is the charge of an electron (e ¼ 1:602E-19) and V is the carbon – bond
energy (V ¼ 3:033 eV).12,13 As static random-access memory (SRAM) consumes
70% of a system's total power and occupies 80% of the total die size, it is essential to
reduce the power consumption and space occupied by it. When SRAM cell made of
MOSFET is downscaled, it reduces the noise margin as well as it increases leakage
power.14 CNTFET-based SRAM design overcomes all of the limitations of MOSFET
based nanotechnology design. Conventional 6T SRAM (Fig. 4) cell has only one path
for both writing and reading operations which decreases the stability of memory cell.
As a result, reading noise margin of the 6T SRAM cell is extremely low compared to
that of all other SRAM cells. In contrast, traditional 8T SRAM cell (Fig. 5) has
di®erent paths for writing and reading operations8 through two dedicated transistors
for the reading process. These transistors are known as read-access transistors. Ad-
dition of a separate path for reading operations increases the read stability of 8T
SRAM cell. But the leakage current of read access transistors is higher which results
in higher leakage power consumption of traditional 8T SRAM cell.15 When compared
to the standard 10T SRAM cells, the 10T-P1-3-bit cells save 19.8% in energy per
access and 19.5% in area and also improves read performance by about
100 mV. These cells are more suitable for battery assisted circuits and low power
sensors.16 The stacked P-MOSFET in pull-up network of the single ended PPN
based 10T SRAM cell improves read static noise margin (RSNM) and decreases the
leakage power of the SRAM cell. The single-ended PPN-based 10T SRAM cell is
better suited to low-power wireless sensor network nodes.17 TG9T SRAM cell uses a
read decoupling technique to preserve high RSNM. It employs the feedback cutting
method to boost write SNM (WSNM) of the bit cell. By lowering the bit-line
switching factor, the dynamic power consumption of the cell is reduced and the
leakage power consumption is reduced by transistor stacking technique.18 SPG11T

Fig. 4. 6T CNTFET SRAM cell.8

2250233-4
 High Stability and Low Power 7T SRAM Cell IN 32-nm CNTFET

Fig. 5. Conventional 8T CNTFET SRAM cell.13

SRAM cell has a write and read assist technology built-in which includes the addition
of a write and read assist scheme which improves the write and read stability of the
cell. The leakage power consumption of SPG11T SRAM cell is lowered by 53.3% and
44.5% than that of conventional 6T and 8T SRAM cells respectively.19 The power
gating or sleep transistor approach used in FinFET-based ST13T SRAM cell
improves the power e±ciency of the SRAM cell by about 93%, while the transmission
gate-based access method reduces the delay by about 12.84%.20 In the optimized 9T
SRAM cell, the stacked P-MOSFETs in the pull-up network decreases the power
consumption by 58% compared to that of conventional 6T SRAM cell. The SRAM
cell's SINM and SVNM are 93% and 45% better than those of a sub-threshold 10T
SRAM cell, respectively.21 P-CNTFET and N-CNTFET in pull-up and pull-down
networks are used in the 8T CNTFET SRAM cell, which is highly stable and con-
sumes low power. Staked transistors boost the write and hold stability of the cell over
traditional 6T and 8T CNTFET SRAM cells.13 WSNM, HSNM, and RSNM of the
proposed 10T CNTFET SRAM cell are higher than those of traditional 10T SRAM
cell due to stacked transistor structure and a dedicated read path.22 E±ciency
metrics of various 9T SRAM cell are compared and tabulated in Ref. 23. The supply
feedback of 9T SRAM cell has the lowest write delay and uses least amount of power

2250233-5
M. Elangovan & M. Muthukrishnan

while writing.23 A sleep transistor in the pull-down network and stacked transistors
in the pull-up network make up the 9T SRAM cell proposed in Ref. 24. As a result,
when compared to 8T SRAM cell, the leakage, read, and write power consumption of
the 9T SRAM cell is reduced.24 As compared to a 6T SRAM cell, the static and
leakage power consumption of a 9T SRAM bit-cell with sleep transistor is signi¯-
cantly low. SNM of the 9T SRAM bit-cell is 18.9% higher than that of 6T SRAM
cell.25 As compared to traditional two-bit-line SRAM cells, the single-bit-line 9T
SRAM cell consumes less power. Both bit-lines of conventional 2-bit-lines SRAM
cells are precharged for write and read operations. For write and read operations in a
single bit-line 9T SRAM cell, precharging the single bit-line is su±cient. As a result,
the proposed cell requires less power than traditional structures and also has higher
RSNM than conventional cells.26 A boosted bit-line read scheme is used in a 32-kb 9T
SRAM cell which increases RSNM of the SRAM cell more than that of conventional
8T SRAM cell. The proposed cell automatically detects process, voltage and tem-
perature (PVT) variations and ensures that the usage of bit-lines is data indepen-
dent.27 NCNTFET Darlington 8T SRAM cell is basically a conventional 6T SRAM
cell with a Darlington pair included in the pull-down network. Read power con-
sumption of this cell is found to reduce by 87.18% and 88.57% than that of con-
ventional 6T CNTFET and 8T CNTFET SRAM cells, respectively. Also WSNM of
the same is found to increase by 70.83% than both conventional 6T and 8T CNTFET
SRAM cells.28 The HSNM and WSNM of the novel 8T CNTFET SRAM cell are
higher than that of conventional 8T CNTFET SRAM cell. The noise margin and
power performance of the proposed 8T CNTFET SRAM cell are better.29
P CNTFET Darlington 8T SRAM cell is found to be better that 6T and 8T
CNTFET SRAM cells in terms of power and noise performances.30 The write power
consumption of low power and high stable 12T SRAM cell is minimized by using
power cutting technique which in turn increases the WSNM of the cell.31 A bit-
interleaved 10T SRAM cell proposed for low power applications has achieved sig-
ni¯cant improvement in the noise margin and also leakage power dissipation of the
cell is minimized by using high threshold voltage devices in its read path. The WSNM
of the cell is improved by employing cut-o® switching technique.32 Ternary inverter
based SRAM cell has lesser power consumption as it conducts less current while
keeping the input as VDD/2.33 The power delay product (PDP) of 4T-STI 32-nm
CNTFET SRAM cell is 86–97% lower compared to the conventional 32-nm 6T-STI
SRAM cell.34 As we have witnessed there has been a quest for miniaturizing SRAM
cell and also minimizing power consumption while improving the noise margin. In
this paper, a novel CNTFET-based 7T SRAM cell is proposed. The power con-
sumption of the proposed cell is measured for hold, write and read modes. The
stability of the proposed SRAM cell against DC noise is calculated using an
SNM. The hold SNM (HSNM), WSNM and RSNM of the proposed cell are deter-
mined. The power and SNM performance of the proposed cell are found to be better
than that of conventional SRAM cells.

2250233-6
 High Stability and Low Power 7T SRAM Cell IN 32-nm CNTFET

2. Proposed 7T CNTFET SRAM Cell

The proposed 7T CNTFET SRAM cell consists of seven CNTFETs: N1–N5, P1 and
P2. The storage cell in the proposed 7T CNTFET SRAM cell is made up of two
inverters and a single diode-connected transistor (N3) in the pull-down network. The
access transistors (N4 and N5) are used to access the information in the storage cell.
The WL line is controlling the access transistors. The bit values are stored in storage
nodes Q and QB. The SRAM cell's bit-lines (BL and BLB) and word lines (WL) are
used to perform various controlling operations. For write, hold and read operations,
the signals BL, BLB and WL are activated and deactivated in di®erent ways. The
introduction of the N3 transistor decreases power consumption and improves noise
stability, compared to the conventional memory cells. The proposed 7T CNTFET
SRAM cell is shown in Fig. 6.

2.1. Write operation

The proposed 7T CNTFET SRAM cell write (Bit \1") operation is shown in Fig. 7.
BL ¼ 1, BLB ¼ 0, and WL ¼ 1 are the conditions for the write \1" operation. As a

Fig. 6. Schematic of proposed 7T CNTFET SRAM cell.

2250233-7
M. Elangovan & M. Muthukrishnan

Fig. 7. Write operation of proposed 7T CNTFET SRAM cell.

result, the access transistors are turned \ON". Bit values BL and BLB are forced to
store in Q and QB, respectively. This enables P1 and N2 and disables N1 and P2
CNTFETs. As a result, the storage nodes Q and QB are pulled up to VDD and pull-
down to ground potential, respectively.

2.2. Read operation

The read action of the proposed 7T SRAM cell begins with the precharging of BL
and BLB into VDD, while the access transistors are kept low. As a result, the bit-
lines are separated from the storage nodes. The WL line is enabled after precharging,
and BL and BLB are connected to Q and QB, respectively. BLB is discharged
through N2, N3, and N5 transistors, as shown in Fig. 8. As a result, the potential at
BLB is lower than VDD. As N1 transistor is switched \OFF" and there is no way for
BL to discharge, hence potential at BL remains same as that of VDD. External sense
ampli¯ers are connected to bit-lines for reading purposes. The sense ampli¯er
determines the potential di®erence between the bit-lines and gives the resultant bit
value that is stored in the cell.

2250233-8
 High Stability and Low Power 7T SRAM Cell IN 32-nm CNTFET

Fig. 8. Read operation of proposed 7T CNTFET SRAM cell.

2.3. Hold operation

The WL line is disabled during the hold operation. Access transistors are then set to
\OFF". This in turn separates the bit-lines from the storage cell. The storage nodes
preserve the values of the stored bit as it is. The state of hold is often called stand-by
state. The 7T CNTFET SRAM cell structure during the hold operation is shown
in Fig. 9.

3. Simulation Result and Discussion

The proposed 7T CNTFET SRAM cell has a better power and noise e±ciency due to
the addition of a diode connected transistor (N3). In the conventional 6T and 8T
SRAM cells, the source terminals of pull-down transistors (N1 and N2) are connected
to the ground potential. Hence the threshold voltage or above threshold voltage noise
potential is enough to turn \ON" the N1 and N2 transistors. In the proposed 7T
CNTFET SRAM cell, the N3 is connected between the ground and sources of N1 and
N2. The presence of N3 shifts the potential of sources of the N1 and N2 above ground
potential. Hence as compared to conventional SRAM cells, more DC noise is needed
to °ip the data present in the storage nodes of the proposed 7T CNTFET SRAM cell.

2250233-9
M. Elangovan & M. Muthukrishnan

Fig. 9. Hold operation of proposed 7T CNTFET SRAM cell.

The WSNM and HSNM of the proposed cell are thus improved. The proposed 7T
CNTFET SRAM cell contains stacked CNTFETs between the storage nodes and
ground. The N3 is stacked with either N1 or N2 based on stored bit value (either \0"
or \1"). The stacked transistors increase the \ON" condition resistance (RON Þ be-
tween the storage nodes and the ground. This RON value is two times greater than
the conventional 6T and 8T CNTFET SRAM cell between the storage nodes and the
ground. The increase in RON , decreases the current consumption of the proposed cell.
This in turn reduces the power consumption of the proposed 7T CNTFET SRAM
cell relative to traditional 6T and 8T CNTFET SRAM cells. Hence, for the proposed
cell, the noise margin is obviously higher than that of conventional one. For write,
hold and read operations, the power consumption and SNM of proposed cell are
calculated.
The power consumption of the proposed 7T CNTFET SRAM cell is calculated.
The proposed SRAM cell is found to consume 2.14E10 W power during hold
mode. The power dissipated during read mode of operation in the proposed cell is
found to be 87.09% and 91.96% less than that of conventional 6T and 8T SRAM
cells, respectively. Figure 11 compares the power of conventional 6T, 8T, and the
proposed 7T SRAM cells.

2250233-10
 High Stability and Low Power 7T SRAM Cell IN 32-nm CNTFET

Fig. 10. Schematic of the proposed 7T CNTFET SRAM cell (N3 as voltage source).

We have investigated the SNM of the proposed 7T SRAM cell and compared it
with that of conventional 6T and 8T SRAM cells. The results indicate that the
proposed 7T SRAM has better SNM than that of the conventional cells. Figure 12
shows the comparison of SNM of conventional and the proposed cells. HSNM and
WSNM of the proposed cell are found to be 15% and 78.83% higher than conven-
tional 6T and 8T SRAM cells, respectively. The SNM of the proposed cell during

Fig. 11. Power comparison of various SRAM cells.

2250233-11
M. Elangovan & M. Muthukrishnan

Fig. 12. SNM comparison of various SRAM cells.

read operation is found to be 14.28% higher than that of traditional 6T SRAM cell.
During read mode, storage nodes are directly connected with bit-lines. This reduces
the read stability of the proposed 7T SRAM cell compared to the conventional 8T
cell. The WSNM, HSNM, and RSNM butter°y diagrams of di®erent SRAM cells are
shown in Figs. 13–15.
The e®ect of gate oxide thickness on the performance of the proposed cell is
studied by varying the gate oxide thickness of CNTFET from 2 nm to 6 nm. The
power dissipation of the proposed 7T CNTFET SRAM cell as a function oxide
thickness is given in Fig. 16. Tunneling of electrons from channel to gate or gate

Fig. 13. WSNM butter°y diagram of various SRAM cells.

2250233-12
 High Stability and Low Power 7T SRAM Cell IN 32-nm CNTFET

Fig. 14. HSNM butter°y diagram of various SRAM cells.

leakage is reduced as the oxide thickness increases which results in the reduction of
leakage power consumption.22 The leakage power consumption of the proposed 7T
CNTFET SRAM is inversely proportional to thickness of gate oxide in CNTFET
(Fig. 16).
The current °owing in the channel is directly proportional to the dielectric con-
stant of the gate oxide material used.22 Here, we have increased the dielectric con-
stant of the gate oxide material from 3.9 to 55 and observed the power consumption

Fig. 15. RSNM butter°y diagram of various SRAM cells.

2250233-13
M. Elangovan & M. Muthukrishnan

Fig. 16. Power comparisons of the proposed 7T CNTFET SRAM for di®erent oxide thickness.

of the proposed SRAM cell (Fig. 17). Power consumed by the device is found to be
very negligible when we increase the dielectric constant of gate oxide from 3.9 to 55.
The variation in dielectric constant is found to have very negligible e®ect on the
power performance of the device.
The e®ect of temperature on the power performance of a memory cell has to be
studied as it is known that temperature plays a crucial role in determining the
e±ciency of a cell. Here, we have varied the temperature of the proposed cell from
20  C to 227  C. The thermally generated electrons in CNTFET channel increases
with the increase in temperature. Thus, the channel current increases. As a result, a

Fig. 17. Power comparisons of proposed 7T CNTFET SRAM for di®erent dielectric constant.

2250233-14
 High Stability and Low Power 7T SRAM Cell IN 32-nm CNTFET

Fig. 18. Power comparisons of proposed 7T CNTFET SRAM for di®erent temperature.

voltage signi¯cantly lower than that of threshold voltage at lower temperature is

su±cient to turn the device \ON".22 As a consequence, threshold voltage decreases
with increase in temperature. This in turn increases the power consumption of the
memory cell with temperature (Fig. 18).
The channel of CNTFET is formed by either as SWCNT or MWCNTs arranged
parallel to each other.8 The rate of current °ow of CNTFET channel is determined

Fig. 19. Power comparisons of proposed 7T CNTFET SRAM for di®erent CNTs.

2250233-15
M. Elangovan & M. Muthukrishnan

Fig. 20. Power comparisons of proposed 7T CNTFET SRAM for di®erent pitch values.

by the number of CNTs in the channel. With the increase in number of CNTs, the
power consumed by the proposed CNTFET-based 7T SRAM cell increases as shown
in Fig. 19.
The axial distance between two adjacent CNTs placed in CNTFET channel is
known as pitch value.22 The e®ect of pitch on the power performance of the proposed

Fig. 21. Power comparisons of proposed 7T CNTFET SRAM for di®erent supply voltages.

2250233-16
 High Stability and Low Power 7T SRAM Cell IN 32-nm CNTFET

Fig. 22. Basic SRAM cell with noise sources for SNM calculation.

cell is studied by varying the pitch value from 10 nm to 90 nm. It is observed that the
power performance of SRAM cell remains una®ected by changing the pitch value as
shown in Fig. 20.
Supply voltage plays a vital role in determining the amount of power consumed by
the device. With the increase in supply voltage, the current in the channel increases
which in turn will increase the power consumed.22 As expected, the power consumed
for read, write and hold operations by the proposed 7T CNTFET SRAM cell
increases with the increase in supply voltage as shown in Fig. 21. As the minimum
voltage for the proposed cell to meet out the functionality is 0.4 V, hence, the sim-
ulation is done by varying the supply voltage from 0.4 V to 1.5 V.

Fig. 23. SNM of the proposed 7T CNTFET SRAM for various oxide thicknesses.

2250233-17
M. Elangovan & M. Muthukrishnan

Fig. 24. SNM of the proposed 7T CNTFET SRAM for various dielectric constants.

3.1. SNM modeling

SNM is the minimum amount of direct current (DC) noise required to °ip the state of
an SRAM cell (i.e., from \0" to \1" or \1" to \0"). SNM is a metric used to calculate

Fig. 25. SNM of the proposed 7T CNTFET SRAM for various temperatures.

2250233-18
 High Stability and Low Power 7T SRAM Cell IN 32-nm CNTFET

Fig. 26. SNM of the proposed 7T CNTFET SRAM for various number of CNTs.

the stability of SRAM cell. Voltage transfer characteristics (VTC) of both inverters
in the SRAM cell can be obtained by varying the DC noise from 0 V to VDD at the
storage nodes. A \butter°y diagram" is obtained by overlapping the two VTC plots.

Fig. 27. SNM of the proposed 7T CNTFET SRAM for various pitch values.

2250233-19
M. Elangovan & M. Muthukrishnan

Fig. 28. SNM of the proposed 7T CNTFET SRAM for various supply voltages.

SNM is calculated by determining the largest diagonal of the square that can be
inserted into the butter°y diagram.8 The model of basic SRAM cell with noise
sources for SNM calculation is shown in Fig. 22.
Increase in gate oxide thickness results in increase in threshold voltage of
CNTFET. The value of increase in threshold voltage for the proposed cell is obtained
by varying the gate oxide thickness from 2 nm to 6 nm. With the increase in gate
oxide thickness, threshold voltage of CNTFET is found to increase which improves
SNM of SRAM cell. The dielectric constant is inversely proportional to threshold
voltage. The gate capacitance between the channel and the gate terminal increases as
the dielectric constant increases. As a result, threshold voltage of the device decreases
with increase in dielectric constant which decreases the stability of the proposed
SRAM cell. Increase in temperature of the proposed cell decreases the threshold
voltage of the CNTFET which in turn decreases the SNM of proposed 7T CNTFET
SRAM cell. The supply voltage also plays a crucial part in the stability of a memory
cell by a®ecting its SNM. With the increase in supply voltage, SNM of the proposed
7T CNTFET SRAM increases. Figures 23–28 illustrate the SNM of the proposed 7T
CNTFET SRAM for various parameters, such as oxide thickness, dielectric constant,
temperature, number of CNTs, pitch and supply voltage, respectively.

4. Conclusion
HSNM and WSNM of the proposed 7T CNTFET SRAM cell are found to be 15%
and 78.83% higher than the conventional 6T and 8T SRAM cells, respectively.

2250233-20
 High Stability and Low Power 7T SRAM Cell IN 32-nm CNTFET

The SNM of the proposed cell during read operation is found to be 14.28% higher
than that of traditional 6T SRAM cell. The power dissipated during read mode of
operation in the proposed cell is found to be 87.09% and 91.96% less than that of
conventional 6T and 8T SRAM cells, respectively. The hold mode power con-
sumption of the proposed cell is of the order of pico-watts, whereas in the conven-
tional SRAM cell it is of the order of micro-watts. SNM of SRAM cell is directly
proportional to the supply voltage and gate oxide thickness, and inversely propor-
tional to dielectric constant of the gate oxide and temperature. It is noted that power
consumption of the proposed 7T CNTFET SRAM cell is directly proportional to the
supply voltage, temperature and dielectric constant of gate oxide. The power con-
sumption of the SRAM cell is inversely proportional to the gate oxide thickness of
CNTFET. The proposed cell o®ers excellent power and noise performance than that
of the conventional CNTFET SRAM cells upon varying the process parameters. The
proposed cell is therefore very suitable for low power applications.

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