ALLDATASHEET.

COM

Part # BQ4285EP X

Preview PDF Download HTML Chat AI

BQ4285EP Datasheet (PDF) - Texas

Instruments
2 of 32
clock, calendar, and storage registers
ä Automatic backup and write- - Periodic rates from 122μ s to during power failure. A backup bat-
protect control to external SRAM 500ms tery then maintains data and oper-
ä Functionally compatible with the - Time-of-day alarm once per
ates the clock and calendar.
DS1285 second to once per day The bq4285E/L is a fully compatible
ä Less than 0.5 μ A load under bat- - End-of-clock update cycle real-time clock for IBM AT-
compatible computers and other ap-
tery operation ä 24-pin plastic DIP or SOIC plications. The only external compo-
nents are a 32.768kHz crystal and a
backup battery.
The bq4285E/L integrates a
ä 14 bytes for clock/calendar and battery-backup controller to make a
control

Pin Connections Pin Names

AD0–AD7 Multiplexed address/data
input/output
MOT Bus type select input
VOUT 1 24 VCC
X1 2 23 SQW CS Chip select input
X2 3 22 CEOUT AS Address strobe input
AD0 4 21 CEIN DS Data strobe input
AD1 5 20 BC R/W Read/write input
AD2 6 19 INT INT Interrupt request output
AD3 7 18 RST RST Reset input
AD4 8 17 DS SQW Square wave output
AD5 9 16 VSS
BC 3V backup cell input
AD6 10 15 R/W
X1–X2 Crystal inputs
AD7 11 14 AS
VSS 12 13 CS NC No connect
CEIN RAM chip enable input
24-Pin DIP or SOIC 28-Pin PLCC: No Longer Available CEOUT RAM chip enable output
PN428501.eps
VOUT Supply output
VCC +5V supply

SLUS006A - MAY 1994 - REVISED MAY 2004

bq4285E/L

Block Diagram

standard CMOS SRAM nonvolatile during power-fail The setting should not be changed during
conditions. During power-fail, the bq4285E/L auto- system operation. MOT is internally pulled
matically write-protects the external SRAM and pro- low by a 20KΩ resistor. For the DIP and
vides a VCC output sourced from the clock backup SOIC packages, this pin is internally con-
battery. nected to VSS, enabling the bus timing for
the Intel architecture.
Pin Descriptions CS Chip select input

AD0 –AD7 Multiplexed address/data input/ CS should be driven low and held stable
output during the data-transfer phase of a bus cy-
cle accessing the bq4285E/L.
The bq4285E/L bus cycle consists of two
phases: the address phase and the data-
transfer phase. The address phase precedes
the data-transfer phase. During the ad-
dress phase, an address placed on AD0 –AD7
is latched into the bq4285E/L on the falling Table 1. Bus Setup
edge of the AS signal. During the data-
transfer phase of the bus cycle, the AD0–AD7 Bus MOT DS R/W AS
pins serve as a bidirectional data bus. Type Level Equivalent Equivalent Equivalent

MOT
Connect to VSS for normal operation

RD, WR,
Intel VSS MEMR, or MEMW, or ALE
I/OR I/OW

Click to view in HTML datasheet.

Similar Part No. - BQ4285EP

Manufacturer Part # Datasheet Description

[Old version datasheet] Enhanced

BQ4285EP
Texas 1Mb / 31P RTC With NVRAM Control
Instruments
More results

Similar Description - BQ4285EP

Manufacturer Part # Datasheet Description
[Old version datasheet] Enhanced
BQ4285E 1Mb / 31P
RTC With NVRAM Control
Texas Instruments [Old version datasheet] Real-Time
BQ4285 1Mb / 27P
Clock RTC With NVRAM Control
[Old version datasheet] Real-Time
BQ4285 1Mb / 29P
Clock (RTC) With NVRAM Control
483Kb / Serial real-time clock (RTC) with
M41T56
27P 56 bytes NVRAM
STMicroelectronics 231Kb / Serial real-time clock (RTC) with
M41T11
30P 56 bytes of NVRAM
142Kb / [Old version datasheet] Real-Time
BQ4287
8P Clock Module With NVRAM Control
Texas Instruments BQ4287MT- 376Kb / [Old version datasheet] Real-Time
SB2 10P Clock Module With NVRAM Control
Y2K Watchdog RTC with
547Kb /
DS1500 Nonvolatile Control
20P
Maxim Integrated Rev 11/11
Produc... Y2K Watchdog RTC with
365Kb /
DS1500 Nonvolatile Control
19P
REV: 111705

Y2K Watchdog RTC with

DS1500 351Kb /
Dallas Nonvolatile Control
Semiconductor 19P

More results

Link URL
https://www.alldatasheet.com/datasheet-pdf/view/26821/TI/BQ4285EP.h

English

Privacy Policy
ALLDATASHEET.COM