MC14070B, MC14077B
CMOS SSI
Quad Exclusive “OR” and “NOR” Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P−channel and
N−channel enhancement mode devices in a single monolithic http://onsemi.com
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC−14
D SUFFIX
• All Outputs Buffered CASE 751A
• Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature PIN ASSIGNMENT
Range
• Double Diode Protection on All Inputs IN 1A 1 14 VDD
• MC14070B − Replacement for CD4030B and CD4070B Types IN 2A 2 13 IN 2D
• MC14077B − Replacement for CD4077B Type OUTA 3 12 IN 1D
• NLV Prefix for Automotive and Other Applications Requiring OUTB 4 11 OUTD
Unique Site and Control Change Requirements; AEC−Q100
IN 1B 5 10 OUTC
Qualified and PPAP Capable
IN 2B 6 9 IN 2C
• These Devices are Pb−Free and are RoHS Compliant
VSS 7 8 IN 1C
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol Parameter Value Unit MARKING DIAGRAM
VDD DC Supply Voltage Range −0.5 to +18.0 V
Vin, Vout Input or Output Voltage Range −0.5 to VDD + 0.5 V 14
(DC or Transient)
140xxBG
Iin, Iout Input or Output Current ±10 mA AWLYWW
(DC or Transient) per Pin
1
PD Power Dissipation, per Package 500 mW
(Note 1)
xx = Specific Device Code
TA Ambient Temperature Range −55 to +125 °C A = Assembly Location
WL, L = Wafer Lot
Tstg Storage Temperature Range −65 to +150 °C
YY, Y = Year
TL Lead Temperature 260 °C WW, W = Work Week
(8−Second Soldering) G = Pb−Free Package
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be ORDERING INFORMATION
assumed, damage may occur and reliability may be affected. See detailed ordering and shipping information in the package
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C dimensions section on page 4 of this data sheet.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:
August, 2014 − Rev. 10 MC14070B/D
MC14070B, MC14077B
MC14070B MC14077B
QUAD Exclusive OR QUAD Exclusive NOR
Gate Gate
1 1
3 3
2 2
5 5
4 4
6 6
8 8
10 10
9 9
12 12
11 11
13 13
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)
20 ns 20 ns
VDD VDD
90%
50%
Vin 10%
IDD VSS
1/f
Vin * 50% DUTY CYCLE
CL
*Inverted output on MC14077B only.
Figure 1. Power Dissipation Test Circuit and Waveform
VDD 20 ns 20 ns
VDD
PULSE 90%
* INPUT 50%
GENERATOR 10%
# VSS
CL tPHL tPLH
VSS 90% VOH
OUTPUT 50%
10% VOL
tTHL tTLH
*Inverted output on MC14077B only.
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
Figure 2. Switching Time Test Circuit and Waveforms
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2
MC14070B, MC14077B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
−55_C 25_C 125_C
VDD Typ
Characteristic Symbol Vdc Min Max Min (Note 2) Max Min Max Unit
Output Voltage “0” Level VOL 5.0 − 0.05 − 0 0.05 − 0.05 Vdc
Vin = VDD or 0 10 − 0.05 − 0 0.05 − 0.05
15 − 0.05 − 0 0.05 − 0.05
“1” Level VOH 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc
Vin = 0 or VDD 10 9.95 − 9.95 10 − 9.95 −
15 14.95 − 14.95 15 − 14.95 −
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 − 1.5 − 2.25 1.5 − 1.5
(VO = 9.0 or 1.0 Vdc) 10 − 3.0 − 4.50 3.0 − 3.0
(VO = 13.5 or 1.5 Vdc) 15 − 4.0 − 6.75 4.0 − 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 − 3.5 2.75 − 3.5 −
(VO = 1.0 or 9.0 Vdc) 10 7.0 − 7.0 5.50 − 7.0 −
(VO = 1.5 or 13.5 Vdc) 15 11 − 11 8.25 − 11 −
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 –3.0 − –2.4 –4.2 − –1.7 −
(VOH = 4.6 Vdc) 5.0 –0.64 − –0.51 –0.88 − –0.36 −
(VOH = 9.5 Vdc) 10 –1.6 − –1.3 –2.25 − –0.9 −
(VOH = 13.5 Vdc) 15 –4.2 − –3.4 –8.8 − –2.4 −
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc
(VOL = 0.5 Vdc) 10 1.6 − 1.3 2.25 − 0.9 −
(VOL = 1.5 Vdc) 15 4.2 − 3.4 8.8 − 2.4 −
Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc
Input Capacitance Cin − − − − 5.0 7.5 − − pF
(Vin = 0)
Quiescent Current IDD 5.0 − 0.25 − 0.0005 0.25 − 7.5 mAdc
(Per Package) 10 − 0.5 − 0.0010 0.5 − 15
15 − 1.0 − 0.0015 1.0 − 30
Total Supply Current (Notes 3 & 4) IT 5.0 IT = (0.3 mA/kHz) f + IDD mAdc
(Dynamic plus Quiescent, 10 IT = (0.6 mA/kHz) f + IDD
Per Package) 15 IT = (0.9 mA/kHz) f + IDD
(CL = 50 pF on all outputs, all buffers
switching)
Output Rise and Fall Times (Note 3) tTLH, ns
(CL = 50 pF) tTHL
tTLH, tTHL = (1.35 ns/pF) CL + 33 ns 5.0 − − − 100 200 − −
tTLH, tTHL = (0.60 ns/pF) CL + 20 ns 10 − − − 50 100 − −
tTLH, tTHL = (0.40 ns/pF) CL + 20 ns 15 − − − 40 80 − −
Propagation Delay Times (Note 3) tPLH, ns
(CL = 50 pF) tPHL
tPLH, tPHL = (0.90 ns/pF) CL + 130 ns 5.0 − − − 175 350 − −
tPLH, tPHL = (0.36 ns/pF) CL + 57 ns 10 − − − 75 150 − −
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns 15 − − − 55 110 − −
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
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3
MC14070B, MC14077B
ORDERING INFORMATION
Device Package Shipping†
MC14070BDG SOIC−14 55 Units / Rail
(Pb−Free)
MC14070BDR2G SOIC−14 2500 / Tape & Reel
(Pb−Free)
NLV14070BDR2G* SOIC−14 2500 / Tape & Reel
(Pb−Free)
MC14077BDG SOIC−14 55 Units / Rail
(Pb−Free)
MC14077BDR2G SOIC−14 2500 / Tape & Reel
(Pb−Free)
NLV14077BDR2G* SOIC−14 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC14070B, MC14077B
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
D
ISSUE K
A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
b DIM MIN MAX MIN MAX
0.25 M B M 13X
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h D 8.55 8.75 0.337 0.344
A X 45 _ E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
M L 0.40 1.25 0.016 0.049
e A1
SEATING M 0_ 7_ 0_ 7_
C PLANE
SOLDERING FOOTPRINT*
6.50 14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
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