MC14541B

Programmable Timer
The MC14541B programmable timer consists of a 16stage binary
counter, an integrated oscillator for use with an external capacitor and
two resistors, an automatic poweron reset circuit, and output control
logic.
Timing is initialized by turning on power, whereupon the poweron
reset is enabled and initializes the counter, within the specified VDD
range. With the power already on, an external reset pulse can be
applied. Upon release of the initial reset command, the oscillator will
oscillate with a frequency determined by the external RC network. The
16stage counter divides the oscillator frequency (fosc) with the nth
stage frequency being fosc/2n.
Available Outputs 28, 210, 213 or 216
Increments on Positive Edge Clock Transitions
Builtin Low Power RC Oscillator ( 2% accuracy over temperature
range and 20% supply and 3% over processing at < 10 kHz)
Oscillator May Be Bypassed if External Clock Is Available (Apply
external clock to Pin 3)
External Master Reset Totally Independent of Automatic Reset
Operation
Operates as 2n Frequency Divider or Single Transition Timer
Q/Q Select Provides Output Logic Level Flexibility
Reset (auto or master) Disables Oscillator During Resetting to
Provide No Active Power Dissipation
Clock Conditioning Circuit Permits Operation with Very Slow Clock
Rise and Fall Times
Automatic Reset Initializes All Counters On Power Up
Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset
Supply Voltage Range = Disabled (Pin 5 = VDD)
Supply Voltage Range = 8.5 Vdc to 18 Vdc with Auto Reset
Supply Voltage Range = Enabled (Pin 5 = VSS)
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
VDD
Vin, Vout

Parameter

Value

Unit

0.5 to +18.0

Input or Output Voltage Range

(DC or Transient)

0.5 to VDD + 0.5

DC Supply Voltage Range

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PDIP14
P SUFFIX
CASE 646

14

MARKING
DIAGRAMS
MC14541BCP
AWLYYWW

1
14

SOIC14
D SUFFIX
CASE 751A

14541B
AWLYWW
1
14

TSSOP14
DT SUFFIX
CASE 948G

14
541B
ALYW
14

SOEIAJ14
F SUFFIX
CASE 965

1
MC14541B
AWLYWW

1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

ORDERING INFORMATION
Device

Package

Shipping

MC14541BCP

PDIP14

2000/Box

MC14541BD

SOIC14

55/Rail

MC14541BDR2

SOIC14

2500/Tape & Reel

MC14541BDT

TSSOP14

96/Rail

MC14541BDTR2

TSSOP14 2500/Tape & Reel

MC14541BF

SOEIAJ14

See Note 1.

SOEIAJ14

See Note 1.

Iin

Input Current (DC or Transient)

10 (per Pin)

mA

MC14541BFEL

Iout

Output Current (DC or Transient)

45 (per Pin)

mA

PD

Power Dissipation,
per Package (Note 3.)

500

mW

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local
ON Semiconductor representative.

TA

Ambient Temperature Range

55 to +125

Tstg

Storage Temperature Range

65 to +150

TL

Lead Temperature
(8Second Soldering)

260

2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C
Semiconductor Components Industries, LLC, 2000

March, 2000 Rev. 6

This device contains protection circuitry to guard

against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this highimpedance circuit. For proper
operation, Vin and Vout should be constrained to the
range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

Publication Order Number:

MC14541B/D

MC14541B
PIN ASSIGNMENT
Rtc

14

VDD

Ctc

13

RS

12

NC

11

NC

AR

10

MODE

MR

Q/Q SEL

VSS

NC = NO CONNECTION

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

55_C

VDD

25_C

125_C

Symbol

Vdc

Min

Max

Min

Typ (4.)

Max

Min

Max

Unit

0 Level

VOL

5.0
10
15

0.05
0.05
0.05

0
0
0

0.05
0.05
0.05

0.05
0.05
0.05

Vdc

1 Level

VOH

5.0
10
15

4.95
9.95
14.95

4.95
9.95
14.95

5.0
10
15

4.95
9.95
14.95

Vdc

Input Voltage
0 Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

VIL
5.0
10
15

1.5
3.0
4.0

2.25
4.50
6.75

1.5
3.0
4.0

1.5
3.0
4.0

1 Level

VIH
5.0
10
15

3.5
7.0
11

3.5
7.0
11

2.75
5.50
8.25

3.5
7.0
11

5.0
10
15

7.96
4.19
16.3

6.42
3.38
13.2

12.83
6.75
26.33

4.49
2.37
9.24

IOL

5.0
10
15

1.93
4.96
19.3

1.56
4.0
15.6

3.12
8.0
31.2

1.09
2.8
10.9

mAdc

Input Current

Iin

15

0.1

0.00001

0.1

1.0

Adc

Input Capacitance
(Vin = 0)

Cin

5.0

7.5

pF

Quiescent Current
(Pin 5 is High)
Auto Reset Disabled

IDD

5.0
10
15

5.0
10
20

0.005
0.010
0.015

5.0
10
20

150
300
600

Adc

Auto Reset Quiescent Current

(Pin 5 is low)

IDDR

10
15

250
500

30
82

250
500

1500
2000

Adc

Supply Current (5.) (6.)

(Dynamic plus Quiescent)

ID

5.0
10
15

Characteristic
Output Voltage
Vin = VDD or 0

Vin = 0 or VDD

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

Vdc

Vdc

IOH
Source

(VOL = 0.4 Vdc)

(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Sink

mAdc

ID = (0.4 A/kHz) f + IDD

ID = (0.8 A/kHz) f + IDD
ID = (1.2 A/kHz) f + IDD

Adc

4. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. When using the on chip oscillator the total supply current (in Adc) becomes: IT = ID + 2 Ctc VDD f x 103 where ID is in A, Ctc is in pF,
VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during poweron with automatic reset enabled is typically 50 A @ VDD = 10 Vdc.

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2

MC14541B

SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)

Characteristic

VDD

Min

Typ (8.)

Max

5.0
10
15

100
50
40

200
100
80

5.0
10
15

3.5
1.25
0.9

10.5
3.8
2.9

5.0
10
15

6.0
3.5
2.5

18
10
7.5

tWH(cl)

5.0
10
15

900
300
225

300
100
85

ns

fcl

5.0
10
15

1.5
4.0
6.0

0.75
2.0
3.0

MHz

tWH(R)

5.0
10
15

900
300
225

300
100
85

ns

trem

5.0
10
15

420
200
200

210
100
100

ns

Symbol

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH,
tTHL

Propagation Delay, Clock to Q (28 Output)

tPLH, tPHL = (1.7 ns/pF) CL + 3415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 1217 ns
tPLH, tPHL = (0.5 ns/pF) CL + 875 ns

tPLH
tPHL

Propagation Delay, Clock to Q (216 Output)

tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns
tPHL, tPLH = (0.66 ns/pF) CL + 3467 ns
tPHL, tPLH = (0.5 ns/pF) CL + 2475 ns

tPHL
tPLH

Clock Pulse Width

Clock Pulse Frequency (50% Duty Cycle)

MR Pulse Width

Master Reset Removal Time

Unit
ns

7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

VDD

PULSE
GENERATOR

VDD

PULSE
GENERATOR

RS
AR
Q/Q SELECT
MODE

RS
AR
Q/Q SELECT
MODE
A
B
MR

A
B
MR

CL

VSS

CL

VSS

20 ns

(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)

20 ns

RS

20 ns
90% 50%
10%
50%
DUTY CYCLE

20 ns
90% 50%
10%

tPLH

tPHL
50%

Q
tTLH

Figure 1. Power Dissipation Test Circuit

and Waveform

50%

90%
10%

50%
tTHL

Figure 2. Switching Time Test Circuit

and Waveforms

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3

MC14541B
EXPANDED BLOCK DIAGRAM
A 12
B 13
1 OF 4
MUX
8 Q
Rtc 1
Ctc 2

OSC

RS 3

RESET

AUTO RESET
5

210 213 216

C 8STAGE
COUNTER
RESET

8STAGE 8
2
C
COUNTER
RESET

POWERON
RESET

6
MASTER RESET

10
MODE

9
Q/Q
SELECT

VDD = PIN 14
VSS = PIN 7

FREQUENCY SELECTION TABLE

Number of
Counter Stages
n

13

8192

10

1024

256

16

65536

TRUTH TABLE
State

Count
2n

Pin
Auto Reset,

0
5

Auto Reset
Operating

Auto Reset Disabled

Master Reset, 6

Timer Operational

Master Reset On

Q / Q,

Output Initially Low

After Reset

Output Initially High

After Reset

Mode,

10

Single Cycle Mode

Recycle Mode

TO CLOCK
CIRCUIT
INTERNAL
RESET
2

1
Ctc

RS

RTC

Figure 3. Oscillator Circuit Using RC Configuration

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4

MC14541B
TYPICAL RC OSCILLATOR CHARACTERISTICS
8.0

100
VDD = 15 V
f, OSCILLATOR FREQUENCY (kHz)

FREQUENCY DEVIATION (%)

0
10 V
4.0
8.0

5.0 V

12
RTC = 56 k,
C = 1000 pF

16
55

25

VDD = 10 V

50

4.0

RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C

RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C

0
25
50
75
TA, AMBIENT TEMPERATURE (C)

100

f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS 2RTC)

20
10
5.0
2.0
1.0

f AS A FUNCTION
OF C
(RTC = 56 k)
(RS = 120 k)

0.5
0.2
0.1
1.0 k

125

0.0001

Figure 4. RC Oscillator Stability

10 k
100 k
RTC, RESISTANCE (OHMS)

1.0 m

0.001
0.01
C, CAPACITANCE (F)

0.1

Figure 5. RC Oscillator Frequency as a

Function of Rtc and Ctc

OPERATING CHARACTERISTICS
With Auto Reset pin set to a 0 the counter circuit is
initialized by turning on power. Or with power already on,
the counter circuit is reset when the Master Reset pin is set
to a 1. Both types of reset will result in synchronously
resetting all counter stages independent of counter state.
Auto Reset pin when set to a 1 provides a low power
operation.
The RC oscillator as shown in Figure 3 will oscillate with
a frequency determined by the external RC network i.e.,
f=

1
2.3 RtcCtc

and RS 2 Rtc

if (1 kHz

when B is 0, normal counting is interrupted and the 9th

counter stage receives its clock directly from the oscillator
(i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a 0 the Q output is a 0,
correspondingly when Q/Q select pin is set to a 1 the Q
output is a 1.
When the mode control pin is set to a 1, the selected
count is continually transmitted to the output. But, with
mode pin 0 and after a reset condition the RS flipflop (see
Expanded Block Diagram) resets, counting commences,
and after 2n1 counts the RS flipflop sets which causes the
output to change state. Hence, after another 2n1 counts the
output will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to reset
the single cycle operation.

v f v 100 kHz)

where RS 10 k

The time select inputs (A and B) provide a twobit address

to output any one of four counter stages (28, 210, 213 and
216). The 2n counts as shown in the Frequency Selection
Table represents the Q output of the Nth stage of the counter.
When A is 1, 216 is selected for both states of B. However,

DIGITAL TIMER APPLICATION

When Master Reset (MR) receives a positive pulse, the
internal counters and latch are reset. The Q output goes high
and remains high until the selected (via A and B) number of
clock pulses are counted, the Q output then goes low and
remains low until another input pulse is received.
This one shot is fully retriggerable and as accurate as the
input frequency. An external clock can be used (pin 3 is the
clock input, pins 1 and 2 are outputs) if additional accuracy
is needed.
Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up,
during which time Q output will be high.

Rtc
Ctc

NC

RS
AR
MR

INPUT

14

VDD

13

12

11

10

N.C.
MODE
Q/Q

VDD
OUTPUT

tMR

t + tMR

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5

MC14541B
PACKAGE DIMENSIONS

P SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE M
14

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

A
F

DIM
A
B
C
D
F
G
H
J
K
L
M
N

T
SEATING
PLANE

K
H

D 14 PL

0.13 (0.005)

INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310

10_
0.015
0.039

MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87

10_
0.38
1.01

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

A
14

B
1

P 7 PL
0.25 (0.010)

R X 45 _

T
SEATING
PLANE

0.25 (0.010)

D 14 PL
M

T B

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6

DIM
A
B
C
D
F
G
J
K
M
P
R

MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019

MC14541B
PACKAGE DIMENSIONS

DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G01
ISSUE O
14X K REF

0.10 (0.004)
0.15 (0.006) T U

T U

N
2X

14

L/2

0.25 (0.010)

M
B
U

L
PIN 1
IDENT.

F
7

0.15 (0.006) T U

DETAIL E
K

A
V

K1

J J1

SECTION NN
W

C
0.10 (0.004)
T SEATING
PLANE

DETAIL E

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7

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C

1.20

0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.50
0.60
0.020
0.024
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0_
8_
0_
8_

MC14541B
PACKAGE DIMENSIONS

F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96501
ISSUE O

14

LE

Q1
E HE

M_
L

DETAIL P

Z
D
VIEW P

A1

b
0.13 (0.005)

0.10 (0.004)

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z

MILLIMETERS
MIN
MAX

2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90

1.42

INCHES
MIN
MAX

0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035

0.056

ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be
validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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