TN2640

N-Channel Enhancement-Mode Vertical DMOS FET

Features General Description
• 2V Maximum Low Threshold The TN2640 low-threshold Enhancement-mode
• High Input Impedance (normally-off) transistor uses a vertical DMOS structure
• Low Input Capacitance and a well-proven silicon-gate manufacturing process.
This combination produces a device with the power
• Fast Switching Speeds
handling capabilities of bipolar transistors and the high
• Low On-Resistance input impedance and positive temperature coefficient
• Free from Secondary Breakdown inherent in MOS devices. Characteristic of all MOS
• Low Input and Output Leakage structures, this device is free from thermal runaway and
thermally induced secondary breakdown.
Applications Microchip’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications
• Logic-Level Interfaces (Ideal for TTL and CMOS)
where very low threshold voltage, high breakdown
• Solid-State Relays voltage, high input impedance, low input capacitance,
• Battery-Operated Systems and fast switching speeds are desired.
• Photovoltaic Drives
• Analog Switches
• General Purpose Line Drivers
• Telecommunication Switches

Package Types

3-lead TO-252 (D-PAK) 3-lead TO-92 8-lead SOIC

(Top view) (Top view) (Top view)
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN

DRAIN GATE
SOURCE SOURCE
GATE SOURCE N/C
N/C

GATE

See Table 3-1, Table 3-2, and Table 3-3 for pin information.

 2021 Microchip Technology Inc. DS20005795A-page 1

TN2640
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-Source Voltage ...................................................................................................................................... BVDSS
Drain-to-Gate Voltage ......................................................................................................................................... BVDGS
Gate-to-Source Voltage.......................................................................................................................................... ±20V
Operating Ambient Temperature, TA ................................................................................................... –55°C to +150°C
Storage Temperature, TS ..................................................................................................................... –55°C to +150°C

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. All DC parameters are 100% tested at 25°C unless
otherwise stated. (Pulse test: 300 µs pulse, 2% duty cycle)
Parameter Sym. Min. Typ. Max. Unit Conditions
Drain-to-Source Breakdown Voltage BVDSS 400 — — V VGS = 0V, ID = 1 mA
Gate Threshold Voltage VGS(th) 0.8 — 2 V VGS = VDS, ID = 2 mA
Change in VGS(th) with Temperature ΔVGS(th) — –2.5 –4 mV/°C VGS = VDS, ID = 2 mA (Note 1)
Gate Body Leakage Current IGSS — — 100 nA VGS = ±20V, VDS = 0V
VGS = 0V,
— — 10 µA
VDS = Maximum rating
Zero-Gate Voltage Drain Current IDSS
VDS = 0.8 Maximum rating,
— — 1 mA
VGS = 0V, TA = 125°C (Note 1)
1.5 3.5 — A VGS = 5V, VDS = 25V
On-State Drain Current ID(ON)
2 4 — A VGS = 10V, VDS = 25V
Static Drain-to-Source On-State — 3.2 5 Ω VGS = 4.5V, ID = 500 mA
RDS(ON)
Resistance — 3 5 Ω VGS = 10V, ID = 500 mA
VGS = 10V, ID = 500 mA
Change in RDS(ON) with Temperature ΔRDS(ON) — — 0.75 %/°C
(Note 1)
Note 1: Specification is obtained by characterization and is not 100% tested.

DS20005795A-page 2  2021 Microchip Technology Inc.

 TN2640
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. All AC parameters are not 100% sample tested.
Parameter Sym. Min. Typ. Max. Unit Conditions
Forward Transconductance GFS 200 330 — mmho VDS = 25V, ID = 100 mA
Input Capacitance CISS — 210 225 pF
Common-Source Output Capacitance COSS — 30 50 pF VGS = 0V, VDS = 25V, f = 1 MHz
Reverse Transfer Capacitance CRSS — 8 15 pF
Turn-On Delay Time td(ON) — 4 15 ns
Rise Time tr — 15 20 ns
VDD = 25V, ID = 2A, RGEN = 25Ω
Turn-Off Delay Time td(OFF) — 20 25 ns
Fall Time tf — 22 27 ns
DIODE PARAMETER
Diode Forward Voltage Drop VSD — — 0.9 V VGS = 0V, ISD = 200 mA (Note 1)
Reverse Recovery Time trr — 300 — ns VGS = 0V, ISD = 1A
Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated.
(Pulse test: 300 µs pulse, 2% duty cycle)

TEMPERATURE SPECIFICATIONS
Parameter Sym. Min. Typ. Max. Unit Conditions
TEMPERATURE RANGE
Operating Ambient Temperature TA –55 — +150 °C
Storage Temperature TS –55 — +150 °C
PACKAGE THERMAL RESISTANCE
3-lead TO-252 (D-PAK) JA — 81 — °C/W
8-lead SOIC JA — 101 — °C/W
3-lead TO-92 JA — 132 — °C/W

THERMAL CHARACTERISTICS
ID (Note 1) ID Power Dissipation at
IDR (Note 1) IDRM
Package (Continuous) (Pulsed) TA = 25°C
(mA) (A)
(mA) (A) (W)
3-lead TO-252 (D-PAK) 500 3 2.5 (Note 2) 500 3
8-lead SOIC 260 2 1.3 (Note 2) 260 2
3-lead TO-92 220 2 0.74 220 2
Note 1: ID (continuous) is limited by maximum TJ.
2: Mounted on an FR4 board, 25 mm x 25 mm x 1.57 mm

 2021 Microchip Technology Inc. DS20005795A-page 3

TN2640
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
1.15 10

VGS = 5.0V
1.10 8
BVDSS (normalized)

RDS(ON) (ohms)
1.05 6 VGS = 10V

1.00 4

0.95 2

0.90 0
-50 0 50 100 150 0 1.0 2.0 3.0 4.0 5.0
O
Tj ( C) ID (amperes)

FIGURE 2-1: BVDSS Variation with FIGURE 2-4: On-resistance vs. Drain
Temperature. Current.
3.0 1.4 2.2
25OC

V(th) @ 2.0mA
2.4 1.2 1.8

RDS(ON) (normalized)
O
125 C
VGS(th) (normalized)

TA = -55OC
ID (amperes)

1.8
1.0 1.4

1.2
0.8 -1.0
VDS = -25V

0.6 RDS(ON) @ 10V, 0.5A

0.6 0.6

0
0 2 4 6 8 10 0.4 0.2
-50 0 50 100 150
VGS (volts) Tj (OC)

FIGURE 2-2: Transfer Characteristics. FIGURE 2-5: VGS(th) and RDS(ON)

Variation with Temperature.
400 10

f = 1MHz
8
300
C (picofarads)

653pF
VGS (volts)

200 VDS = 10V

CISS 4

VDS = 40V
100
2
COSS

CRSS 253pF
0
0 10 20 30 40 0
0 1 2 3 4 5
VDS (volts) QG (nanocoulombs)

FIGURE 2-3: Capacitance vs. FIGURE 2-6: Gate Drive Dynamic

Drain-to-source Voltage. Characteristics.

DS20005795A-page 4  2021 Microchip Technology Inc.

 TN2640
5.0 2.5
VGS = 10V
8V
6V
4.0 2.0 4V
VGS = 10V
8V
ID (amperes)

ID (amperes)
3.0 6V 1.5
4V 3V

2.0 1.0

3V
1.0 0.5

2V
2V
0 0
0 10 20 30 40 50 0 2 4 6 8 10
VDS (volts) VDS (volts)

FIGURE 2-7: Output Characteristics. FIGURE 2-10: Saturation Characteristics.

2.0 3.0
VDS = 25V
DPAK
1.6 2.4
GFS (siemens)

PD (watts)
1.2 1.8

SO-8
0.8 TA = -55OC 1.2

TO-92
25OC 0.6
0.4

125OC 0
0
0 1.0 2.0 3.0 4.0 5.0 0 25 50 75 100 125 150

ID (amperes) TC (OC)

FIGURE 2-8: Transconductance vs. Drain FIGURE 2-11: Power Dissipation vs.
Current. Temperature.
10 1.0
Thermal Resistance (normalized)

TO-92 (pulsed)
0.8
1.0
DPAK (DC)
ID (amperes)

SO-8 (pulsed) 0.6

0.1
TO-92 (DC)

0.4
SO-8 (DC)

0.01
0.2 TO-92
PD = 1W
O
TC = 25 C TC = 25OC

0.001 0
0 1.0 100 1000 0.001 0.01 0.1 1.0 10
VDS (volts) tP (seconds)

FIGURE 2-9: Maximum Rated Safe FIGURE 2-12: Thermal Response

Operating Area. Characteristics.

 2021 Microchip Technology Inc. DS20005795A-page 5

TN2640
3.0 PIN DESCRIPTION
Table 3-1, Table 3-2, and Table 3-3 show the
description of pins in TN2640. Refer to Package Types
for the location of the pins.

TABLE 3-1: 3-LEAD TO-252 (DPAK) PIN FUNCTION TABLE

Pin Number Pin Name Description

1 Gate Gate
3 Source Source
4 Drain Drain

TABLE 3-2: 8-LEAD SOIC PIN FUNCTION TABLE

Pin Number Pin Name Description

1 N/C No connect
2 N/C No connect
3 Source Source
4 Gate Gate
5 Drain Drain
6 Drain Drain
7 Drain Drain
8 Drain Drain

TABLE 3-3: 3-LEAD TO-92 PIN FUNCTION TABLE

Pin Number Pin Name Description

1 Source Source
2 Gate Gate
3 Drain Drain

DS20005795A-page 6  2021 Microchip Technology Inc.

 TN2640
4.0 FUNCTIONAL DESCRIPTION
Figure 4-1 illustrates the switching waveforms and test
circuit for TN2640.

10V 90% VDD

INPUT Pulse RL
10% Generator
0V OUTPUT
t(ON) t(OFF)
RGEN
td(ON) tr td(OFF) tf

VDD INPUT D.U.T.

10% 10%
OUTPUT
0V 90% 90%

FIGURE 4-1: Switching Waveforms and Test Circuit.

TABLE 4-1: PRODUCT SUMMARY

RDS(ON) ID(ON) VGS(th)
BVDSS/BVDGS
(Maximum) (Minimum) (Maximum)
(V)
(Ω) (A) (V)
400 5 2 2

 2021 Microchip Technology Inc. DS20005795A-page 7

TN2640
5.0 PACKAGING INFORMATION

5.1 Package Marking Information

TO-252 (D-PAK) Example

XX TN
XXXXX e3 2640 e3
YYWWNNN 2112541

8-lead SOIC Example

XXXXXXXX TN2640LG
e3 YYWW e3 2125
NNN 579

3-lead TO-92 Example

XXXXXX TN2640
XX e3 N3 e3
YWWNNN 12987

Legend: XX...X Product Code or Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.

DS20005795A-page 8  2021 Microchip Technology Inc.

 TN2640

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

 2021 Microchip Technology Inc. DS20005795A-page 9

TN2640

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

DS20005795A-page 10  2021 Microchip Technology Inc.

 TN2640

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

 2021 Microchip Technology Inc. DS20005795A-page 11

TN2640
NOTES:

DS20005795A-page 12  2021 Microchip Technology Inc.

 TN2640
APPENDIX A: REVISION HISTORY

Revision A (February 2021)

• Converted Supertex Doc# DSFP-TN2640 to
Microchip DS20005795A
• Changed the package marking format
• Updated the quantity of the 8-lead SOIC from
2500/Reel to 3300/Reel to align it with the actual
BQM
• Removed the TO-92 N3 P002, P003, P005, P013,
and P015 media types to align package specifica-
tions with the actual BQM
• Made minor text changes throughout the docu-
ment

 2021 Microchip Technology Inc. DS20005795A-page 13

TN2640
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Examples:
PART NO. XX - X - X

Device Package Environmental Media Type a) TN2640K4-G: N-Channel Enhancement-

Options Mode Vertical DMOS FET,
3-lead TO-252 (D-PAK),
2000/Reel

Device: TN2640 = N-Channel Enhancement-Mode Vertical

DMOS FET b) TN2640LG-G: N-Channel Enhancement-
Mode Vertical DMOS FET,
8-lead SOIC, 3300/Reel
Packages: K4 = 3-lead TO-252 (D-PAK)
LG = 8-lead SOIC
c) TN2640N3-G: N-Channel Enhancement-
N3 = 3-lead TO-92 Mode Vertical DMOS FET,
3-lead TO-92, 1000/Bag
Environmental: G = Lead (Pb)-free/RoHS-compliant Package

Media Types: (blank) = 2000/Reel for a K4 Package

= 3300/Reel for an LG Package
= 1000/Bag for an N3 Package

DS20005795A-page 14  2021 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
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please visit www.microchip.com/quality.

 2021 Microchip Technology Inc. DS20005795A-page 15

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DS20005795A-page 16  2021 Microchip Technology Inc.

02/28/20