Literature Review: Level Shifter

Niveditha Shashank G K Sumanth R R

Dept. Of ECE, Dept. Of ECE Dept. Of ECE
BNM Institute of technology BNM Institute of technology BNM Institute of technology
Bangalore, India Bangalore, India Bangalore, India
nivedithacs3@gmail.com shashankgkubasad@gmail.com sumanthrr8521@gmail.com

Priyadarshini K Desai Jyoti R Munavalli

Dept. of ECE Dept. of ECE
BNM Institute of technology Bangalore, BNM Institute of technology Bangalore,
India India
priyadarshinikdesai@bnmit.in jyotirmunavalli@bnmit.in

Abstract will perform differently under various

From low-power and energy-efficient operating voltage domains and specific
designs in modern VLSI circuits, research application requirements, such as sub-
in voltage level shifters has increased threshold versus above-threshold.
because they are vital for interfacing Additionally, quite a few designs showed a
between multi-voltage domains in significant improvement in dynamic power
integrated systems. In this paper, we due to the reduction of threshold voltage
analyzed and compared existing low-power drop and minimization of short circuit
level shifter designs that are up to seven, currents. The simulation results graphically
which considered methodologies to show that although a few methods provided
optimize power, delay, and overall energy. reductions in power, others essentially
The survey shows that techniques such as concentrated on faster transition rates, so
multi-threshold CMOS, contention trade-offs were made in much design. A
mitigation, auxiliary circuits, and current complete survey on level shifters is brought
mirror configuration are the most important to the limelight through this survey on how
in realizing power-delay trade-offs. For efficient these types of devices can be in
example, some designs have reached an contemporary multi-voltage VLSI designs.
ultra-low value of power dissipation: as low Keywords – Low-power design, Voltage
as 0.29 pW, whereas others provide level shifter, Multi-threshold CMOS,
considerable improvements in delay Contention mitigation, Subthreshold
compared to conventional shifters of up to operation, Energy efficiency, VLSI circuits,
55%. Dynamic power consumption, Current
Our analysis indicates that these designs mirror circuit.
Introduction extensively used and experimented to yield
The primary reason for the success of the better results with each improvement [3].
microelectronics industry that has spanned Using multiple supply voltages (MSV) in
over decades is the reduction of dimensions VLSI circuits enables the division of
in VLSI chips [10]. With the lifestyle voltage into low and high domains. By this,
moving towards handheld and portable low power circuits have the liberty to
devices, power consumption has become of operate at lower voltages and high power at
prime importance for VLSI circuit higher voltages, ensuring that optimization
designers, keeping battery life in mind. is taken care. To achieve this, level shifters
Power consumption has a direct are used. They aid in mitigating issues like
consequence on reliability, therefore DC leakage. But, they again add on to
packaging must also be optimized [16]. power consumption and delay. Hence, it
Nanometer-scale technologies has been becomes essential to minimize the number
observing progress rapidly, going in hand of level-shifters and enhance their design
with new high-voltage design techniques. that is tailored for low-power, high
Nanometer technologies address the reliability systems that operate at extremely
increasing integration density needed for low voltage levels [10].
VLSI circuits and the low power demands A level shifter is a circuit designed to
of complex digital signal processing connect low core voltage systems with high
applications [9]. input-output voltage systems. Without the
Power consumption in VLSI circuits can be need of additional pins, level shifters enable
divided into three categories static power, communication between different modules
dynamic power and leakage power. The within the circuit. The traditional level
power consumed during the transition of shifter that has a cross-coupled PMOS load.
load capacitance between 2 different The two cross-coupled PMOS transistors in
voltage levels is dynamic power. It also the pull-up configuration create positive
depends on the frequency of operation. On feedback, which leads to a full VDD output
the other hand, static power comes from at the node. But, conventional level shifters
direct short circuits between the supply have issues such as varying delays,
voltage VDD and ground. Moving on, difference in current-driving capabilities of
leakage power is caused due to leakage transistors, excessive power dissipation and
currents (by substrate injection) and potential failure at low core supply voltage
subthreshold conduction, thereby [5].
necessitating methods to be developed to The purpose of this literature review is to
reduce leakage power [5]. By far, the most investigate and understand the innovations
efficient and straightforward technique that being led in the development of level shifter
can be implemented to reduce power designs for low power consumption. Level
dissipation in circuits is by decreasing the shifters are essential for ensuring reliable
supply voltage, the reason being that the signal conversion between different voltage
power consumed has a quadratic domains in contemporary integrated
relationship with the supply voltage. To circuits, especially as multi-voltage designs
combat the demand for low power become more prevalent due to aggressive
consumption, reduced size and high VLSI technology scaling. However, there
performance, CMOS technology is being are potential issues that must be addressed
like transistor contention, increased delays, techniques aim to reduce power
high power consumption and operational consumption and improve performance.
failures at low supply voltages. This gives Even stacking method has been proven
rise to development of new and more useful to reduce leakage power without any
effective designs. By analysing these compromise on output levels. The modified
designs, we identify the trade-offs, designs of the conventional, single supply
advantages, and limitations of existing and contention mitigated level shifter have
strategies, paving the way for the creation shown better performance metrics when
of enhanced level shifters tailored for compared to their original designs[1].
modern low-power VLSI applications. This The prevalent CMOS level shifters are
paper has the work related to types of level divided into 2 main types single supply
shifters and the significance of low power level shifters (SSLS) and dual supply level
designing of level shifters. Review the shifters (DSLS). SSLS circuits are preferred
existing literature and summarize their over DSLS due to reduced pin count, lesser
research and the trends low power routing congestion with decreasing
optimization techniques as mentioned in complexity, thereby reducing overall
related work. system cost. They use higher voltage only
for signal conversion. This paper focuses on
Related Works two traditional DSLS circuits, DSLS1 and
Managing both dynamic and static power DSLS2. DSLS1 makes use of differential
consumption in VLSI circuits is important. cascode voltage switched logic gate which
Dynamic power is caused due to switching although is a simple design, suffers from
activities and short circuit currents. Static performance degradation at low input
power is primarily due to leakage currents supply voltage. DSLS2 makes DSLS1
in CMOS circuits. As technology scales better by using PFET current mirror, by
down, it becomes crucial to mitigate enhancing performance and current driving
leakage power as it has a significant impact. capability. But the drawback faced here is
Level shifters play a key role in SoC increased power consumption due to
designs as they are responsible for varying leakage paths. The paper throws light on the
the voltage based on the need for optimized opportunity of improvements in
performance. They are essential in multi- conventional level shifters by integrating
voltage systems for converting logic signals voltage doublers, that can effectively raise
between the higher and lower voltage low supply voltage levels to super-threshold
levels. The conventional/traditional level levels, improving the performance of NFET
shifters suffer from issues like delay devices as a consequence. Care has been
variations, high power consumption and taken to exclude certain level shifter
failing to operate at lower supply voltages. designs that involve thick gate oxide
Using a single supply level shifter can transistors, ideal capacitors and low
mitigate some of these issues by reducing threshold transistors as they do not prove
pin count and routing congestion. But the useful for sub-threshold operation and
drawback faced here is that leakage power increase costs [8].
is increased. Advancements in level shifter PMOS and NMOS are implemented in
designs, such as the contention mitigated Conventional level shifters which use two
level shifter and the bootstrapped gate drive supply voltages, VDDL and VDDH.
Difference here is that single-supply level that both deep sub-threshold and standard
shifters are flexible in physical placement supply voltage levels are managed
due to single supply. Due to the increasing efficiently [12].
transistors in nanometer technologies,
research based on reducing the power Proposed Methodologies
consumption has taken a peak. High voltage This research focuses on improving single-
level shifters are basically designed to supply and conventional level shifters for
reduce both power consumption and delay leak power savings and performance
[10]. Designing of level shifters also focus improvement. Stack-based techniques are
on novel Dual Cascode Voltage Switch applied to modify conventional level
Logic (DCVSL) along with multi-threshold shifters by placing three NMOS transistors
CMOS transistors to maintain the speed and in the architecture to reduce sub-threshold
power consumption. It also has a dual stage leakage while maintaining output levels. In
design with cross coupled differential the case of single-supply level shifters,
inverters and diode that is connected to stacking uses four NMOS transistors to
NMOS for the swing and short circuit replace two transistors while keeping the
current [15]. initial widths but adding the stack
Reduction in size and addition of auxiliary arrangement in the design. Contention-
functions in digital integrated circuits has mitigated level shifters further improved
shown significant increase in power stack forcing by four other NMOS
dissipation per unit area. Power transistors without compromising the
consumption, among the various design reliability of the circuit; and improved
constraints like area and speed, stands out power saving and less delay are achieved.
as the most critical one [16]. In multiple Systematically, these modifications take
supply voltage (MSV) designs, level into the lower power dissipation and
shifters play a key role in connecting the leakage currents even at higher operating
multiple domains [10]. Another problem frequencies and higher integration densities
persisting in traditional designs of level of operation [1].
shifters is contention between pull-up A traditional delay is used to reduce the
(PMOS) and pull-down (NMOS), that short circuit and also minimize the delay. It
consequently increase both delay and power also optimizes the transistor count. It uses
usage. They have difficulty functioning two NMOS transistors N1 and N2 in input
efficiently at low core voltages and display stage. N2 drives the inverted input signal in
variations in delay due to inconsistent order to satisfy the threshold voltage drops
current driving capabilities among using two keeper PMOS transistors P1 and
transistors affected by VDDH and VDDL. P2. P1 limits short circuit current during
DC leakage combined with contention leads discharge and P2 leads the output node to
to significant power consumption and high supply voltage. A pull-down NMOS
extended delays, that cannot be considered transistor is added to decrease delay during
for applications requiring a wide voltage high-to-low output transitions [8].
range [13]. A newly designed level shifter, Conventional Level Shifters (CLS) depend
the modified Wilson current mirror hybrid on cross-coupled PMOS transistors for level
buffer (mwcmhb), facilitates full-range and shifting but have some limitations like
bidirectional level conversion. This ensures routing congestion and higher power
consumption due to the need for larger energy-efficient tasks in battery-powered
NMOS transistors. Single Supply Level biomedical devices is very crucial.
Shifters (SS-LS) has placement flexibility Therefore, this article focuses on converting
and also dynamically switches the inverter sub-threshold input voltages to higher
stage supply voltage depending on input output voltages. It integrates circuits with
state. Multi-VDD systems contain multiple special transistors to decrease the
voltage domains but have complexities in contention between PMOS and NMOS
routing. The High Voltage Level Shifter transistors which minimizes transition time
(HV-LS) integrates cross-coupled PMOS and power consumption during signal
transistors with thick gate oxides and a switching. Especially in current mirror
novel design where NMOS and PMOS configuration large gate lengths of PMOS
transistors receive input signals instead of a transistors sizing is done to reduce the
fixed DC voltage, providing high voltage power consumption. Comparative analysis
tolerance. This approach reduces leakage of this proposed design is done to achieve a
power, minimizes propagation delay, and better performance result [19].
significantly improves power and delay This method follows a new mixed-threshold
performance [10]. current mirror circuit to improve the voltage
There are different level shifters which suit transition while reducing the static power
their applications to address the transfer utilization. Low threshold transistors are
voltage domain through different design used in the pull-down networks to
techniques. The Voltage Level Shifter improvise both propagation delay and
(VLS), while offering rail-to-rail output for conversion range when reducing leakage
both sub-threshold and above-threshold current by placing the transistors in a super-
conditions, does not support optimization cut-off state when off. This super-cut-off
for speed. The Diode-Based VLS, while state integrates larger pull-down transistors
enhancing speed and power efficiency, uses without notably increasing the leakage
diode-connected PMOS transistors to limit current which play an important role in
short-circuit currents. The Resistor-Based maintaining performance in sub-threshold
VLS consumes less area and current as operation. Output buffer in this design
NMOS transistors are applied as resistors in transmits signals to make sure that the pull-
the PMOS latch. The Hybrid VLS offers a down network effectively pulls down
compromise between speed and low power, internal node voltages when the input signal
thus making it versatile for applications. is high [21].
Dual Cascode Voltage Switch Logic, on the Two methodologies for the design of level
other hand, provides via multi-threshold shifters that is Contention Mitigated Level
CMOS the advantage of both static and Shifter (CMLS) and Bypassing Enabled
dynamic power at the expense of some Level Shifters (BELS) are considered.
delay making it quite applicable under CMLS has a contention-reduction technique
modern portable devices operating in that reduces the increased delay and power
multiple voltage domains. Each of these is consumption by improving the performance
specifically designed to meet a particular in low voltage criteria. BELS has a bypass
performance, power, and area set function that allows signals to flow through
requirement [15]. a transfer gate when both the input and
Designing a low-power level shifter for output are at the same voltage level
(VDDL), the same scenario in dynamic BELS reduces power consumption by half
voltage scaling environments. reducing when operating in bypass mode [20].
dynamic charging and discharging currents The level shifter suggested in the article
to improve power efficiency in BELS integrates a multi-threshold CMOS
which overlooks the contention by ensuring technique to make it an effective voltage
that transistors not in operation are cut off conversion, and uses a mixed-threshold
[20]. current mirror circuit to address reduced
swing issues, thereby improving
Results and Discussion performance. To improve power efficiency,
This new level shifter effectively converts a auxiliary bias circuits are used to minimize
low voltage input of about 0.8 V to an leakage in low-threshold networks. The
output around 1.2 V, performing much level shifter operates across a wide voltage
better than the conventional approaches. It range from 0.12V to 1.2V, achieving a
achieves 67 percent power saving and a delay of 17.86ns and static power
delay reduction of 55 percent compared to consumption of 73.95pW at 0.3V [21].
traditional level shifters. The average power This level shifter achieves a propagation
consumption of the HV-LS is about 54.32 delay of 31ns and a static power dissipation
nW, with a rising delay of 87.79 ps, a of 1.16nW, with power dissipation for a 1-
falling delay of 63.22 ps, and an overall MHz input signal measured at 0.68µW.
delay of just 35.41 ps. Thus, it can be Simulations show that the level shifter
termed the most efficient and fastest for delivers good performance in terms of both
voltage level shifting [10]. power dissipation and delay. It operates
It envisions designing for optimized delay, correctly across various process, voltage,
power, and leakage current and finally fair and temperature (PVT) corners, with
performance results. The simulation results propagation delay and power dissipation
show that the effective decrease of exhibiting a lognormal distribution. The
propagation delay occurs by increasing the design effectively reduces transition time
supply voltage, while average power and power consumption, contributing to its
consumption increases correspondingly. overall energy efficiency [19].
The level shifter provides a perfect interface The modified conventional level shifter
for circuits running from different power gains a power consumption of 402.2264pW.
domains, dynamic power consumption The modified single supply level shifter
increased as the supply voltage decreases, consumes 108.641pW. The modified
which shows trade-off factors involved in contention mitigated level shifter operates
multi-voltage systems [15]. at 396.75pW, all demonstrating remarkably
Compared to conventional level shifter, reduced power consumption compared to
contention mitigated level shifter has 50% their conventional counterparts. While these
reduction in delay and 24% reduction in modifications effectively improve power
power consumption. BELS achieves a 50% efficiency, they result in a slight increase in
reduction in power and a 65% decrease in delay, which shows a trade-off between
delay leakage current of BELS is only 51% power savings and performance [1].
of that of the conventional shifter. In terms For multivoltage operation, a new dual
of power consumption, CMLS operates at supply level-up shifter is suggested. In
0.29pW at a supply voltage of 0.3V and addition to using less space, the suggested
design uses less power than the most
popular cross-coupled topology. The
suggested topology results in a 10%
reduction in physical area when compared
to the bootstrapping technique.
Additionally, corner simulations are run to
show the improved performance of the level
shifter that was suggested [8].

Types Power Delay Conclusion

Consumption A dual-supply level shifter where efficiency
is concerned, capacity, and area is
SS-LS 54.32 nW 35.41 ps
overall; significantly better than bootstrapping
87.79 ps technique in area reduction by 10% while
rising; 63.22 optimization of power consumption on
ps falling multiple configurations indicates great
VLS Increases with Reduces with suitability of this design for emerging low-
higher supply increased power applications. Modified conventional,
voltage supply
single supply, and contention-mitigated
voltage
level shifters have distinct improvements in
BMLS 73.95 pW at 17.86 ns power consumption of 402.2264 pW,
0.3 V 108.641 pW, and 396.75 pW, respectively.
WCMLS 1.16 nW static 31 ns All of these were achieved with slight
power; 0.68
sacrifice concerning delay but high
µW at 1 MHz
input performance addressing well interfacing
different voltage domains.
CMLS 402.2264 pW Slightly This innovative level shifter is extremely
(Modified higher than
permissive with ultra-low voltage
CLS) conventional
applications, yielding a 1.2V output at 0.8V
CMLS 402.2264 pW Slightly input while lowering power and delay.
(Modified higher than Multiplicity of thresholds is a very wealthy
CLS) conventional
feature in its integration within a low-power
system, while curtailment of short-circuit
current still maximizes the speed and
efficiency. Simulations proved its
performance superiority as compared to
traditional designs, particularly in
addressing leakage and improving
reliability during voltage domain
conversions. The design introduces a new
paradigm in the area addressing the current
needs of hi-end, low-power systems.
The low-power voltage level shifter being
proposed would efficiently and strongly Novel High Performance Dynamic Voltage
convert input voltages of sub-threshold Level Shifter” ARPN Journal of
levels into their corresponding output Engineering and Applied Sciences VOL.
levels. 10, NO. 10, JUNE 2015.
The design combines several advanced [7] A.Vidhyalakshmi, S.Sobana “CMOS
strategies, such as mixing thresholds of VLSI Architecture Of Low Power Level
current mirrors and auxiliary bias circuits Shifter” GRD Journals (ICIET) - 2016
for completing the energy efficiency goals [8] Bert Serneels, Michiel Steyaert and
without sacrificing the speed performance. Wim Dehaene " A High speed, Low
It does convert voltages, from very low Voltage to High Voltage LevelShifter in
0.12V to a maximum of 1.2V with a Standard 1.2V 0.13μm CMOS" IEEE 2006.
propagation delay of 17.86ns at 73.95pW [9] Vijay Kumar Reddy, G.Srinivasulu, "
static at 0.3V. The robustness of the circuit A Low To High Voltage Tolerant Level
over size variations spans its ability to stand Shifter For Low Voltage Applications"
and maintain performance even under quite (IJERT) . Vol. 2 Issue 8, August – 2013
severe conditions, thus leaving a good [10] Meenu Singh, Priyanka Goyal, Ajeet
fortune of versatility and possibilities of Kumar Yadav, “Design And Analysis Of
integration in state-of-the-art electronics Low Power Level Shifter” IJRCR Vol.2
systems. Issue.12, December 2014.
References [11] Karthikeyan. G1, Mathan. K2, Li-Fi
[1] Manoj Kumar, Sandeep K. Arya Sujata transmission of messages underwater. April
Pandey2 " Level Shifter Design For Low 2018 issue of the International Journal of
Power Applications" October 2010. Trendy Research in Engineering and
[2] Shipa Thakur and Rajesh Mehra Technology.
"CMOS Design and Single Supply Level [12] Nisha1, Rajesh Mehra " High Speed
Shifter using 90nm Technology" Level Shifter Design for Low Power
Conference on advance in Communicaton Applications Using 45nm Technology"
and Contol system 2013 (CAC2S 2013). IOSR Volume 6, Issue 2, Apr 2016.
[3] Norfazliana Binti Romli, Md. Mamun, [13] Mohammad Abbas.A,
Mohammad Arif Sobhan Bhuiyan and Kuppusamy.P.G " Design Of Level Shifter
Hafizah Husain, “Design of a Low Power Using Dual Cascode Voltage Switch For
Dissipation and Low Input Voltage Range Low Power Application" ISSN Volume 10,
Level Shifter in Cedec 0.18-μm Cmos Number 9 (2015).
Process” World Applied Sciences Journal [14] G.Srinivasulu, K. Venkata
19. Ramanaiah, K. Padma Priya. Underwater
[4] T Lehman, “Design of fast Low Power “Design Of Low Power High Speed Level
Floating High Voltage Level Shifters,” Shifter” IJRET Vol 03 No.04 May-2014.
Electronics letter 30 Jan 2014. [15] Jalla Chinnari, Hanumantha Rao
[5] G.Srinivasulu, K. Venkata Ramanaiah, Sistla, " Implementation Of Low Power
K. Padma Priya “Design Of Low Power Voltage Level Shifter Using GALEOR
High Speed Level Shifter” IJRET May Technique For Subthreshold Operation",
2014. IOSR Journal of VLSI and Signal
[6] Srinivasulu Gundala1, Venkata K. Processing (IOSR-JVSP) Vol 7 No 5, Sep
Ramanaiah and Padmapriya Kesari3 “A 2017.
[16] Marco Lanuzza, Pasquale
Corsonello,, “Low-Power Level Shifter for
Multi-Supply Voltage Designs,” IEEE
2012.
[17] Rasool Hosseini, Mehdi Saberi1 and
Reza Lotfi, " An Energy-Efficient Level
Shifter for Low-Power Applications " 2015
IEEE.
[18] Canh Q. Tran, Hirosh Kawaguchi and
Takayasu Sakurai " Low-power High-speed
Level Shifter Design for Block-level
Dynamic Voltage Scaling Environment",
2005 IEEE.
[19] Heng You, Jia Yuan, Weidi Tang,
Shushan Qiao and Yong Hei “An Energy-
efficient Level Shifter for Ultra Low-
Voltage Digital LSIs” IEEE 2020.
[20] Marco Lanuzza, Felice Crupi Sandro
Rao, Raffaele De Rose, Sebastiano
Strangio, and Giuseppe Iannaccone “An
Ultra-Low Voltage Energy Efficient Level
Shifter” IEEE DOI
10.1109/TCSII.2016.2538724.