Journal of Science, Computing and Engineering Research (JSCER)

Volume-6, Issue- 4, April 2023.

DOI: https://doi.org/10.46379/jscer.2023.060402

An Investigation of Low Power VLSI Design Techniques

R.Dinesh Kumar, M.Ramkumar Prabhu, K.Lakshmi Priya, M.Renuga, K.S.Senthil Kumar, V.Vennisa
Department of ECE, PERI Institute of Technology, Chennai, India.
Article Information
Abstract—low power has become a major subject in the electronics industries of today. For the
Received : 30 Jan 2023
design of VLSI chips, power dissipation has taken on equal importance to performance and area.
Revised : 02 Mar 2023 The main issues below 90nm due to increased complexity are lowering power usage and overall
Accepted : 18 Mar 2023 power management on chip. Due to the requirement to lower package costs and increase battery
Published 08 April 2023 life, power optimization is crucial for many systems. In low power VLSI designs, leakage current
:
also has a significant impact on power management. An growing portion of integrated circuits'
overall power dissipation is being accounted for by leakage current. This paper discusses
numerous power management techniques, methodologies, and tactics for low power circuits and
systems. Future challenges for designing low power high performance circuits are also discussed.
Corresponding Author:
R.Dinesh Kumar
Keywords: VLSI, Low Power, Power Dissipation, leakage current, process nodes, power management.

Copyright © 2023: R.Dinesh Kumar. This is an open access distribution, and reproduction in any medium, provided Access
article distributed under the Creative Commons Attribution License the original work is properly cited License, which permits
unrestricted use.
Citation: R.Dinesh Kumar, M.Ramkumar Prabhu, K.Lakshmi Priya, M.Renuga, K.S.Senthil Kumar, V.Vennisa. “An
Investigation of Low Power VLSI Design Techniques”, Journal of Science, Computing and Engineering Research, 6(4), 05-09,
2023.

I. INTRODUCTION
the majority of high performance. The fundamental methods
of low power design, such as clock gating to cut down on
The benefit of combining low-power components with dynamic power and multiple threshold voltage (multi-Vt) to
low-power design strategies is more important than ever cut down on Leakage current, are well known and supported
before. As components get smaller, more battery-powered, by current tools [17]. We may examine the number of
and require more functionality, the need for lower power changes in circuit design using Figure 1 by looking at power
consumption is rising considerably. In the past, area, dissipation [15].
performance, and cost were the three main concerns for
VLSI designers. The secondary problem was power
consideration. Due to the extraordinary development and
success of personal computers and wireless communication
systems, which require high-speed computation and
extensive functionality with minimal power consumption,
power is now a major challenge. Applications have different
reasons for wanting to cut back on power consumption. The
objective is to maintain an appropriate battery lifetime,
weight, and packaging cost for the category of micro-
powered battery-operated portable applications, such as cell
phones. The objective is to decrease the power dissipation of Fig. 1: Power dissipation Evolutions [15]
the electronics component of the system to a level that is
II. STRATEGIES OF LOW POWER
around half of the overall power dissipation for high
performance portable computers like laptops. The general Table I. Strategies for low power designs
purpose of power minimization for high performance non-
Design Level Strategies
battery operated systems, like workstations, is to lower the
system cost while ensuring long-term device reliability. Circuit/Logic level Logic styles,
Process technology has pushed power to the forefront of all
elements in such designs for such high performance systems. transistor sizing and energy
recovery
Power consumption from leakage has joined switching
activity as the main power management concern at process
nodes with technology below 90nm. Over the past ten years, Operating System Portioning, Power down
a variety of strategies [15] have been created to address the Level
continuously aggressive power reduction requirements of
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more of these parameters is part of optimizing for greater

Threshold reduction, power. This section briefly discusses their significance in
Technology Level multi threshold devices the power optimization process.
4.1. Voltage
Regularity, locality, concurrency Voltage reduction is the most effective method of
reducing power usage due to its quadratic relationship with
Software level power. A factor of two reductions in supply voltage results
Pipelining, Redundancy, in a factor of four reductions in power consumption without
the need for any additional circuits or technologies.
Architecture level Data encoding Unfortunately, there is a speed penalty for lowering the
Various methods for reducing power consumption are supply voltage, and delays increase dramatically as Vdd
available at various stages of the VLSI design process approaches the device's threshold voltage Vt. Modifying the
shown in above Table I. Utilizing a variety of solutions at threshold voltage of the devices is one method for lowering
different stages of the VLSI Design process can result in the supply voltage without sacrificing throughput. By
effective power management. Therefore, designers must lowering the Vt, the supply voltage can be reduced without
adopt a wise strategy for maximizing power consumptions sacrificing speed. The requirement to provide suitable noise
in their creations. margins and restrict the growth in subthreshold leakage
current sets the limit of how low the Vt can fall [6, 8, 10].
III. POWER DISSIPATION BASICS
4.2. Physical Capacitance
In an electronic circuit the three components are
responsible for power dissipation: static power, dynamic The dynamic power usage is proportional to the physical
power, and short circuit power. The power dissipated when capacitance being switched. As a result, in addition to
charging or discharging capacitors makes up the majority of running at low voltages, decreasing capacitances provides
dynamic power, which is described below [5, 6]: another method for reducing power usage. Capacitances can
be reduced by utilizing less logic, smaller devices, and fewer
PDynamic = CL Vdd2 α f (1) and shorter wires [6, 8, 10]. However, as with voltage, we
Where CL is a load capacitance which functions of fan- are not free to optimize the capacitances independently. For
out, wire length, and transistor size, Vdd is a function of example, reducing device sizes reduces physical capacitance
supply voltage, which has been decreasing with each but also reduces the transistor's current drive, causing the
subsequent process node, f is a function of clock frequency, circuit to function more slowly.
which is increasing with each succeeding process node. The 4.3. Switching Activity
supply voltage (Vdd), switching threshold (Vt), and
transistor size all influence static power or leakage power The switching activity has two components: Fclk, which
(Figure2). Leakage becomes a more major source of energy determines the average periodicity of data arrivals, and
use as process nodes shrink, absorbing at least 30% of total E(sw), which specifies how many transitions each arrival
power [2]. Crowbar currents, which occur when both the will generate[14]. E(sw) is reduced by selecting appropriate
PMOS and NMOS devices are turned on at the same time, algorithms, optimizing the logic topology, and optimizing
also contribute to leaky power dissipation [17]. Most circuit the logic level, all of which result in less power[15]. The
level minimization strategies focus solely on reducing sub- data activity E(sw) is multiplied by the physical capacitance
threshold leakage without taking into account the impacts of C to get the switch capacitance Csw=C. E(sw) describes the
gate leakage [15]. average capacitance charge throughout each data period,
while Fclk determines the power utilised by the CMOS
[4] has been proposed for this MTCMOS method to circuit[9].
reduce sub-threshold leakage current in sleep mode. Figure
2 depicts the many components of CMOS that are V. POWER MINIMIZATION TECHNIQUES
responsible for power dissipation. This section discusses (TABLE II) the various
techniques of minimizing power at various levels:
5.1. Scaling the supply voltage (Voltage Scaling)
This method can be quite effective in lowering the power
dissipation, but it frequently requires new IC fabrication
processing [13].
5.2. Reducing Chip and package capacitance
IV. LOW POWER DESIGN SPACE
This can be accomplished by the development of
According to the above section, there are three degrees processes such as SOI with partially or completely depleted
of freedom in the VLSI design space: voltage, physical wells, CMOS scaling to submicron device sizes, and
capacitance, and data activity. Attempting to lower one or improved interconnect substrates such as multi-chip module
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(MCM). This method can be quite effective, but it is also

very costly [15, 19].
Technology selection is followed by an emphasis on
5.3 USING POWER MANAGEMENT STRATEGIES power-saving design strategies. In Figure 5, the first step is
to choose the proper logic gate from the library of common
Effective power management necessitates the use of the
cells. A conventional cell library has many versions of each
appropriate technology, optimized libraries, IP (intellectual
gate with various drive strengths, sizes, delays, multiple-
property), and design approach [1, 19]. Figure 3 depicts an
threshold voltages, and power consumption. Each gate
efficient power management method.
employs the fewest transistors possible. Cell designers often
5.3.1. The Role of Technology Selection: design and characterize the gates to function at voltages as
much as 30% lower than the power-supply voltage because
One of the most important parts of power management is
this is the primary parameter for managing active power [1].
proper technology selection [1]. Each technological
breakthrough seeks to enhance performance, density, and
power consumption. The standard method for generating a
new generation of technology is to use constant-electric-
field scaling. To retain the same electric field, process
designers adjust both the applied voltage and the oxide
thickness [13,16]. With each new technological node, this
strategy reduces power by around 50%. However, as the
voltage decreases, the threshold voltage must similarly
decrease in order to satisfy the performance requirements of
that technology. Unfortunately, this scaling raises the
subthreshold current and thus the leakage power. To address
this limitation, process engineers employed a more
generalized kind of scaling rather than constant-field scaling
for processes of 65 nm or less. Each technology usually has Figure 4: Tradeoff between leakage and Power
two variants since it is impossible to improve a technology
for both performance and leakage at the same time. One Smaller currents are produced when the power supply
version seeks high performance, while the other seeks low voltage is reduced, which causes additional delay. However,
leakage. The oxide thickness, supply voltage, and threshold if the design does not test the limits of a particular
voltage are the key variations between the two. To attain a technology, the slowness is acceptable. The leakage current
reasonable performance, the technological variation with the in the device is decreased by raising the threshold voltage.
thicker gate oxide aims for a low-leakage design and must Designing logic gates with multiple-threshold-voltage
handle a higher voltage [9]. When choosing a technology to components, such as conventional high and low threshold
optimize the power for a specific design, you must consider voltage components is another method for reducing power
both aspects: the need for smaller geometry to reduce active leakage [16]. Figure 4 depicts the relationship between gate
power and the necessity for a low-leakage variation to delay and leakage power.
reduce leakage. 5.3.3 CAD Methodologies and Technique:
Trade off related with power management techniques
(Table III)

Methodology Impact
Power Po Tim Are
Arc De Ve Impl
Reduction wer ing a
hite sign rifi em
Techniqu Benefit Penalty Penalty
cture cation entation
e
Multi
Vt
Me Littl Litt Lo Lo No Low
optimizati
Figure 3: Selection of Technologies for effective power dium e le w w ne
on
management [9]
Clock Me
Gating dium
Littl Litt Lo Lo No Low
e le w w ne
5.3.2 Circuit-Design Techniques:

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optimization. In conclusion, a number of problems and

Multi significant difficulties with low power designs are:
supply
Large Some Little High Medi Low Mediu 1. Scaling of Technology
voltage
um m
The following parameters are related to it: Die size
Power Huge grows by 14% (Moore's Law), Capacitance per node
Shut off decreases by 30%, Electrical nodes expand by 2X, Supply
Some Some High High High High
Voltage decreases by 15%, and Frequency increases by 2X.
Dynamic Relatively 2.7 X more active power will be added to address
and these problems.
Large Some Some High High High High
adaptive
Voltage 2. Leakage power:
frequency Vt will be scaled to match frequency requirements,
scaling which leads to excessive leakage power. a low voltage/low
Substrate threshold technology and circuit design strategy that aims
Biasing for supply voltages of roughly 1V and operates at lower
Large Some Some Mediu None None High thresholds.
m
3. Power management strategies that change supply
These power-management strategies are effectively voltage and execution speed in response to activity
supported by EDA software tools today [3]. Additionally, monitoring
they offer electricity savings during deployment. At several
levels of design abstraction, ranging from algorithmic and 4. Low power connectivity, low swing or activity
system levels to layout and circuit levels, low power VLSI approach, using advanced technology.
systems are possible. 5. Improvement of power conscious techniques and tools
VI. LOW POWER MANAGEMENT IN PHYSICAL DESIGN forlayout optimization, behavioral synthesis and logic
synthesis.
Physical design tools correctly read power intent and
implement the layout, from special cell placement to routing 6. The techniques of power saving that recycle the signal
and optimization across power domains in the presence of energies using the adiabatic switching principals rather
numerous corners, modes, and power states, as well as them dissipating them as a heat and promising in certain
manufacturing variability [2, 3]. The use of numerous applications where speed can be trades for low power.
voltage islands (domains) to minimize power in physical VIII. CONCLUSION
design is becoming more widespread, allowing some blocks
to require lower supply voltages than others or to be totally From this work we have found that the wear resistance
switched off for specific modes of operation [6]. Clocks for polypropylene with acacia 3% plate is higher than that of
consume a substantial amount of dynamic power. To save virgin polypropylene plate. This work is still continued with
power, low-power clock tree synthesis (CTS) solutions [5, 6] varying percentage of acacia with polypropylene material.
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