Black BaaklM

Dr. K.V.K.K. Prasad

&
Kattula Shyamala

DT Editorial Services

Published by:
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dreamlech
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©Copyright 2016 by Dreamtech Press, 19-A, Ansari Road, Daryaganj, New Delhi-110002

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 Preface
As the impact of electronic systems on every walk of life is becoming more and more, the demand for very
low cost, very small and very reliable systems is also increasing exponentially. The rapid developments in
the semiconductor technology is leading to very tiny systems that have the power of super-computers of
the last decade. Designing such tiny systems is now being witnessed in every field—mobile
communications, industrial electronics, ubiquitous computing and so on.
In good old days, hardware development used to be an extremely challenging task involving
interconnecting hundreds and thousands of discrete components. With the advent of Programmable Logic
Devices, Field Programmable Gate Arrays and Application Specific Integrated Circuits, the hardware is
becoming more reliable, the size is reducing and the power consumption is also reducing drastically.
Designing hardware using these advanced chips calls for specialized skills in understanding the
semiconductor fabrication process, learning the design process, knowledge of Electronic Design
Automation tools and expertise in Hardware Description Languages.
It is very important to realize that the whole process of designing systems is changing rapidly due to the
developments in VLSI technology during the last decade. The power of VLSI is increasing day by day and
interestingly; designing hardware is now more of ‘software development’.
The purpose of writing this book is to demystify hardware design for software engineers by introducing
VLSI design to computer science majors who do not have in-depth knowledge of hardware. With the
availability of sophisticated Electronic Design Automation (EDA) tools and Hardware Description
Languages (HDLs), designing systems that consist of both hardware and software is now extremely easy.
This book takes you through this process and helps you in designing FPGAs and SOCs.

The Targeted Audience

This book is for computer science majors who would like to develop advanced electronic systems
involving FPGAs, SoCs and ASICs. A basic background in digital electronics is all that is assumed to learn
the various topics covered in this book.
Final year B.E./B.Tech/M.Tech students will find this book useful for learning the complete theory and
practical aspects of VLSI technology and FPGA design.
Practicing engineers will find this book very handy to learn how to design and develop industry standard
FPGA based hardware and software.
Preface

Organization of the Book

This book is divided into 14 chapters. At the end of each chapter, questions and exercises are given.
Chapter 1 gives an introduction to the VLSI design. The traditional approach to hardware design is
described and how this approach is being replaced by design automation using EDA tools to design
FPLDs, FPGAs and ASICs is described. The concept of System on a Chip is also introduced in this chapter.
Chapter 2 describes VLSI design technologies. Combinatorial design technique, sequential design
technique and state machine logic design technique are described briefly. The various design issues such
as meta-stability, noise margin, power, fan-out and timing considerations are discussed in detail.
Chapter 3 deals with CMOS VLSI design. MOS technology and fabrication process is described briefly.
nMOS, pMOS, CMOS and BICMOS technologies are explained and a comparison of different processes is
made.
Chapter 4 describes the various building blocks of a VLSI circuit. Computer, memory and communication
interface architectures are described briefly. Mixed signal interfaces are also discussed.
Chapter 5 explains the VLSI design process and issues such as such design for testability, technology
options, power consumption, package selection, clock mechanisms and mixed signal design.
Chapter 6 gives an overview of various Electronic Design Automation (EDA) tools. Various front-end
tools and backend tools are explained along with their salient features.
Chapter 7 focuses on Hardware Description Languages. An overview of VHDL and Verilog is presented
along with illustrative examples.
Chapter 8 deals with IC design. PLA, CPLD, FPGA and ASIC are explained and their pros and cons are
discussed.
Chapter 9 describes the process of designing hardware using FPGAs.
Chapter 10 illustrates the implementation examples for VHDL/Verilog lab exercises.
Chapter 11 explains how to program an FPGA development board for various peripherals and then how
to communicate through a PC.
Chapter 12 gives a case study of development of a communication system using FPGA development
board.
Chapter 13 a case study of system on a chip development.
Chapter 14 gives a glimpse of future trends in VLSI technology.
Appendix A gives answers to review questions given at the end of each chapter.
Appendix B gives list of some important Internet resources and reference textbooks. As the field of VLSI
design is changing rapidly, it is important for every professional to keep pace with these developments by
constantly referring to the web sites listed in this appendix and also subscribing to professional journals
and magazines.
Appendix C gives a list of acronyms and abbreviations.
Appendix D gives glossary of important terms used in VLSI design. A quick study of this appendix will
make you familiar with the VLSI ‘jargon’ and this is a good place to start reading the book if you are
reading about VLSI for the first time.

Credits
The author thanks the following engineers for their help in preparation of the manuscript: A. Veerraju,
Silpa, Atchut Ram Chaudury.

iv
 Table of Contents
Preface ....................................................................................................................................... iii

Chapter 1: Introduction to VLSI Design ..................................................................................... 1

Traditional Approach to Hardware Design ....................................................................................................... 2
New Paradigms in Hardware Design ................................................................................................................ 3
VLSI Technology: Fundamentals and Applications .......................................................................................... 4
Advantages of VLSI Technology .................................................................................................................. 4
Challenges in VLSI Technology .................................................................................................................... 4
Evolution of the Integration Levels .............................................................................................................. 5
VLSI Design Process ...................................................................................................................................... 6
VLSI Design Methodology ............................................................................................................................ 7
How to Specify a System? ............................................................................................................................. 7
How to Convert Specifications into a Chip? ................................................................................................ 8
Electronic Design Automation ............................................................................................................................ 9
ASIC ............................................................................................................................................................... 9
ASIC Design Flow ....................................................................................................................................... 10
Field Programmable Gate Array (FPGA) ................................................................................................... 10
FPGA Design Flow ............................................................................................................................................ 11
System on Chip Designs.............................................................................................................................. 13
Summary............................................................................................................................................................ 14
Review Questions .............................................................................................................................................. 14

Chapter 2: VLSI Design Technologies...................................................................................... 15

Combinatorial Design Technique ..................................................................................................................... 16
Boolean Equation......................................................................................................................................... 19
Schematic ..................................................................................................................................................... 19
Canonical Form............................................................................................................................................ 20
Standard Form ............................................................................................................................................. 21
Factored Form .............................................................................................................................................. 22
Don’t Care Combinations............................................................................................................................ 22
Sequential Design Technique............................................................................................................................ 26
Synchronous Sequential Circuits ................................................................................................................ 27
Table of Contents

Asynchronous Sequential Circuits.............................................................................................................. 31

State Machine Logic Design Technique............................................................................................................ 31
Design Issues ..................................................................................................................................................... 34
Fan-Out ........................................................................................................................................................ 34
Meta-Stability............................................................................................................................................... 34
Timing .......................................................................................................................................................... 35
Summary............................................................................................................................................................ 36
Questions ........................................................................................................................................................... 36
Exercises ............................................................................................................................................................. 36

Chapter 3: CMOS VLSI Design.................................................................................................. 37

MOS Technology and Fabrication Process ....................................................................................................... 38
Fabrication Process ...................................................................................................................................... 38
pMOS ................................................................................................................................................................. 41
nMOS ................................................................................................................................................................. 42
CMOS ................................................................................................................................................................. 44
The p-well Process ....................................................................................................................................... 44
The n-well Process ....................................................................................................................................... 45
The twin-tub Process ................................................................................................................................... 45
BiCMOS.............................................................................................................................................................. 46
Comparison of Different Processes................................................................................................................... 46
Power Dissipation ....................................................................................................................................... 46
Propagation Delay ....................................................................................................................................... 47
Summary............................................................................................................................................................ 47
Questions ........................................................................................................................................................... 48
Exercises ............................................................................................................................................................. 48

Chapter 4: Building Blocks of a VLSI Circuit ........................................................................... 49

Computer Architecture ..................................................................................................................................... 50
MUX ............................................................................................................................................................. 50
Decoder ........................................................................................................................................................ 52
Priority Encoder........................................................................................................................................... 53
Magnitude Comparator............................................................................................................................... 54
Bit-Adder ..................................................................................................................................................... 55
Memory Architectures ...................................................................................................................................... 57
Shifter ........................................................................................................................................................... 57
ROM ............................................................................................................................................................. 58
RAM ............................................................................................................................................................. 59
Communication Interfaces ................................................................................................................................ 59
Parallel Data Transmission ......................................................................................................................... 60
Parallel Communication Interface .............................................................................................................. 61
Mixed Signal Interfaces ..................................................................................................................................... 61
Summary............................................................................................................................................................ 61

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 Table of Contents

Questions ........................................................................................................................................................... 62
Exercises ............................................................................................................................................................. 62

Chapter 5: VLSI Design Issues ................................................................................................. 63

Design Process ................................................................................................................................................... 64
Design for Testability ........................................................................................................................................ 64
What is testing?............................................................................................................................................ 65
Fault Coverage............................................................................................................................................. 66
The Single Stuck-At Fault Model ................................................................................................................ 66
Technology Options .......................................................................................................................................... 67
Full-Custom Design..................................................................................................................................... 67
Semi-Custom Design ................................................................................................................................... 68
Cell-Based Designs ...................................................................................................................................... 68
Array-Based Designs ................................................................................................................................... 69
Power Calculations............................................................................................................................................ 70
Package Selection............................................................................................................................................... 70
Clock Mechanisms............................................................................................................................................. 71
Mixed Signal Design.......................................................................................................................................... 73
Summary............................................................................................................................................................ 74
Review Questions .............................................................................................................................................. 74

Chapter 6: EDA Tools: An Overview ........................................................................................ 75

EDA .................................................................................................................................................................... 76
Taxonomy of Tools ...................................................................................................................................... 76
Altera’s Quartus II Software ....................................................................................................................... 79
Microwind Tools.......................................................................................................................................... 79
Xilinx Tools .................................................................................................................................................. 79
Architecture Design........................................................................................................................................... 79
Top-Down Design ....................................................................................................................................... 80
Bottom-Up Design ....................................................................................................................................... 80
Design Entry ...................................................................................................................................................... 81
Schematic Editor .......................................................................................................................................... 81
VHDL Editor/Verilog Editor...................................................................................................................... 82
Block Editor.................................................................................................................................................. 82
Synthesis Tools: XST, Synplify, and Leonardo Spectrum................................................................................ 83
Creating a new Project using the Xilinx Project Navigator ....................................................................... 83
Functional Verification ...................................................................................................................................... 97
Black Box Verification ................................................................................................................................. 98
White Box Verification ................................................................................................................................ 98
Timing Verification............................................................................................................................................ 99
On-Chip Debugging .......................................................................................................................................... 99
Summary.......................................................................................................................................................... 100
Questions ......................................................................................................................................................... 100

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Table of Contents

Exercises ........................................................................................................................................................... 100

Chapter 7: HDL Simulation and Synthesis ............................................................................. 101

Overview of VHDL ......................................................................................................................................... 102
VHDL Code Structure ............................................................................................................................... 103
Syntax and Semantics of VHDL................................................................................................................ 104
NOT Gate ................................................................................................................................................... 106
OR Gate ...................................................................................................................................................... 108
AND Gate .................................................................................................................................................. 111
NOR Gate ................................................................................................................................................... 113
NAND Gate ............................................................................................................................................... 115
XOR Gate ................................................................................................................................................... 117
XNOR Gate ................................................................................................................................................ 119
D Flip-Flop ................................................................................................................................................. 121
VHDL Implementation ............................................................................................................................. 121
Decade Counter ......................................................................................................................................... 124
Overview of Verilog ........................................................................................................................................ 127
Verilog Code Structure.............................................................................................................................. 128
Syntax and Semantics of Verilog .............................................................................................................. 129
Data Types ................................................................................................................................................. 130
Data Objects ............................................................................................................................................... 130
NOT Gate ................................................................................................................................................... 130
OR Gate ...................................................................................................................................................... 131
AND Gate .................................................................................................................................................. 132
NOR Gate ................................................................................................................................................... 133
NAND Gate ............................................................................................................................................... 133
XOR Gate ................................................................................................................................................... 134
XNOR Gate ................................................................................................................................................ 134
D Flip-Flop ................................................................................................................................................. 135
Counter ...................................................................................................................................................... 136
Simulation ........................................................................................................................................................ 136
Synthesis .......................................................................................................................................................... 137
Behavioral Modeling ....................................................................................................................................... 140
Timing Analysis............................................................................................................................................... 141
RTL Simulation ................................................................................................................................................ 141
VITAL Simulation ........................................................................................................................................... 141
Summary.......................................................................................................................................................... 142
Questions ......................................................................................................................................................... 142
Exercises ........................................................................................................................................................... 142

Chapter 8 IC Design ................................................................................................................ 143

PLAs ................................................................................................................................................................. 144
PLDs ................................................................................................................................................................. 146

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 Table of Contents

FPGA ................................................................................................................................................................ 148

Antifuse FPGA........................................................................................................................................... 149
Flash FPGA ................................................................................................................................................ 150
SRAM FPGA .............................................................................................................................................. 150
ASIC ................................................................................................................................................................. 151
Selection of an Appropriate Integrated Circuit .............................................................................................. 151
Summary.......................................................................................................................................................... 151
Questions ......................................................................................................................................................... 152
Exercises ........................................................................................................................................................... 152

Chapter 9: FPGA Design Process........................................................................................... 153

Architectures of Popular FPGAs..................................................................................................................... 154
Basic FPGA Architecture........................................................................................................................... 154
Choosing an FPGA .......................................................................................................................................... 156
IP Cores ...................................................................................................................................................... 156
FPGA Configuration.................................................................................................................................. 157
Configuration Modes ................................................................................................................................ 158
FPGA Design Process ...................................................................................................................................... 159
FPGA Design Flow .................................................................................................................................... 159
Designing FPGA-Based PCBs ................................................................................................................... 161
FPGA Families of Different Vendors .............................................................................................................. 163
Illustration: FPGA Families of Xilinx........................................................................................................ 163
FPGA Design Examples .................................................................................................................................. 164
Stack Implementation using VHDL.......................................................................................................... 164
Device Utilization Summary ..................................................................................................................... 169
Queue Implementation using VHDL ....................................................................................................... 170
Shift Register implementation using VHDL ............................................................................................ 175
Summary.......................................................................................................................................................... 179
Questions ......................................................................................................................................................... 179
Exercises ........................................................................................................................................................... 180

Chapter 10: VHDL Implementation Examples ........................................................................ 181

Adder ............................................................................................................................................................... 182
Multiplier ......................................................................................................................................................... 186
Multiplexer ...................................................................................................................................................... 192
16 X 1 Multiplexer...................................................................................................................................... 195
Summary.......................................................................................................................................................... 198
Questions ......................................................................................................................................................... 198

Chapter 11: Case Study: Xilinx Development Board ............................................................. 199

Xilinx ISE 10.1 .................................................................................................................................................. 200
Design Entry in HDL/Schematic.............................................................................................................. 200
Simulation and Synthesis (Design Verification) ...................................................................................... 201

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Table of Contents

Design Implementation ............................................................................................................................. 201

Development Board Architecture ................................................................................................................... 201
Interfacing with Peripherals............................................................................................................................ 202
Summary.......................................................................................................................................................... 208
Questions ......................................................................................................................................................... 208
Exercises ........................................................................................................................................................... 208

Chapter 12: Case Study: Implementation of a Communication System ............................... 209

Xtreme DSP Board Overview.......................................................................................................................... 210
The Xtreme DSP Kit for Virtex-4............................................................................................................... 210
Design Details .................................................................................................................................................. 212
Implementation Details ................................................................................................................................... 212
Creating a New Project using the Xilinx Project Navigator .................................................................... 213
Generation of 1 KHz Sine Wave (Tone) Component ............................................................................... 217
Simulation ........................................................................................................................................................ 225
Simulation in ModelSim............................................................................................................................ 226
AM Modulator Implementation ............................................................................................................... 231
Simulation Results of AM Modulation..................................................................................................... 238
AM Demodulation..................................................................................................................................... 238
Envelope Detector ..................................................................................................................................... 238
AM Demodulation Simulation Results .................................................................................................... 246
Device Utilization ...................................................................................................................................... 247
Testing Environment ....................................................................................................................................... 247
Testing the Code on FPGA Development Board ..................................................................................... 247
Challenges in Signal Processing using FPGA .......................................................................................... 261
Summary.......................................................................................................................................................... 261
Questions ......................................................................................................................................................... 261
Exercises ........................................................................................................................................................... 262

Chapter 13: Case Study: System-On-Chip Development ...................................................... 263

System-On-Chip Requirements ...................................................................................................................... 263
Design .............................................................................................................................................................. 265
Hard Core/Hard IP ................................................................................................................................... 266
Soft Core/Soft IP ....................................................................................................................................... 266
Firm Core/Firm IP .................................................................................................................................... 266
Implementation ............................................................................................................................................... 266
Selection of Platform based on Application ............................................................................................. 267
Summary.......................................................................................................................................................... 268
Questions ......................................................................................................................................................... 268
Exercises ........................................................................................................................................................... 268

Chapter 14: Future Trends ...................................................................................................... 269

Ubiquitous Computing and Pervasive Computing Technologies ................................................................ 270
VLSI Design Trends......................................................................................................................................... 271
Summary.......................................................................................................................................................... 273
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 Table of Contents

Appendix A: VHDL and Verilog Examples ............................................................................. 275

Appendix B: Internet Resources ............................................................................................ 329

Appendix C: Acronyms and Abbreviations............................................................................ 331

Glossary ................................................................................................................................. 337

Index ........................................................................................................................................... 341

xi
 1
Introduction
to VLSI Design
If you need information on: See page:
Traditional Approach to Hardware Design 2
New Paradigms in Hardware Design 3
VLSI Technology: Fundamentals and Applications 4
Electronic Design Automation 9
FPGA Design Flow 11
Chapter 1

In the recent years, there have been rapid developments in the field of semiconductor electronics.
Consequently, hardware design methodology has also seen various changes. In this chapter, you learn
about the traditional approach to hardware design and the changing trends in the hardware designing
approach. The chapter provides an overview of Very Large Scale Integration (VLSI) technology. It also
explains design flow using Electronic Design Automation (EDA) tools. Towards the end, you learn how
the design automation leads to System-on-Chip (SOC) solutions.

Traditional Approach to Hardware Design

People in their 60’s and 70’s will generally tell you a lot of interesting stories about their experiences
related to hardware design and experiments with bulky vacuum tubes, transistors, resistors, inductors,
and capacitors. For people who were not electronics engineers, hardware development used to be like
black art!
Well! Past is past, let’s take a look at various steps currently involved in designing a system are as follows:
 Work out the specifications of the system; for example, a mobile phone
 Decide what is implemented in hardware and what is implemented in software
 Carry out a design using various components, develop a Printed Circuit Board (PCB), and test the
PCB for the hardware
 Develop the necessary programs for the software
 Integrate the hardware and software
 Test the entire system
Developing a PCB is a herculean task. Imagine that there are no microprocessors and you have to develop
the entire PCB using transistors, resistors, and capacitors. Now imagine the size of the PCB and the mobile
phone! Designing such hardware is called designing using discrete components.
Even about three decades ago, hardware used to be very bulky due to the discrete components used in the
circuits. Subsequently, a number of Integrated Circuits (ICs) that can carry out specific functionality have
made life a bit easier. However, hardware still contain hundreds and thousands of components. As the
number of components (called component count) increases, the power dissipation will be more and the
reliability of the product will go down. Every designer strives to reduce the component count. This led to
the developments in the integration of more and more components into one IC. Therefore, highly
powerful ICs started appearing in the market; for example, a single IC for voice coding, a video amplifier,
or a high capacity memory.
Surprisingly, even today, several hardware engineers take the traditional approach of combining a large
number of components to design hardware to meet a particular functionality. However, this approach has
the following drawbacks:
 A system consists of both hardware and software. Software does not weigh anything; the entire
weight of the system depends on its hardware. Therefore, the weight of the system will be very high if
its component count is high.
 The space occupied by the components will be high resulting in large-sized systems.
 The higher the component count, the higher will be the failure rate. Therefore, reliability of the system
will be very low.
 Power consumption will be high, as each component will consume some power.
 Development time and cost will be very high, as debugging/testing will take lot of time.
 Production cost will be very high because inventory will be more as the component count increases.

2
 Introduction to VLSI Design

Due to these drawbacks, hardware engineers are no longer using the traditional approach of having a
large number of components on the PCB. The aim is to have a few (or even one) chips do the entire system
functionality.

New Paradigms in Hardware Design

The fast pace of developments in technology has resulted in exciting applications that have affected all
walks of life, such as entertainment, health care, transportation, banking, and defense. Not surprisingly,
the competition among the hardware development organizations is also increasing tremendously.
Nowadays, for such organizations to survive, they need to develop systems at the lowest cost, sell the
systems at the minimum price, and develop the system in the shortest possible time. To achieve this
objective, you need to keep the following goals in mind:
 Reduce the development cost and time
 Reduce the production cost of the system
 Improve the reliability of the system
 Decrease the hardware size, weight, and power consumption
 Provide flexibility to make changes to the hardware in the field. Yes, make changes to the hardware in
the field; in other words, develop reprogrammable hardware.
To achieve these goals, the traditional approach to hardware design is no longer of any use. Now, the
objective is to develop a few ICs, and if possible, a single IC, which will achieve the complete system
functionality. The fast pace of developments in semiconductor technology has led to the development of
small chips that can hold a lot of logic and memory. These chips are of the following types:
 Field Programmable Logic Device—Offers the highest amount of logic density and, the highest
performance. These advanced devices also offer features such as built-in hardwired processors,
substantial amounts of memory, clock management systems, and support for many of the latest, very
fast device-to-device signaling technologies.
 Application Specific Integrated Circuit (ASICs)—is an integrated circuit (IC) that is customized for a
particular use, rather than for a general-purpose. For example, a chip designed solely to run a cell
phone is an ASIC.
 System on Chip (SOC)—is a system on a VLSI chip that has all needed analog as well as digital
circuits, processors and software, for example, single-chip mobile phone.
These devices are capable of providing the functionality of hundreds and thousands of discrete
components.
Another interesting development is in terms of the methodology used to develop systems using these
devices. You can buy these devices from a manufacturer and you can just write software to program these
devices. Yes, you need to write software to do hardware development. Therefore, developing the
hardware is similar to doing programming.
Hardware development has now become fun, as it can be done sitting in front of a computer and there is
no need to burn fingers with soldering irons or dirty hands with solder. This has become possible due to
the VLSI technology. An excellent example of the VLSI technology is a mobile phone, which is a sleek, low
power consuming, and lightweight device. You cannot manufacture a mobile phone at such a low cost if it
was not developed using the VLSI technology.
Let’s now learn the basics and detailed description of the design process for VLSI technology.

3
Chapter 1

VLSI Technology: Fundamentals and Applications

The electronics revolution started in 1920 when the vacuum tube was discovered leading to diodes,
triodes, and pentodes whose descriptions you will find in old books found in museums. The invention of
transistor in 1948 laid the foundation for semiconductor electronics. In late 1950’s, with the development
of lithography techniques, Small Scale Integration (SSI) technology came into picture and the basic gates
were developed. The first integrated chip was SSI chips with a few gate counts. Subsequently in early
1960’s, gate oxide technology was developed leading to P-type metal-oxide-semiconductor logic (PMOS)-
based devices, such as registers, multiplexers, and decoders. In late 1960’s, with the development of ion
implantation technology, N-type metal-oxide-semiconductor logic (NMOS) devices have been developed,
such as the memory chips. In late 1970’s, Complementary metal–oxide–semiconductor (CMOS) (CMOS)
devices, particularly powerful microprocessors, are available with the developments in multi-layer
interconnect technology. All these developments have led to smaller and smaller devices. The packaging
of the devices also evolved from metal packaging to ceramic packaging to plastic packaging, leading to
further reduction in size and weight, and of course cost.
In the year 1965, Gordon Moore, co-founder of Intel Corporation, predicted that the size of the transistor
would continue to shrink resulting in doubled transistor density and doubled performance every 18 to 24
months. This is known as Moore’s law and surprisingly, Moore’s law has proved to be correct. You are
indeed witnessing the growth in the semiconductor technology at this pace. The power of mainframe
computers of yesteryears is now available on our desktops. If you were to develop a mobile phone with
the technology of 1960’s, the mobile phone probably would weigh a few hundred kilograms!

Advantages of VLSI Technology

Billions of dollars are spent every year on research in VLSI because of the immense advantages of this
technology. These advantages are as follows:
 Size of the devices will reduce; and therefore, the size of the systems will reduce.
 Weight of the device/system will also reduce.
 Power consumption of the device/system will reduce.
 Development time will be less as compared to discrete hardware design.
 The cost of the end system will be reduced benefiting the end users.
 The design of the system can be protected by the design organization, as it is difficult to copy the
design. This was not possible with discrete design of hardware.
 The reliability of the system will increase due to less number of components.

Challenges in VLSI Technology

VLSI technology is a very exciting area to work on. However, it poses the following interesting challenges:
 The entire process of developing a VLSI chip is a very involved process. In addition, a very huge
costly infrastructure is required to set up the fabrication houses or fabs.
 VSLI technology development is a highly inter-disciplinary area and people with expertise in fields,
such as solid state physics, material science, lithography, device modeling, hardware design,
algorithm development, Computer-Aided Design (CAD) tools, and quality assurance, need to work
together. As these people are specialists in their area, they are costly.
 As the size of the device shrinks, the design and testing activities become more and more complex.
Therefore, highly sophisticated development tools are required for carrying out these activities.

4
 Introduction to VLSI Design

Evolution of the Integration Levels

The number of equivalent two input NAND gates in a chip is taken as the measure to indicate the
complexity of the integration in the chip. The various integration levels are as follows:
 SSI—Maximum 10 gates per chip in 1960’s
 Medium Scale Integration (MSI)—Maximum 1000 gates per chip in 1970’s
 Large Scale Integration (LSI)—Maximum 10,000 gates per chip in 1980’s
 VLSI—Maximum 100,000 gates per chip in 1990’s
 Ultra Large Scale Integration (ULSI)—100 million gates per chip
The level of semiconductor process technology is measured in terms of the gate length, which is measured
in micrometers or nanometers (1 micrometer = 10 –6 meter and 1 nanometer = 10-9 meter). The reduction
in the gate length shows the progress in VLSI developments. International Technology Roadmap for
Semiconductors (ITRS) has defined the process levels, as shown in Table 1.1:
Table 1.1: Showing the ITRS Process Levels
Process Level/Gate Length Year Example

10 micrometer 1972 Intel 8008

3 micrometer 1975 Intel 8085

1.5 micrometer 1982 80286

1 micrometer 1985 80386

800 nanometer 1990 Intel 486

600 nanometer 1995 PowerPC

350 nanometer 1996 Pentium Pro

250 nanometer 1999 Pentium II

180 nanometer 2000 Pentium III

130 nanometer 2001 Intel Tualatin

90 nanometer 2003 P4 Prescott, Virtex 4 FPGA

65 nanometer 2007 Pentium IV

45 nanometer 2008 Pentium Dual Core

32 nanometer 2009 Pentium Core i7 Series

28 nanometer 2012 Qualcom dual core

22 nanometer

In the last two rows, the Year and Example columns are left blank because at this hour, the prediction is
difficult. The expectation of experts is that 16 nanometer technologies will be available by 2018.
With the improvements in process technology, you can easily see how the hardware design has changed.
You no longer need to use all the discrete components, as you can take readily available processors and
memory chips, and glue them together to develop powerful hardware for various applications.

5
Chapter 1

The next step in this evolution is to develop very few chips that will carry out the complete functionality
of the system, which is called SOC. However, putting the entire logic and memory in one chip requires
sophisticated design automation tools.

VLSI Design Process

The step-by-step procedure for developing VLSI chips is called the design process. A simplified design
process is shown in Figure 1.1:

Figure 1.1: Displaying the VLSI Design Flow

You may get a brilliant idea to put lot of functionality into a small chip, which may be a processor that can
do zillions of operations per second or process a video signal and automatically identify the objects in the
video. The idea may be used for a very specific application; and therefore, you want to develop an ASIC.
You need to convert that idea into detailed specifications. Based on these specifications, you need to
develop the logic, such as, how the specifications can be achieved using an electronic circuit. After the
logic is developed, you need to do the physical design of the chip, that is, the internal architecture of the
chip. This information, known as mask information, is then sent to a foundry where the actual chip is
manufactured.
Generally, logic design is referred to as front-end design and physical design is referred to as back-end
design. Both the back-end and front-end designs can be done using the sophisticated EDA tools. The
organizations, which develop the designs, are called fabless houses. On the other hand, fabs are set up
with huge investments for actual manufacturing of these chips. These fabs are the actual foundries. The
output of the foundry is the ASIC that implements your great idea. Sell those ASIC’s in millions and you
make great money.
However, if you want to develop an ASIC, it is going to be a very costly affair. It is not worth making an
ASIC unless you are sure that your Return On Investment (ROI) is good, as you are going to invest lots of
money. You need to compare the cost of making an ASIC with respect to what will be the sale price of
each chip and how many pieces you are going to sell. Based on this analysis, you need to decide whether it
is really worth going in for an ASIC.

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 Introduction to VLSI Design

In Figure 1.1, you can observe an interesting output from the fabless house, FPGA bit stream. Field
Programmable Gate Array (FPGA) is a very flexible chip. It can be configured through a bit stream so that
the same chip can be used for realizing different functionalities. If you think that the ROI, which you have
calculated on ASIC, is not very attractive, then you can choose the option of FPGA to implement your
idea.

VLSI Design Methodology

In the process of VLSI design, the first step is to get an idea. To convert this idea into a chip, you will think
in the behavioral domain, such as what the chip is supposed to do, instead of going into the details of how it
is to be implemented. After that, you will get into the structural domain in which you will think about the
various sub-systems, modules, and components that make up the system (or the chip). Then, you will get
into the physical domain, where you think about converting these modules into a physical chip by getting
into details, such as floor plan, mask layout, and packaging. In every domain, you follow a hierarchical
model. You divide a program into functions and write the code for each function; divide the system into
hardware modules; divide each module further into sub-modules; and then design each sub-module. To
carry out this entire method manually is an impossible task; however, for this, you need very sophisticated
tools and techniques. These tools and techniques need to address the following issues:
 How to describe or specify a system (or a circuit)? Note that the system is for doing a simple thing,
such as switching on/off a lamp or a large control system to control a spacecraft.
 How to convert the description/specification of a system into a realizable circuit that can be
embedded in a chip?
 How to ensure that things are going on fine at every step? If you assume that everything is going fine
and then finally, if your chip does not work, you will be in a great shock. Therefore, you need to test
at every stage, whether things are OK.

How to Specify a System?

In the early days of hardware development, experienced users used to specify the hardware by getting
into the implementation details directly. This is because the availability of the hardware limited the
engineer’s innovation. Any system can be designed using basic building blocks, such as gates and flip-
flops. If you want to design a logic circuit, you can write the Boolean equations from which you can design
the circuit using gates and flip-flops. Note that theoretically, any system can be represented by Boolean
equations. In basic electronics, you must have learned the procedure of minimizing the Boolean equations
so that you can minimize the number of gates and flip-flops used in the circuit. To design today’s complex
digital systems with millions of gates and flip-flops, writing Boolean equations is an impossible task and
this method is now almost obsolete.
The next step in the evolution of digital systems is the availability of ICs, which have gates and flip-flops
inside them, but for circuit designers, only a few pins are available. To achieve a desired functionality,
circuit designers need to select the desired ICs. A circuit designer has to create a circuit schematic that
gives a graphical representation of ICs, gates, and flip-flops. Even today, this schematic-based design is
used for hardware design, though each IC is more and more functionally rich. A schematic contains wires,
buses, and various components. This schematic can be converted into a breadboard PCB. Alternatively,
you can use a CAD tool that converts this schematic into a PCB design automatically.
As the complexity of digital systems grew further, Hardware Description Languages (HDLs) were
developed. Similar to the way functionality can be represented by a series of statements in a programming
language (C, C++, or Java), HDLs can provide the mechanism to describe a system using a series of
statements. Verilog and VHDL are the two most popular HDLs. To design chips, you need to be good in at
least one of these languages. However, gaining knowledge in both languages is better as both are equally

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Chapter 1

popular. You can describe a system using HDL and then compile the code to check whether it is correctly
written and then simulate the system and check how the system is likely to work.
Writing code in HDL is not a very easy task. However, you can use the following tools to describe a
system:
 Block diagram: is a diagram of a system, in which the principal parts or functions are represented by
blocks connected by lines, that show the relationships of the blocks. They are heavily used in the
engineering world in hardware design, electronic design, software design, and process flow
diagrams.
 Finite State Machine(FSM): is a mathematical abstraction sometimes used to design digital logic or
computer programs.
These tools will automatically convert the high-level representation into HDL code so that you need not
write the code yourself.

How to Convert Specifications into a Chip?

Specification describes the functionality, interface, and overall architecture. Based on the specifications,
behavioral description is created to analyze the design in terms of functionality and performance. These
behavioral descriptions are written in HDL, such as Verilog or Very High Speed Integrated Circuits
hardware description language (VHDL). To convert the specifications into a chip, you need to develop the
front-end and back-end designs. The steps to develop a front-end design are shown in Figure 1.2:

Figure 1.2: Displaying the Front-End Design

The specifications/design written in HDL or block diagram is checked for syntax and the simulation is
done on a desktop computer or work station. The next step is to verify the functionality of the design by
giving the necessary inputs and checking whether the correct output is obtained or not. This is called
functional verification. After this, synthesis is done, which is a process of translating the code into a circuit
(using gates and flip-flops) and optimizing the circuit to ensure that the minimum number of gates are
used and the timing constraints are met. As the wire lengths used inside the chip are a source of delays,
timing analysis has to be done on the entire internal circuit. However, at this stage, the exact wire lengths
are unknown; and therefore, only estimated wire lengths are considered for timing analysis. At a later
stage (after layout is finalized), taking into consideration the actual wire lengths, static timing analysis is
again performed.

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 Introduction to VLSI Design

Similarly, the steps to develop a back-end design are shown in Figure 1.3:

Figure 1.3: Displaying the Back-End Design

After the synthesis step, layout design is done and the placement and routing are carried out. Then, masks
are prepared and sent to the fabrication unit where the chips are fabricated, packaged, and shipped.

Electronic Design Automation

To achieve large-scale integration, the importance of tools cannot be overemphasized. The ultimate
objective of tools is to automate the entire VLSI design process. The tools that help in converting the
representation of the design in terms of HDL into a chip are called the EDA tools. As there is a good
demand for these tools, a very large number of tools are available in the market. Several companies, such
as Cadence Design system, Magma Design Automation, Synopsis, Mentor Graphics, and Xilinx, specialize
in EDA tools. Once the designer is satisfied that the design functions properly, he directs the computer to
synthesize a specially formatted file, a netlist, that describes a real circuit that behaves as the simulation.
The netlist is then used to direct physical implementation tools. The synthesized netlist is transformed to
an equivalent hardware implementation file for an ASIC or FPGA and is used as input to the tools that
build the final device The brief description of the design flows for ASIC and FPGA are discussed in detail
in the subsequent subsections.

ASIC
ASIC is an IC, which is designed in such a way that it meets the exact requirements for a specific
application. It is a fully customized device, the pre-laid out standard cells in ASIC libraries cover a large
range of functionality. If you are developing a product that will have a mass market, such as a mobile
phone, MP3 player, or set top box, then you can design an ASIC. The advantages of designing ASIC are as
follows:
 Very low production cost if the ASIC is for mass market
 Best utilization of the resources on the chip (as compared to FPGA)
 Optimized for a specific application; and therefore, power consumption and size will be less

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Chapter 1

ASIC Design Flow

Figure 1.4 shows the sequence of steps to design an ASIC:

Figure 1.4: Displaying the ASIC Development Process

The steps can be briefly described as follows:
 Algorithm—Behavioral description of the specifications.
 Design Entry—The design description is done in HDL (VHDL and Verilog) or schematic entry.
 Logic Synthesis—Using a HDL simulator and a logic synthesis tool to produce the gate-level netlist
(standard cell library).
 Logic verification—Verification of the functionality of the design.
 Mapping, Placing and Routing—Arrange the blocks; place the cells on the chip with connections.
 Physical layout—The final design is transformed and placed on the chip.
The tools used for the design of ASICs are described as follows with companies and the
simulators/synthesizer tools:
1. Cadence – Verilog-XL are simulators acts as front-end tools and CTgen (back-end tools)
2. Synopsis – VCS, VHDL simulators – functional and timing verification tool. And Design Compiler,
Test Complier are back-end design tools.
3. Altera – Quartus II A-HDL front-end simulator.
4. Magma Design Automation – back-end design tool

Field Programmable Gate Array (FPGA)

Field Programmable Gate Array (FPGA) is a two-dimensional array of logic blocks and flip-flops with
electrically programmable interconnections between logic blocks. Each logic block is capable of
implementing a combinational and sequential logic of different complexity. Logic block on an FPGA can
be as simple as a 2-input NAND gate or as complex as functional units, such as Arithmetic Logic Units
(ALUs) and memory units. The synthesis process includes mapping of the logic to the physical circuits on

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 Introduction to VLSI Design

the FPGA, such as Lookup tables (LUTs), memories, shift registers, and multipliers. These units are much
higher level than the gates in ASICs.

FPGA Design Flow

Figure 1.5 shows the sequence of steps to design an FPGA:

Figure 1.5: Displaying the FPGA Design Flow

The brief description of various steps is listed as follows:
 Algorithm—Behavioral description of a design is described in this step.
 HDL design entry—The design description is written using HDL, such as VHDL or Verilog.
 Logic synthesis—Logic simulation and optimization takes place in this step.
 Technology netlist—The Optimized/synthesized netlist is transformed into the Technology
dependent net-list (Lookup tables i.e.LUTs).
 Mapping, Placing, and Routing—Arrange the blocks; place the cells on the chip with connections.
 Bit stream—The synthesized, verified timing constraints netlist is converted into bit streams to
transform onto chip. The final streams are programmed onto target device.
The tools developed by major vendors for FPGA design flow are as follows:
1. Mentor Graphics:
 Model Sim, QuestaSim – functional simulation and debugging.
 Leonardo Spectrum – synthesis with FPGA-vendor place-and-route tools
 Leonardo Insight - performance analysis and debugging.
2. Cadence:
 NC Verilog, NCSim – functional simulation tool.
3. Aldec:
 Active-HDL – integrated design entry and functional simulation environment tool.

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Chapter 1

4. Synplicity:
 Synplify – synthesizes for code design description in VHDL and Verilog.
 Amplify - performs physical synthesis, one of the first tools to do this for FPGA’s.
5. Synopsis:
 Virtuso – platform for simulation environment
 Scirocco VHDL and VCS Verilog simulators
6. Xilinx
 ISE – Simulation and logic synthesis tool.
7. Altera-Quartus – A-HDL (front-end design tool) and MaXPlus back-end tool.

Example
The behavioral description is given in Verilog to perform the addition of two 4-bit binary numbers. For
example, the behavior of an adder that adds two 4-digit inputs and returns an output is specified as
module adder(ip1, ip2, op)
input [3:0] ip1, ip2; //input signals
output [3:0] op; //output signals
op <= ip1 + ip2;
end module
The behavioral description does not specify the structure of the design (whether combinatorial or
sequential elements) used. This description also does not capture the timing information.
In the Register Transfer Level RTL description, the design is split into registers with flow of information
between each register at each clock cycle.
module adder(ip1, ip2, op)
input [3:0] ip1, ip2;
input cin;
output [4:0] op;
assign op = ip1 + ip2 + cin;
end module
Design is divided into registers and logic blocks that join the registers together, as shown in Fig. 1.4.3. The
detailed design flow is shown in Fig 1.4.4 for 4-bit full adder (FA). The design consists of four 1-bit full
adder and the flow of inputs and outputs of each logic block. Each 1-bit full adder has three inputs –
ip1[0], ip2[0] and input carry (cin).

Design entry: The design description is done using Hardware Description Language or schematic entry.
Simulation is checked using front-end tools. The optimization of the design takes place at logic synthesis
and gate-level netlist(Gate-level netlist is basically a circuit implementation of the design made of library
components available in the technology library and their interconnections. The netlist is generated by the
synthesis tool according to the constraints set by the designer) is generated, verified and placed and
routing is done by back-end tools. Finally the physical layout of the circuit is mapped on to target device.
The flow of data between the logic blocks are shown in Figure 1.6 and the structural description of 1-bit
full adder is shown in Figure 1.7.

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 Introduction to VLSI Design

Figure 1.6: The structure of flow of Data in 4-bit Full adder

Figure 1.7: Structural description of 1-bit full adder

System on Chip Designs

System on Chip(SoC) technology will put the maximum amount of technology into the smallest possible
space. A SoC is an IC designed by stitching together multiple stand-alone VLSI designs to provide full
functionality for an application. An SoC comprises of predesigned models of complex functions known as
cores (terms such as intellectual property block, virtual components, and macros) that serve a variety of
applications. SoC is an integrated device consists of hardware (processor/microcontroller) components,
software that controls the hardware and peripherals.
Three forms of SoC designs are
1. ASIC vendor design—This refers to the design in which all the components in the chip are designed
as well as fabricated by an ASIC vendor.
2. Integrated design—This refers to the design by an ASIC vendor in which all components are
obtained from some other sources.
3. Desktop design—This refers to the design by a fabless company that uses cores obtained from other
source such as IP companies, EDA companies, design services companies.
Typical applications of SoC:
 Consumer devices ( Wireless phones, DVD players, digital camera, digital television )
 Networking and Communication (graphics and routers).
Advantages of SoCs:
 Consumes less power and have a lower cost.
 Higher reliability than the multi-chip systems.
 Fewer packages in the system, assembly costs are reduced as well.

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Chapter 1

Summary
This chapter presented a brief introduction about VLSI Design. The traditional approaches in the
hardware design – vacuum tubes, transistors, diodes, semiconductors, and Integrated Circuit chips. The
invention of transistor laid down the foundation of semiconductor technology. The fast pace development
of semiconductor technology increased the capability of achieving the functionality of complex logic and
memory usage. With the level of increase in integration of circuits, the processor developments achieved
with complex functionality like memories, ALUs, DSP etc., The two important phases in VLSI Design
process: front end process and Back end process. The front end design is the first phase in the VLSI design
process where the logic for the chip is built using the HDL. Verilog HDL has become popular due to its c-
like syntax. The second major phases is known as Backend process where the logic synthesis is been
performed, cells in the netlist are placed on the die and then routed with final layout. The automated tools
for front end and backend are termed as Electronic Design Automation tools.
Application Specific Integrated Circuit (ASIC) is an Integrated Circuit that is designed to meet the exact
requirements for a specific application. ASIC is a fully customized device, the pre-laid out standard cells in
ASIC libraries cover a large range of functionality. Field Programmable Logic Array is a programmable
device consists of programmable logic blocks (LUTs). ASIC Design and FPGA design flow differs at the
synthesis stage of the design process. The major vendors of Front end tools and backend tools are
Synopsis, Mentor Graphics, Cadence, Magma Design Automation, Synplicity, Altera and Xilinx. The tools
like VCS, Verilog, NCSim, Verilog-XL, A_HDL, ModelSim and Nc verilog are some of the logic simulators
(front end tools). The Altera – MAXplus, Magma, Design Compiler, Emulator, Leonardo Spectrum and
Xilinx are the Backend tools.

Review Questions
1. Explain the developments in VLSI technology.
2. Explain the front end and back end process in a VLSI design process.
3. Explain the features of ASICs devices.
4. What are the applications of FPGAs?
5. List and write the major vendors of front end tools.
6. List and write the major vendors of back end tools for FPGAs and ASICs.

14
 2
VLSI Design Technologies
If you need information on: See page:
Combinatorial Design Technique 16
Sequential Design Technique 26
State Machine Logic Design Technique 31
Design Issues 34
Chapter 2

Combinatorial Design Technique

Digital world is based on the binary number system. The binary number represents the numerical value 0
and 1. Therefore, while dealing with the digital logic, these values are specified as:
 0 = false (no)
 1 = true (yes)
The logic systems that are represented based on the binary number system are called two-valued (binary)
logic system. Using this two-valued logic system, every statement or condition must be evaluated as either
true or false; however, the value cannot be partly true and partly false. The binary logic plays a vital role
in the digital world for basing logical operations on the binary number system.
Binary logic is used to design simple, stable electronic circuits, which can switch back and forth between
two clearly-defined states, with no ambiguity attached. It can also be used to build circuits, which will
remain indefinitely in one state. This makes it possible to construct a machine or computer that can hold
sequence of events and changes its behaviour according to the logical operations. These logical operations
are realized using logic gates.
A digital logic circuit can be represented in different ways, such as truth table, Boolean equation, and
schematic.
A logic gate is an electronic circuit or a device that makes the logical decisions. Logic gates have one or
more inputs and only one output. The output is active based on the input values applied to the gate. Logic
gates are also called switches. The most common logic gates are OR, AND, NOT, NAND, and NOR gates.
The AND, OR, and NOT gates are called primitive or basic gates. The logic function of the basic gates are
given as follows:
 AND Gate—The output Z is true if input X AND input Y are both true: Z = X AND Y. An AND gate
can have two or more inputs, and its output is true if all the input values are true. The truth table
shows the output values for each possible combination of two input variables.
 OR Gate—The output Z is true if input X OR input Y is true (or both of them are true): Z = X OR Y.
An OR gate can have two or more inputs, and its output is true if at least one input is true.
 NOT Gate—The output Z is true when the input X is NOT true, that is, the output is the inverse of
the input: Z = NOT X. A NOT gate can only have one input, and it is also called inverter.
The traditional symbol and truth table for all these logic gates are shown in Figure 2.1:

Traditional symbol of the two-input AND gate

Truth Table

Traditional symbol of the two-input OR gate

Truth Table

Traditional symbol of the NOT gate

Truth Table
Figure 2.1: Displaying the Traditional Symbols and Logic Gates

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 VLSI Design Technologies

The Exclusive-OR (XOR) gate and the Exclusive-NOR (XNOR) gate are other logic gates that can be
constructed using the AND, OR, and NOT gates or the NAND or NOR gates. The NAND and NOR gates
are called universal gates because any logic gate, such as AND, OR, NOT, Exclusive-OR, Exclusive-NOR,
NAND, and NOR, can be realized using only the NAND gates or the NOR gates. Similarly, any logic
circuit can be realized using any of these universal gates.
A set consists of logic gates is said to be a functionally complete set if any logical operation can be realized
with these set elements. For example, the set {NAND} is called a functionally complete set because any
logic circuit can be realized using the NAND gate. In this case, the NAND gate is a set element.
Similarly, {NOR}, {AND, NOT}, {OR, NOT}, and {AND, OR, NOT} are functionally complete sets.
Figure 2.2 shows the AND, OR, and NOT gates that are realized from the NAND and NOR gates:

Figure 2.2: Displaying the NAND and NOR Realization of Basic Gates

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Chapter 2

As mentioned earlier, the digital circuits are constructed with a set of logic circuits. Logic circuits perform
an operation that can be specified logically by a set of Boolean functions. The two types of digital circuits
are as follows:
i. Combinational
ii. Sequential
Logic circuits whose output depends on the current logic states of the inputs are called combinational
logic circuits.
A combinational circuit consists of logic gates, where output values are determined only by the present
combination of inputs. In other words, a combinational circuit performs an operation specific to
information processing assigned logically by a set of Boolean functions. These circuits consist of input
variables, output variables, logic gates, and interconnections. Each input and output variable exist
physically as a binary signal that represents a logic 1or logic 0.
Combinational circuits can have one or more inputs. Figure 2.3 shows the block diagram of a
combinational circuit with m-inputs and n-outputs where m and n are variables:

Figure 2.3: Displaying the Block Diagram of a Combinational Circuit

The interconnected logic gates accept signals from the inputs and generate signals at the output. The total
number of input combinations is the permutations of the number of inputs, that is, 2n combinations for n-
inputs.
Logic gates are the building blocks of any digital circuit. A circuit can have m-inputs and n-outputs and can
be realized or implemented using several logic gates.
For n input variables, 2n binary input combinations are possible. For each binary combination of the input
variables, one binary value (0 or 1) on each output is possible. Therefore, a combinational circuit can be
specified by a truth table that lists the output values for each combination of the input variables. Similarly,
Boolean function represents the functionality of any combinational circuit. With two-input variables, the
numbers of distinct Boolean functions that can be realized are four; whereas, with three-input variables,
eight distinct combinational circuits can be realized.
Similarly, the total number of distinct Boolean functions with n-input variables are 2m, where m = 2n and
each function is expressed as a function with n-input variables.
Logic functions can also be expressed using truth table and schematic. Let’s now learn about the Boolean
equation and schematic in the next sections.

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 VLSI Design Technologies

Boolean Equation
If the value of the output variable is represented as a function of the input variables, then that function is
called Boolean expression or Boolean equation.
For example, the Boolean equation for a two-input AND gate is
F(x, y) = xy
In this Boolean equation, x and y are the input variables that can be assigned any possible combinations of
the input values, such as 00, 01, 10, and11.
Similarly, Boolean function for a two-input XOR gate is
F(a,b) = a’b + ab’
In the preceding Boolean function, a and b are the input variables and a’, a, b’, and b are literals. A literal is
a variable in a complement or normal form. The output of the Boolean function is true when a = 0 and b =
1 and a = 1 and b = 0. Table 2.1 shows the truth table for the Boolean function:
Table 2.1: Truth Table for the Boolean Function
A B Output

0 0 0

0 1 1

1 0 1

1 1 0

Schematic
The schematic, which is also known as logic diagram, shows the connection of hardware logic gates that
implement the circuit.
The schematic for the Boolean function F(x, y) = x’y + x y’, where x and y are inputs to the XOR gate is as
shown in Figure 2.4:

Figure 2.4: Displaying the Schematic for the Boolean Function F(x, y) = x’y + x y’
Similarly, let’s consider the three-variable Boolean functions F1and F2 such that F1(x,y,z)=x'yz+xy'z+xyz
and F2(x,y,z)=xy+yz+xy.
Figure 2.5 shows the schematic of the Boolean function:

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Chapter 2

Figure 2.5: Displaying the Schematic Diagram for the Boolean Function
Figure 2.6 shows the schematic diagram of Boolean function F1(x,y,z)=x'yz+xy'z+xyz:

Figure 2.6: Displaying the Schematic Diagram for the Boolean Function F1
Figure 2.7 shows the schematic diagram of F2(x,y,z)=xy+xz+yz:

Figure 2.7: Displaying the Schematic Diagram for the Boolean Function F2
Any logic function or Boolean function expressed as a combination of input variables is also called
Switching algebra or Boolean algebra. These functions can be expressed in three forms: canonical,
standard, and factored. Let’s now learn about these forms in detail.

Canonical Form
A binary variable can hold a value 0 or 1, and it is represented as a complement form (x') or a normal form
(x). For n-variables, the binary numbers from 0 to 2n -1 are considered.
A Boolean expression is said be in a canonical form if all the terms are minterms. Each minterm is obtained
from an AND term of n-variables, with each variable in a complement or normal form. In other words,

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 VLSI Design Technologies

binary variables forming AND-terms where each variable in the term is primed if the corresponding bit of
variable is 0 and unprimed if it is 1 are called minterms.
The number of minterms for n-variables is 2n.
The list of all possible combinations with two-variables (0 - 22 -1=0-3) and corresponding minterms are
listed as follows:
00 --- x' y'
01 --- x' y
10 --- x y'
11 --- x y
For example, Boolean function
F(x,y) = x' y' + x' y is expressed in a canonical form where x’y’ and x’y are its minterms.
Similarly, n-variables forming OR terms with each variable to provide 2n possible combinations are called
maxterms. The maxterms for the two-variables x and y are x+y, x+y', x’+y, and x’+y'.
In other words, any n-variable term formed with an OR-operation where each variable in the term is
primed if the corresponding bit of variable holds 1 and unprimed if it is 0, then the term is called maxterm.
Table 2.2 lists the minterms and maxterms for three-binary variables:
Table 2.2: Minterms and Maxterms of Three–Binary Variables
XYZ MINTERMS MAXTERMS

000 X' Y 'Z' X+Y+Z

001 X' Y' Z X+Y+Z'

010 X' Y Z' X+Y'+Z

011 X' Y Z X+Y'+Z'

100 X Y'Z' X'+Y+Z

101 X Y' Z X'+Y+Z'

110 X Y Z' X'+Y'+Z

111 XYZ X'+Y'+Z'

A Boolean function can be expressed algebraically as a Sum of Minterms (SOM) or Product of Maxterms
(POM). If a Boolean function is expressed as SOM or POM, then the function is said to be in a canonical
form. However, the Boolean function is in a standard form if it is expressed in Sum of Products (SOP) or
Product of Sums (POS) form. Let’s learn about these forms in the next section.

Standard Form
Standard form is another way to represent a Boolean function. The standard forms are of two types: SOP
and POS.
The n-variable term obtained by AND-operation of all the variables or some of the variables is said to be in
the SOP form.
SOP is a Boolean expression containing AND terms called products with one or more literals. Each sum
denotes the ORing of the AND terms. An example of SOP is as follows:
F=xy+yz+z

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Chapter 2

Similarly, the n-variable term expressed by ORing all the variables or some of the variables is said to be in
the POS form.POS is a Boolean expression containing OR terms called sums with one or more literals.
Each product of these sums is called POS expression.
An example of POS is as follows:
F(x,y,z) = (x+y+z) (y+z) (x+y)
Any Boolean functions can be expressed in terms of AND, OR, and NOT operations. These functions are
easy to implement using basic gates (AND, OR, and NOT), universal gates (NAND and NOR), or with
functionally complete set of gates.
The implementation of the Boolean function F = ABD + CD + E in the SOP form with logic gates is shown
in Figure 2.8:

Figure 2.8: Displaying the Schematic for F(A,B,C,D,E) = ABD+ CD+E

Factored Form
Boolean functions can also be expressed in the factored form. The logic function is in the factored form, if
it is neither in the SOP form nor in the POS form. The factored form of an expression is composed of
products of factors. This form is used mainly to simplify the logic circuits with minimum logic gates.
Example of a factored form is given as follows:
F = (a+b)cd + (c+d)b

Don’t Care Combinations

Boolean function can also be expressed in a non-standard form. A don’t care minterm is a combination of
variables whose logical value is not specified, that is, neither 0 nor 1. The minterm is represented as
unknown value X in the truth table. Don’t care minterms are used for the simplification of the Boolean
expression due to their unspecified value. The value of these minterms is don’t care and the terms are used
to simplify the Boolean expressions.
Similarly, a don’t care maxterm is a combination of variables whose logical value is not specified and is
represented as X in the truth table. Unspecified minterms or maxterms of a function are called don’t care
conditions.

Completely Specified Combinational Functions

The functions, whose expression is represented in SOP or POS that are specified to a known value (i.e., 0
or 1) for all the maxterms or minterms, are called completely specified functions.

Incompletely Specified Combinational Functions

The functions, whose expression is in SOP or POS form where all the minterms/maxterms/product
terms/sum terms are not defined to a specified value, are called incompletely specified functions.

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 VLSI Design Technologies

Design of a Completely Specified Combinational Circuit

The design of a combinational circuit starts from a specification of the problem and realizes into a logic
diagram or a set of Boolean equations from which the logic diagram can be realized. In other words, the
design of combinational circuits starts from the design objective specification and determines the logical
expression based on the specification and/or a set of Boolean functions followed by a logic circuit
implementation.
The procedure to design combinational circuit varies for completely specified functions and incompletely
specified functions.
Following is the procedure to design a combinational circuit that is completely specified:
1. Obtain the specifications of a circuit.
2. Determine the required numbers of inputs and outputs and assign symbols to each input and output.
3. a. Determine the number of input variables for n-variables, form the 2n possible input
combinations, and list the binary numbers from 0 to 2n-1 in a truth table.
b. Derive the truth table that defines the relationship between inputs and outputs.
4. Obtain the simplified Boolean functions for each output as a function of input variables.
5. Draw the logic diagram and verify the correctness of the design for each input combination with
corresponding output manually or by simulation.
The output binary functions are simplified by using any available method, such as algebraic manipulation,
Boolean theorems, or karnaugh-map (k-map). These Boolean functions can be realized or implemented
using basic logic gates or universal gates.
Let’s design a four-input combinational circuit whose output is equal to 1 if input variables have more 1’s
than 0’s; otherwise, it is 0. The steps to design the circuit are given as follows:
Step-1: As per the specification, output of the circuit will be 1 if the number of 1’s are greater than the
number of 0’s in the input values.
Step-2: The binary variables w, x, y, and z are inputs and f is an output.
Step-3:
a. Derive the truth table, which consists of four columns for input and one column for output. The
4-variable input represents the binary values from 0-15 for four variables.
b. The output column is determined from the stated specification.
Step-4: Boolean functions are transformed into a circuit diagram composed of logic gates connected in a
particular structure. Output function is expressed as a simplified expression in any of the standard form in
terms of input variables.
Step-5: The logic expression or Boolean function is implemented using logic gates.
Table 2.3 shows the truth table for the preceding example:
Table 2.3: Truth Table for the Combinational Circuit

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

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Chapter 2

Table 2.3: Truth Table for the Combinational Circuit

0 0 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

The truth table for output F is determined from the values of w, x, y, and z. The value of F is 1 for any
combination that has three or more inputs equal to 1. Designer’s motive is to design a circuit by using
minimum number of gates to reduce the cost of the circuit. Therefore, by applying Huntington postulates,
Boolean theorems, and algebraic theorems, the Boolean expression is simplified, as shown in Figure 2.9:

Figure 2.9: Displaying the Combinational Circuit Realized with the Basic Gates
Procedure to design a combinational circuit that is incompletely specified for some combinations is given
as follows:
1. Obtain the specifications of the circuit Determine the required number of inputs and outputs and
assign symbols to each input and output.

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 VLSI Design Technologies

2. a. List all the possible input combinations and their corresponding binary numbers from 0 to 2n-1 in
order as a truth table.
b. Derive the truth table that defines the relationship between inputs, outputs, and unspecified
combinations.
c. Represent the unspecified combinations in the truth table as X and specified combinations as 1
and 0 as per the functionality.
4. a. If the function is in the SOP form, then consider the unspecified combination value as 1 and
obtain the simplified Boolean expression for each output as a function of input variables.
b. If the function to be simplified is in the POS form, then consider the unspecified combination
value as 0 and obtain the simplified Boolean expression for each output as a function of input
variables.
5. Draw the logic diagram and verify the correctness of the design for each input combination with the
corresponding output manually or by simulation.
The output binary functions are simplified by using any available method, such as algebraic manipulation,
Boolean theorems, or k-map method. These Boolean functions are implemented using basic logic gates or
universal gates.
Let’s design a four-input combinational circuit
1. Whose output is equal to 1, if input variables have more number of 1’s than 0’s
2. Whose output is unspecified, if input variables have equal 1’s and 0’s
3. Otherwise, the output value is 0
Step-1:
a. Based on the specifications, output of the circuit is equal to 1 if the number of 1’s are greater than
the number of 0’s.
b. The output of the circuit is equal to 0 if the number of 0’s are greater than the number of 1’s.
c. Otherwise, the output of the circuit is don’t care and represent it as X in the truth table.
Step-2: The binary variables w, x, y, and z are inputs and f is an output.
Step-3:
a. Derive the truth table, which consists of four columns for input and one column for output. The
four-variable input represents the binary values from 0-15.
b. The output column is determined from the stated specifications.
Step-4: Boolean function is transformed into a circuit diagram that is composed of logic gates connected in
a particular structure. Output function is expressed as a simplified expression in any of the standard form
in terms of input variables.
Step-5: The logic expression or Boolean function is implemented using the logic gates. The simplified
Boolean function for given specifications is derived as
F(w,x,y,z) = wx + wy +xy.
Table 2.4 shows the truth table for the function F(w,x,y,z) = wx + wy +xy:
Table 2.4: Truth Table with Don’t Care Combinations

W X Y Z F

0 0 0 0 0

0 0 0 1 0

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Chapter 2

Table 2.4: Truth Table with Don’t Care Combinations

0 0 1 0 0

0 0 1 1 x

0 1 0 0 0

0 1 0 1 x

0 1 1 0 x

0 1 1 1 1

1 0 0 0 0

1 0 0 1 x

1 0 1 0 x

1 0 1 1 1

1 1 0 0 x

1 1 0 1 1

1 1 1 0 1

Sequential Design Technique

The digital circuits considered so far have been termed as combinational circuits. A combinational circuit
and storage elements are interconnected to form a sequential circuit.
The storage elements are circuits that are capable of storing binary information. The binary information
stored in these elements at any given time defines the state of the sequential circuit at that point in time.
The sequential circuit receives binary information from its environment through inputs. These inputs
together with the present state of the storage elements, determine the binary value of the outputs. They
also determine the value used to specify the next state of the storage elements. The next state of the storage
elements is also a function of the inputs and present state. Therefore, a sequential circuit is specified by a
time sequence of inputs, internal states, and outputs.
In other words, logic circuits whose outputs depend on the sequence of the input signals are called
sequential circuits. Such circuits remember the past states of their inputs and produce the output based on
the past states as well as the current states of the input signals. The block diagram of a sequential circuit is
as shown in Figure 2.10:

Figure 2.10: Displaying the Block Diagram of a Sequential Circuit

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 VLSI Design Technologies

Following are the two types of sequential circuits based on the timing of the signals:
 Synchronous
 Asynchronous
Synchronous sequential circuit is a logic circuit whose outputs depend on the present values of inputs
and the past values of inputs at discrete interval of time. Synchronous is achieved by timing device called
clock generator, which provides a clock signal for every fixed periodic intervals as 0 – 1 – 0 and denoted as
clock pulse or clk. The pictorial form to represent the clock pulse or clock signal is as shown in Figure 2.11:

Figure 2.11: Displaying the Clock Pulse

Storage elements commonly used in sequential circuits are flip-flops, time delay devices, or latches. These
elements consist of logic gates whose propagation delay provides the required storage. If the storage
elements are synchronized using clock-generator device, then these elements are called flip-flops. The
storage elements that are not synchronized through clock pulse are called latches or time delay devices.
The sequential circuits whose storage elements are flip-flops are termed as synchronous sequential
circuits.
Asynchronous sequential circuits are designed with latches or time delay devices as storage-elements.
Let’s now learn about the synchronous and asynchronous sequential circuits in detail.

Synchronous Sequential Circuits

A synchronous sequential circuit is made up of flip-flops and combinational gates. The designing of a
circuit consists of choosing the flip-flops and finding a combinational circuit structure, which together
with the flip-flops, produces the circuit that fulfills the stated specifications.
The behavior of a synchronous sequential circuit is determined from the inputs, the outputs, and the state
of the flip-flops. The outputs and the next state are the Boolean functions of inputs and the present state.
Figure 2.12 shows a synchronous sequential circuit with flip-flop as a memory element:

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Chapter 2

Figure 2.12: Displaying the Synchronous Sequential Circuit

The number of flip-flops is determined from the number of states in the circuit; n flip-flops can represent
up to 2n binary states. The combinational circuit is derived from the state table by evaluating the flip-flop
input equations and output equations.
The design process involves a transformation from a sequential circuit problem into a combinational
circuit problem such that the techniques of designing a combinational circuit can be applied to design the
sequential circuit.
The various types of flip-flops vary based on the number of inputs. Let’s now learn about flip-flops in
detail.

Flip-Flop
Flip-flop is a circuit constructed from NAND or NOR gates with feedback loop. The circuit has inputs and
outputs. Each flip-flop has two outputs termed as q and q’.
The state of the flip-flop determines the output of the flip-flop and changes only during a clock pulse
transition, that is, when the values of the clock pulse changes from 0 to 1. When clock pulse is not active,
value stored at flip-flop is the output of the flip-flop. The output of flip-flop changes if input change takes
place and clock pulse is active. Therefore, the transition from one state to the next state occurs only at
discrete interval of time. The output value of flip-flop before applying clock pulse is called past input
values and state of the flip-flop is called the present state. Flip-flop is an edge-sensitive device.
The various types of flip-flops are Set – Reset (SR), JK, D, and T. The inputs required for the SR and JK flip-
flops are two.
The state of the flip-flop after applying clock pulse is called the next state of flip-flop and the output values
of the flip-flop are represented as the present input values. The states of sequential circuits are represented
using state equation, state table, and state transition graph. Let’s learn about these in detail.

State Equation
The behavior of a circuit is described algebraically by the means of input variables. The number of state
equations depends on the number of memory elements or the number of flip-flops of the circuit. The
function of state equation specifies the present state and inputs of the circuit. The output of the circuit as
the next state is given as follows:
A(t+1) = A(t)x(t) + B(t)x(t)
The left side of the equation is the output of the flip-flop denoted as next state of the flip-flop after
applying clock pulse. The right side of the equation represents the present state and input conditions that
makes the flip-flop circuit equal to 1. The state equation is also termed as transition function.

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 VLSI Design Technologies

State Table
The state table, also called transition table, consists of input, present state, next state, and output columns.
The derivation of state table requires listing of all the possible binary combinations. The possible
combinations vary with respect to the number of flip-flops and the number of inputs to the circuit. In
general, a sequential circuit with m flip-flops and n inputs needs 2 m+n combinations.
The binary numbers from 0 to 2 m+n -1 rows to be represented in the state table as present state and inputs.
If the present state at t and next state at (t+1) is represented as state equations with input variables, then
the present state represents the state of flip-flop before applying clock pulse, that is, at time t. Similarly, the
next state represents the output of flip-flop after applying clock pulse, that is, at time (t+1).
Following is the state table with one flip-flop and one variable that requires 2 1+1 combinations with one
output variable:
Input Variable Present State Next State Output
X A(t) A(t+1) z
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

State Diagram
The information in the state table can be presented graphically in the form of a state diagram (or transition
diagram). A state is represented by a circle. A transition from the present state to the next state is
represented by an arrow with the inputs and outputs written on that transition with a slash in between
inputs and outputs. Transition from one state to another state is represented as vertices, as shown in
Figure 2.13:

Figure 2.13: Displaying the State Diagram

As shown in Figure 2.13, states are represented as circles S0, S1, S2, and S3.
The design procedure for synchronous sequential circuits starts from the statement of the problem and
culminates into a logic diagram.
Perform the following steps to design the synchronous sequential circuit:
1. Obtain either the state diagram or the state table from the statement of the problem.
2. Obtain the state table, if only a state diagram is available from step 1.
3. Assign binary codes to the states.

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Chapter 2

4. Derive the input equations of flip-flop from the next state entries in the encoded state table.
5. Derive the output equations from the output entries in the state table.
6. Simplify the input equations and output equation of flip-flop.
7. Draw the logic diagram with D flip-flops and combinational gates, as specified by the input equations
and output equation of flip-flop.
Let’s design a synchronous sequential circuit that displays the sequence as 0 0, 0 1, 1 1, 1 0 and repeats
itself. The sequence resets to 0 0 when an input variable is equal to 1.
The procedure to design this synchronous sequential circuit is as follows:
1. Identify the number of states, state variables, and input variables from the statement of the problem.
The number of states identified is four and named as S0, S1, S2, and S3.
2. Assign binary codes to the states and number of variable as A, B to represent the binary coding of
states and input variable as x.
3. The state table is given as follows:
Present State Input x Next State
AB

S0 – 0 0 0 01

S1 – 0 1 0 11

S2 – 1 1 0 10

S3 – 1 0 1 00

The transition state diagram is given in Figure 2.14:

Figure 2.14: Displaying the Transition State Diagram with Four States
4. Derive the input equations from the next-state entries in the encoded state table.
5. Derive the output equations from the output entries in the state table.
6. Simplify the flip-flops input equations and output equation.
If the flip-flop chosen is of D- type, then the equations for the two input variables DA and DB in terms of
present state variables are as follows:
DA = B(t)
DB = A’(t)
where, A(t) and B(t) are present state variables and A(t+1) and B(t+1) are next state variables.

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 VLSI Design Technologies

Asynchronous Sequential Circuits

The asynchronous sequential circuits change the state of the circuit when there is a change in input
variables. The feedback path is maintained using delay devices or latches. Time delay device is a circuit
able to store the binary information for a duration of time unit. Latch is an electronic circuit that stores the
binary information that operates at signal level rather than at signal transition level. Therefore, latches are
called level-sensitive devices.
Asynchronous sequential circuits do not use clock pulse. The memory element in asynchronous sequential
circuits used for feedback is a time delay device, as shown in Figure 2.15:

Figure 2.15: Displaying the Asynchronous Sequential Circuit

Figure 2.14 (a) Transition state table with Present and Next State and input variables

State Machine Logic Design Technique

Finite state machines are built from sequential logic circuits. As an example, let’s suppose that you have to
design a circuit that receives a stream of bits as input at every clock cycle with an external input. The
output of the circuit indicates 1 when the last three input bits received are 1; otherwise, the output of the
circuit indicates 0. The procedure to represent the state transition and the state table is similar to the
procedure for sequential circuits based on the specifications.
Two types of finite-state machine can be built from sequential logic circuits:
 Moore machine—The output depends only on the internal state. If the internal state of a machine
changes on a clock edge, then the output also changes on a clock edge.
 Mealy machine—The output depends not only on the internal state, but also on the inputs.
Finite state machine is a six-tuple function < I, S, δ, O, λ, S0>, where
 I – Input alphabet
 S – Set of states, that is, s0, s1, s2…..
S0 - S0 is a start state (or) an initial state
δ –Next state function in terms of states and input alphabet,
= S x I (Cross product of set of states and input alphabet)
O- Output alphabet
λ- Output function
As mentioned earlier, finite state machines are considered as Mealy or Moore machine based on the
output function.

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Chapter 2

For Mealy machines,

λ= S x I  O.
Figure 2.16 shows the Mealy machine:

Figure 2.16: Displaying the Mealy-Type Finite State Machine

The input alphabets and corresponding functions of the Mealy type machine given in Figure 2.16 is as
follows:
I = {0 ,1} – Input alphabets
S = { s1, s2, s3} – set of states
S0 = {s1} – initial state
δ (s1, 0) = s2 - Transition function ( next state transition)
δ (s1, 1) = s3
δ (s2, 0) = s3
δ (s2, 1) = s2
δ (s3, 0) = s2
δ (s3, 1) = s1
λ(s1,0) = 0 – Output function
λ(s1,1) = 1
λ(s2,0) = 1
λ(s2,1) = 0
λ(s3,0) = 0
λ(s3,1) = 0
Similarly, for Moore machine,
λ = S  O.
An example of Moore machine is as follows:
I = {0,1}
S = {s1,s2,s3}
O ={s1,s2,s3}
λ(s1) ={s2}
λ(s2) ={s3,s1}
λ(s3) ={s1,s2}
δ (s1, 0) = s2 - Transition function ( next state transition)
δ (s1, 1) = s2

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 VLSI Design Technologies

δ (s2, 0) = s3
δ (s2, 1) = s1
δ (s3, 0) = s1
δ (s3, 1) = s2
The transition graph/state diagram for a given Moore-type finite state machine is as shown in Figure 2.17:

Figure 2.17: Displaying the Moore-Type Finite State Machine

If a state-transition function is defined for all the input alphabets, then those finite state machines are
termed as completely specified finite state machine; otherwise, those machines are termed as incompletely
specified finite state machine.
Figure 2.18 shows the completely specified finite state machine:

Figure 2.18: Displaying the Completely Specified Finite State Machine

In Figure 2.18, state transition function is defined for all the input variable values (0,1) and for all the
states.
Figure 2.19 shows the incompletely specified finite state machine:

Figure 2.19: Displaying the Incompletely Specified Finite State Machine

In Figure 2.19, the state transition function is defined only for some states and for some input alphabets.

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Chapter 2

Design Issues
The reliability of digital circuit is the most important design issue for a designer. The characteristics of
digital circuits are measured based on the power consumption, propagation delay, power dissipation,
hazards, glitches, and noise margin. Out of all these, the parameter that affect the circuit lifetime is power
dissipation. Similarly, other important factors that affect the circuit are meta-stability apart from noise
margins and delay incurred in the circuit. In this section, parameters, such as fan-out, meta-stability, noise
margin, power dissipation, and timing are discussed briefly.

Fan-Out
Fan-out of a gate is the maximum number of inputs the gate can derive while maintaining the output
levels within the specified limits. In other words, fan-out specifies the maximum loading that a given gate
is capable of handling to derive the output line.
Figure 2.20 shows the AND gate that derives three inputs to next-level gates:
Figure 2.21 represents the AND gate with fan-out 4:

Figure 2.20: Displaying the AND Gate with Fan-Out 3

Figure 2.21: Displaying the AND Gate Output with Fan-Out 4

A circuit in which no signal has fan-out is said to be a fan-out free circuit.
Source node is called fan-out stem and the number of nodes that derives out inputs to next-level gates are
called fan-out branches.

Meta-Stability
Meta-stable means not stable. If a signal is meta-stable, then the value of that signal is neither 0 nor 1. The
value oscillates between 1 to 0 or 0 to 1. In combinational circuits, hazards arise due to momentary delay
between the input leading to the incorrect output of the circuit. Similarly, meta-stable occurs when a clock
edge is random with respect to a change of an input signal in flip-flops. The momentary incorrect output
leads to unreliable conditions to the digital circuits.
In other words, if a signal changes within the setup/hold time of the flip-flop, the output is unknown for a
period. If this time lag is known and finite, then it is not a factor to be considered to measure the
performance of the circuit. However, this period is known prior to the design stage. This depends on the
characteristics of the flip-flop. One of the best solutions to solve this problem is to use synchronous design
techniques.

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 VLSI Design Technologies

Noise Margins
The unwanted signals arise during the interconnection of logic gates of digital circuit. These signals are
termed as noise. Two types of noises can be considered: AC and DC.
The AC noise is a random pulse that may be created by other switching signals. The DC noise is caused
due to sudden fall in voltage levels of signal. Therefore, noise is an unwanted signal that needs to be
avoided. Otherwise, the tolerance level for the circuit needs to be identified such that it does not affect the
circuit output.
Noise margin is expressed in volts and represents the maximum noise signal that can be tolerated by the
gate. Any logic gate is immune to AC noise margins due to the short duration. These AC noise margins
are higher than the DC noise margins. Some important facts of DC noise margin are as follows:
1. The DC noise margin of a logic-gate is a measure of its noise immunity
2. Noise immunity is a measure of gate’s ability to withstand fluctuations of the voltage levels at its
input
3. The common sources of noise are ground noise, variations, and radiated signals for DC noise margin

Power
The primary causes of power dissipation in digital circuits a r e propagation delays, clock frequency,
circuit topology, and dynamic power (charging and discharging of load capacitances). Out of these,
dynamic power is a major cause that contributes to power dissipation. The dynamic power dissipation
depends both on the functionality of the circuit and the input vectors that are applied to it. Dynamic
power dissipation occurs because of switching activity (0 → 1 or 1 → 0 transitions) in the circuit, which
results in the charging/discharging of the load capacitance.
The dynamic power dissipation PR in the combinational portion of a logic circuit can be computed as
follows:
1
PR  . Vdd2 . f .  ( N ( g ) x C ( g )) (1)
2  gates g

The summation is performed over all the gates g in the circuit; N (g) denotes the number of times
the output of the gate g has switched from 0 → 1 or 1 → 0 (toggled) within a given clock cycle; C (g)
denotes the output capacitance of gate g; f is the frequency of operation; and Vdd is the supply voltage.
Therefore, the total switching activity is the parameter that contributes for power dissipation. To design a
reliable circuit prior the estimation of power dissipation or power consumption is essential in the process of
design flow. General approach to estimate the power component is through simulation of the circuit with
deterministic test vectors or random test vectors. Automatic Test Pattern Generation algorithms are
implemented to simulate the circuit and to estimate the dynamic power dissipation of the circuit.

Timing
The signals through a gate take some amount of time to propagate from the inputs to the outputs of the
gate. This time includes the initial delay and transport delay of the gate, which is known as propagation
delay of a gate. This is measured in time units (nanoseconds). The total time that a signal takes to traverse
from primary inputs to primary outputs in a circuit is considered as the total time taken to pass through
the inputs to outputs. This total time is known as the propagation delay of the circuit.
The input signals in most digital circuits are applied simultaneously to more than one gate. All these gates
at primary inputs and the output of the gates pass through to the next level of the circuit and so on until
the level of the circuit where output reaches to the primary output. Therefore, the propagation delay of the
circuit is computed as follows:
Total Prop Delay = Gate Prop Delay * number of levels of the circuit.

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Chapter 2

The reduction of propagation delay is one of the factors to be considered to increase the speed of the
circuit.

Summary
In this chapter, the design of digital circuits is discussed extensively. The digital circuits are of two types:
combinational and sequential. The basic elements of digital circuits are logic gates: AND, OR, and NOT
(basic gates), NAND and NOR (universal gates), and XOR and XNOR (additional gates). Functionally
complete sets are used to realize any digital circuits. The design of a combinational circuit and detailed
explanation with an example is presented. The completely and incompletely specified functions are useful
to minimize the logic circuit. The basic elements of sequential circuits are discussed briefly. The sequential
circuits are composed of combinational logic and memory elements. The synchronous sequential circuit
changes the state of the circuit with clock pulse and the asynchronous sequential circuit changes the state
of the circuit without clock pulse. The design of synchronous sequential circuits discussed in detail with
example. The importance of state transitions, state tables, and transition graph is illustrated.
Finite state machine is a form of sequential circuits. The two types of finite state machine are Mealy and
Moore machines. The mathematical notation for these machines is given briefly and design concepts with
examples. Finally, the factors that influence the performance of circuits are considered as noise margins,
meta-stability, power dissipation, power consumption, and timing.

Questions
1. Explain the procedure to design the combinational circuits.
2. Explain the procedure to design the synchronous sequential circuits.
3. List the different methods to represent the Boolean expression
4. Write the difference between standard form and canonical form
5. List the differences between synchronous and asynchronous sequential circuits.
6. Define power dissipation, fan-out, and universal gates.
7. What is noise margin?
8. Explain the completely specified sequential machine and incompletely specified sequential machine.
9. Write a procedure to design a 4-bit mod-10 counter
10. What is Mealy and Moore machine?
11. Discuss the procedure to derive the state tables and state transition graphs for the given specifications
where the circuit generates the sequence of numbers as 00, 11, 10, and 00, and then repeats itself.

Exercises
1. Explain the need of incompletely specified combinational circuits.
2. What is the necessity of synchronous sequential circuits?
3. Enumerate the need of functionally complete set.
4. What are the factors that lead to increase the noise immunity?
5. Derive the steps to design Mealy machine.
6. Write the differences between the completely specified finite state machines and incompletely
specified finite state machines.

36
 3
CMOS VLSI Design
If you need information on: See page:
MOS Technology and Fabrication Process 38
pMOS 41
nMOS 43
CMOS 45
BiCMOS 47
Comparison of Different Processes 48
Chapter 3

This chapter gives detailed description of transistor technologies and fabrication process. You also learn
about the physical structure and circuit diagram of p-type Metal-Oxide Semiconductor (pMOS), n-type
Metal-Oxide Semiconductor (nMOS), Complementary Metal-Oxide Semiconductor (CMOS), and Bipolar
Complementary Metal-Oxide Semiconductor (BiCMOS) in detail. The fabrication process concepts to build
Metal-Oxide Semiconductor (MOS) devices and comparisons among different processes are also discussed
in this chapter.

MOS Technology and Fabrication Process

Until 1950’s, electronic device technology was dominated by vacuum tubes. In 1960’s, the invention of the
transistor by William B. Shockley, Walter H. Brattain, and John Bardeen of Bell Telephone Laboratories
made an origin for Integrated Circuits (ICs). The electronic circuits integrated on a single chip are termed
as IC. These ICs are of various sizes and complexities. Electronic circuits are characterized by reliability,
low power dissipation, extremely low weight and volume, and low cost with high degree of computations
and complexities. The main core that consists of a microprocessor, a digital signal processor, and numeric
co-processors has included several millions of transistors on a single chip. Technology advances mainly
contributed towards the miniature in transistor size, reduced power supply consumption, and
enhancement of services with reliability as a major factor.
An IC, also known as chip or die, is a tiny device, which is a collection of patterned material layers in a
specific order to act as an electronic switching network. The two major parts of a chip are:
1. Tiny and a very fragile chip (Silicon chip or die)
2. A package, which is intended to protect the internal Silicon chip
A Silicon die, with a size of 1cm x 1cm, is placed on a printed circuit board of desired logic circuit. The active
part of IC is a thin portion of Silicon die fabricated on a wafer. Each wafer yields numerous chips with
chip die size varying from 5mm x 5mm to 15mm x 15mm, and the whole wafer is processed at a time.
Bipolar Junction Transistor (BJT) and Metal-Oxide Semiconductor Field Effect Transistor (MOSFET or
MOS) are two types of Silicon-based devices that have been used to construct logic circuits. Most Very
Large Scale Integration (VLSI) digital circuits are constructed using CMOS technology. MOSFET, which is
discovered by J. Lilienfeld in 1925, is a basic logic element in CMOS devices. The advantages of these
devices are integration density and simple manufacturing process when compared with other
technologies that made easy to produce large and complex circuits in an economical way.
BJTs are used to design VLSI circuits, but with the limited applications when compared to MOS-VLSI
circuits. The majority of the production is done with the traditional CMOS technology, that is,
approximately 95% of Gallium Arsenide (GaAs), 2% of Bipolar gate arrays, and 1% of others. However,
these CMOS technologies are not suitable for high-speed RF applications.
Silicon CMOS technology has become the dominant process for relatively high performance and cost
effective VLSI circuits. Silicon is a semiconductor that forms a basic material for a large class of ICs. To
design an efficient VLSI circuit, designers must have a working knowledge of integrated chip fabrication
process to create effective designs and optimize the circuit with respect to various manufacturing
parameters. Let’s now discuss the fundamentals of MOS chip fabrication with the major steps of the
process flow.

Fabrication Process
ICs are made up on each wafer, which is a single crystal of Silicon available in the form of thin, flat
circular shape. An IC consists of several layers of different materials on a Silicon wafer. As already
learned, IC that varies in shape, size, and location of material is to be specified as a parameter before the
fabrication process begins.

38
 CMOS VLSI Design

Silicon (Si), GaAs, and Germanium (Ge) are the materials that are used to build ICs. Based on the
movement of electrons, the electrical properties of a material are calculated such that the electrical current
is measured. The resistance to the flow of electricity in a material is measured in terms of amount of
resistance (ohms per unit length) or resistivity. On the basis of resistivity, the materials are categorized as
conductors, semiconductors, and insulators. These three types of materials are used for fabrication
process. The fabrication materials are important to consider the reliability of the die. Let’s now discuss the
materials used for the fabrication process.

Conductors
Materials that have low electrical resistance or high electrical conductivity are called conductors.
Conductors can have resistivity of as low as 1 micro-ohm-cm. Some of the good conducting elements are
Aluminum, Bismuth, Copper, Gold, Platinum, Silicon, and Tungsten. These materials are used to make
connections between devices on a chip. For example, conductors used in the VLSI fabrication are
Aluminum and Gold.

Insulators
Materials that have high electrical resistance are called insulators. These materials have resistivity of more
than millions of giga-ohms. These are used to isolate the devices with different parts of the device.
Insulator used in the VLSI fabrication is Silicon Dioxide.

Semiconductors
Materials that have neither high nor low electrical resistance are called semiconductors. These materials
have resistivity range from 10 m-ohm-cm to 1 giga-ohm-cm. The electrical current is carried by either
holes or electrons. These materials can change their electrical properties by adding impurities into it. If the
impurity elements are added to provide excess electrons, then the resulting material is called n–type
because the excess free electrons have a negative charge. Similarly, if the impurity elements are added to
provide excess holes or positive charges, then the resulting material is called p–type. Arsenic and
Antimony are added as an impurity to form n-type materials; whereas, Aluminum, Gallium, and Indium
are added as an impurity to form p–type materials. Doping is the process of substituting other atoms for
some of the semiconductor materials. The doping materials are also termed as impurities. Silicon is a
major semiconductor material used for the VLSI fabrication.
As already learned, the basic material used for the large class of semiconductor devices and ICs is Silicon.
The fabrication process starts with the creation of a Silicon wafer by crystal growth. A mask is a
specification of geometric shapes that need to be created on certain layers. Masks are used to create
specific patterns of each material in a sequential manner and create a complex pattern of several layers.
Several masks are created one for each layer. The wafer is then processed for size and shape. Devices are
formed by overlapping a material of certain shape in one layer by another material. After patterning of all
the layers, wafer is cut into individual chips and packaged. All the manufacturing process of an IC takes
place in two steps:
1. Wafer fabrication (front-end process)
2. Assembly (back-end process)

Wafer Fabrication
Wafer fabrication is a process of building an IC, die, or chip. Initially, Silicon chip forms a part of very thin
round Silicon slice called raw wafer. Wafer diameter usually varies from 125, 150, or 200 millimeter (5, 6, or
8 inches).

39
Chapter 3

The various steps for the fabrication of an IC are given as follows:

1. Photo Masking
2. Deposition
3. Etching
4. Diffusion
5. Ion Implantation

Photo Masking
The process of producing a pattern on a wafer at desired place is called photo masking. This process takes
place using electron beam focusing on the wafer with selective portions under the beam.

Deposition
Deposition is a process of placing or depositing a material on a raw wafer to change the electrical
properties of the raw wafer. Generally, the raw wafer, which is made up of Silicon, is an insulating
material. The various materials that are used for deposition are insulators, resistive films, and Silicon
Dioxide. The deposition process is done in two ways: physical vapor deposition and chemical vapor
deposition. These depositions are non-selective and are placed uniformly over an entire region of wafer.

Etching
The process of removing unwanted materials over the surface of wafer is called etching. A single IC
undergoes several etches during the process of fabrication for desired circuit. Due to this, chemicals used
for the etching process must be selected in such a way that these materials should not change the
properties of protected areas of wafer. The etching process can be performed in the following two ways:
. Wet: Refers to an etching process where the liquid is used for etching. The horizontal etching and the
vertical etching can be done during this process. The wet etching process is non-uniform due to liquid
chemical agents. The wet etching is also called chemical etching.
. Dry: Refers to an etching process where removal of unwanted material is been performed by
bombardment of ions using electron beam. The dry etching is also called ion etching.

Diffusion
The process of imposing the impurities onto wafer is called diffusion. Silicon features are altered by using
a well-controlled process known as doping the Silicon. Dopants or doping atoms are purposely inserted in
the Silicon lattice to change the features of the materials in predefined areas. These dopants induce the
electrical properties required on semiconductor materials. If the electrical current or charge is carried by
electrons (negative charges), then the material is called n-type material. However, if the electrical current
or charge is carried by holes (positive charges), then the material is called p-type material.
The most frequently used dopants to achieve these features are Phosphorus, Arsenic for negative carriers,
and Boron for positive carriers.
Arsenic results in a semiconductor where the electrical current is carried by electrons; whereas, Boron as a
dopant results in the electrical current carried by holes.

Ion Implantation
Ion implantation is the process of introducing ionized atoms into target wafer or substrate in depth to
avoid any barrier effect of the surface layer.
The etching process is repeated for several times to get the desired circuit. After you get the desired circuit,
the package process takes place, which includes:

40
 CMOS VLSI Design

1. Identifying good and bad chips

2. Assembling and mounting good chips in a plastic or ceramic case
The MOS-based technology is widely used for large scale of ICs. The three major MOS technology families
are pMOS, nMOS, and CMOS. The pMOS and nMOS technologies are popular due to their simplicity in
the fabrication process and are suitable for large-scale or small-scale circuits. As the density of the
transistors increases, the power dissipation increases. These pMOS and nMOS technologies are unable to
sustain the power dissipation. Complementary MOS is a well-known MOS technology, which is used in
present day scenario where Intel x86, Motorola, Pentium, and Multi Core architectures are fabricated with
CMOS process.
The next section explains pMOS, nMOS and CMOS circuit diagram, physical structure, and switch model.

pMOS
An n-type transistor is embedded in a p-type substrate and formed by the intersection of an n-type wire
and a poly Silicon wire. The intersection region is called channel. The transistor action takes place in the
channel. Channel connects two n-type wires that form the Source (S) and Drain (D), which are doped in p-
type substrate also known as n-well or n-channel. To implement p-channel transistors, p-type dopants
(Boron) are diffused into an n-type (Silicon) substrate to form S and D. The electrical charge or current
takes place using holes or positive charge carriers. As the channel is composed of positive charged
carriers, it is called p-channel or pMOS. Indium and Gallium are also p-type materials that are used for
doping. The physical structure and circuit symbol of pMOS transistor is shown in Figure 3.1 (a) and (b);
and the switch model created using the pMOS transistor is shown in Figure 3.1 (c):

41
Chapter 3

Figure 3.1: Displaying the PMOS Structure

The physical structure shown in Figure 3.1(a) consists of two p+ regions and one n-well or n-channel; the
two p+ regions act as S and D; the charge carrier takes place through holes in n-well; the n-well is
connected to VDD; and the Gate (G) is connected to S and D.
The circuit symbol shown in Figure 3.1 (b) consists of S, D, and G. The bubble at the gate of pMOS
transistor implies that its gate must be at a low voltage in order for it to turn ON. In other words, the
pMOS transistor is a device that conducts when gate voltage is low.
In Figure 3.1 (c), VSS and VDD represent ground voltage and source voltage, respectively. The logic level
of the switching device is shown in Table 3.1:
Table 3.1: Logic Levels of pMOS Switching Device
Gate Logic Level pMOS

1 1 OFF

0 0 ON

nMOS
The nMOS technology is similar to the pMOS technology; however, the difference is with the charge
carriers. A p-type transistor is embedded in an n-type substrate and formed by the intersection of p-type
wire and a poly Silicon wire. This intersection region is called p-channel. The p-channel connects two n-
type wires that form S and D, which are doped in the p-type substrate also known as p-well or p-channel.
To implement n-channel transistors, n-type dopants (Phosphorus) are diffused into a p-type (Silicon)
substrate to form S and D. The electrical charge or current takes place using electrons or negative charge
carriers. As the channel is composed of negative charged carriers, it is called n-channel or nMOS. Arsenic
and Antimony are also n-type materials that are used for doping. The physical structure and circuit
symbol of nMOS transistor is shown in Figure 3.2 (a) and (b) and the switch model created using the
nMOS transistor is shown in Figure 3.2 (c):

42
 CMOS VLSI Design

Figure 3.2: Displaying the NMOS Structure

43
Chapter 3

The physical structure shown in Figure 3.2 (a) consists of two n+ regions and one p-well or p-channel. S
and D are created by doping impurities as n+ regions. The charge carrier takes place through electrons in
p-well; this p-well is connected to VDD; and G is connected to S and D.
The circuit symbol shown in Figure 3.2 (b) consists of S, D, and G. The absence of bubble at the gate of
nMOS transistor implies that its gate must be at a high voltage in order for it to turn ON. In other words,
the nMOS transistor is a device that conducts when gate voltage is high. The nMOS are 2.5 times faster
than pMOS due to their mobility of electrons.
The logic level of the switching device is shown in Table 3.2:
Table 3.2: Logic Levels of nMOS Switching Device
Gate Logic Level nMOS

0 0 OFF

1 1 ON

CMOS
The CMOS technology was invented during 1960 and P. K. Weiner succeeded in the year 1962 with the
basic elements to build. In the year 1963, fully-customized CMOS was invented and introduced three basic
logic gate structures (NAND, NOR, and NOT) with CMOS technology. Nowadays, the market is
dominated by CMOS technologies for designing VLSI systems.
CMOS technologies combine both pMOS and nMOS transistor devices on the same Silicon. Both the
transistors require two different substrates, that is, the nMOS transistor requires a p-type substrate and the
pMOS transistor requires an n-type substrate. You can use either a p-type or n-type Silicon substrate as a
channel. However, the opposite doping type called wells must be defined to allow fabrication of the
complementary transistor type. CMOS allows fabrication of nMOS and pMOS transistors side by side on
the same Silicon substrate.
The advantage of CMOS is that its logic elements draw current only during the transition from one state to
another; and therefore, power is conserved. CMOS speed is mainly depends on device parameters, such as
saturation current and capacitance. This in turn depends on oxide thickness, substrate doping, and
channel length.
The various process methods are evolved to build CMOS circuits, such as n-well, p-well, twin-well, and
Silicon, on insulator technology. The process method varies depending on the type of substrate used for
the foundation as a channel. Some of these process methods are described as follows:
1. p-well
2. n-well
3. twin-tub

The p-well Process

The p-well process is the most commonly available forms of CMOS technology. Initially, if the n-type
substrate is doped, then p-well is created to build the p-channel transistor. The physical structure of
CMOS transistor built using the p-well process is shown in Figure 3.3(a):

44
 CMOS VLSI Design

Figure 3.3 (a): Displaying the CMOS Structure

These devices are preferable for applications where characteristics of both p-channel and n-channel are
required.

The n-well Process

In the n-well process, the foundation of n-well process is the p-type substrate followed by an n-well to
build n-channel transistors. These are latched side by side to form CMOS transistor in this process. The
physical structure of CMOS using this n-well process is shown in Figure 3.3 (b).:

Figure 3.3 (b): Displaying the n-well Process CMOS Structure

Figure 3.3 (c): Displaying the p-well Process CMOS Structure

The twin-tub Process

In this process, both the p-channel and n-channel transistors are constructed individually by creating n-
well and p-well. The foundation can be of any type substrate that acts as a neutral substrate. This process
is more flexible but complicated to build.

45
Chapter 3

BiCMOS
As discussed, a major disadvantage of MOS technology is its limited load driving capabilities due to
limited current sourcing, sinking abilities of pMOS and nMOS transistors, and speed. Similarly, the
limitation of bipolar transistors is high power dissipation. To overcome these limitations, BiCMOS
transistors were introduced in late 1970s. VLSI circuits started using BiCMOS technology during 1980s
that resulted in high-speed memories, gate arrays, and microprocessors.
BiCMOS is a combination of bipolar junction transistors and CMOS transistors. These are integrated into
a single IC. The physical structure of BiCMOS is shown in Figure 3.4:

Figure 3.4: Displaying the Physical Structure of BiCMOS

The limitation of BiCMOS includes the complexity involved in design process stage. In addition, the
BiCMOS die cost is 1.25 - 1.4 times higher than the conventional CMOS. Taking into account the packaging
costs, the total manufacturing costs of supplying a BiCMOS chip ranges from 1.1 to 1.3 times that of
CMOS.
The existing available Silicon technologies are used for different applications based on their relative merits
and demerits, such as CMOS technologies used for logic devices and BiCMOS for implementing I/O and
driver circuits. For very large circuits, simultaneously switching and internal clock skews can impose
severe performance penalties due to CMOS transistors; and therefore, BiCMOS has gained importance
over CMOS.

Comparison of Different Processes

In this section, a comparative study is given for various existing technologies, such as CMOS, nMOS,
pMOS, and BICMOS. The parameters, such as power dissipation, propagation delay, noise margin, and
fan out are compared.

Power Dissipation
This parameter is measured in mill watts (mW). It represents the actual power delivered by the gate or
circuit from the power supply. The sum of the total power dissipated in all the gates, circuits, or ICs in the
design is considered as the power dissipated by the system.

46
 CMOS VLSI Design

Propagation Delay
This parameter is the most important factor to measure the performance of the circuit. Time taken to
propagate a signal from the input of the gate to the output of the gate is called the propagation delay of
the gate. Similarly, time taken to propagate signal or signals from the primary input to the primary output
is called the propagation delay of the circuit. This is expressed as nanosecond (ns) where 1 ns = 10-9 of a
second.
The input signals in most digital circuits are applied simultaneously to more than one gate. All the gates
receive their inputs from external inputs considered as the first logic level circuit. In other words, primary
inputs are given as an input to the first level logic circuit. Gates that receive inputs from the first level of
the circuit are considered as second logic level and similarly, for further level until the signal reaches to
primary output. Therefore, the total propagation delay of the circuit is equal to the propagation delay of a
gate times the number of levels in the circuit. As the number of logic levels increases, the delay increases.

Noise Margin
Noise margin is the maximum noise voltage added to the input signal that does not cause any damage or
undesirable change to the circuit. The two types of noise margins are Alternating Current (AC) noise and
Direct Current (DC) noise. A drift in the voltage levels of a signal causes the DC noise; whereas, the AC
noise is a random pulse created by switching of signals. The ability of the circuit depends on the reliability
to operate in a noise environment.
The advantages of CMOS transistor and BiCMOS are compared with respect to the parameters discussed
are listed as follows:

Advantages of CMOS transistors

1. Low static power dissipation
2. Power consumption is less
3. The net delay is reduced by increasing driver sizes
3. Higher packing density leads to lower manufacturing cost per device
4. High yield with large integrated complex functions
5. High input impedance
6. Scalable threshold voltage
7. High delay sensitivity
8. Low output drive current

Advantages of BiCMOS
1. Improved speed over CMOS
2. Low power dissipation
3. Flexible I/Os

Summary
In this chapter, you have learned about the basic transistor technologies and their applications.
The materials used to build transistors are categorized based on their resistivity and conductivity. These
materials are insulators, conductors, and semiconductors. You have also learned about the MOS transistor
fabrication process, which consists of wafer fabrication and device assembling. The wafer fabrication
consists of a sequential set of basic steps: photo masking, deposition, etching, diffusion, and ion
implantation. The pMOS and nMOS transistors dissipate power even when the output is low or high. The

47
Chapter 3

combination of pMOS and nMOS transistors is used to build the CMOS transistor, which dissipates power
only while switching. The processes, such as p-well, n-well, and twin-tub are used to build CMOS device.
These processes are varied based on the type of substrate placed as a foundation to combine pMOS and
nMOS transistors side by side. The major drawback of CMOS circuits is that the total number of
transistors require to build are more than nMOS circuits. BiCMOS circuits are built using bipolar and
CMOS transistors. These technologies are compared with the parameters, such as power consumption, net
delay, noise margins, and power dissipation.

Questions
1. What are the characteristic features of nMOS, pMOS, and CMOS?
2. Define semiconductors. Why semiconductors are used to build transistors?
3. Explain the wafer fabrication process for MOS technologies.
4. Differentiate between p-channel and n-channel.
5. What is ion implantation?
6. Differentiate between dry and wet etching.
7. Explain the physical structure of pMOS and nMOS with diagrams.
8. Explain the switch model of CMOS.
9. Write the differences between the pMOS and nMOS with CMOS technologies.
10. Explain the BiCMOS features when compared with CMOS.

Exercises
1. Explain the merits and de-merits of nMOS, pMOS, and CMOS.
2. Draw the schematic for NOT-gate function using MOS-technology.
3. Study the comparison between the MOS technologies.
4. Study the characteristics of Silicon technology fabrication process and its merits.
5. Study the various fabrication processes for VLSI technology.

48
 4
Building Blocks of
a VLSI Circuit
If you need an inforamtion on: See page:
Computer Architecture 50
Memory Architectures 57
Communication Interfaces 59
Mixed Signal Interfaces 61
Chapter 4

In this chapter, you learn about the building blocks used to design very large-scale systems. The design of
logical components, such as multiplexer (MUX), decoder, priority encoder, comparator, memory arrays,
and communication interface concepts, are discussed. Towards the end, you learn about mixed signal
interfaces.

Computer Architecture
While designing a large digital system, such as computer, millions or thousands of individual gates are
required to create the desired system. The basic logic gates (NOT, AND, and OR) are used to create
complex logic designs. As the complexity of the circuit increases, the logic gates required to build the logic
increases. The most difficult task is to keep track of each gate in the circuit for testing and verification of
the design. The other factor is propagation delay, which is a major bottleneck that increases as the level of
the circuit increases. To remove these difficulties, the solution is to use the hierarchical approach where a
complex design or a very large function is defined using a logical or digital component of a system that
represents a specific function with more than one or two gates. These digital and logical components act as
a basic building block for large system design. The logical components of digital systems are MUX,
decoder, priority encoder, magnitude comparator, and bit adder.
The functional description of these components with block diagram is given in the following sections.

MUX
The MUX is a logic circuit that consists of n-input lines and one output as F. The selection of a particular
input line for output is determined by a set of selection inputs. The number of selection inputs (m) to a
MUX is determined as,
m = log2(n)
Where, m - Selection input lines
n – Number of input lines
For example, 2-to-1 MUX has two inputs as i0 and i1 , one output line as F, and one selection line as S. The
block diagram is represented as black box with inputs, output, and selection lines; whereas, the functional
diagram shows the logic circuit represented with gates. The functional table gives the input, output, and
selection inputs information. Similarly, 4-to-1 line MUX has four data inputs i0, i1, i2 , and i3 , one output
line as F, and two selection lines S0 and S1. Figure 4.1 (a), (b), and (c) shows the block diagram, functional
diagram, and functional table of a MUX:

Figure 4.1 (a): Displaying the Block Diagram of N X 1 MUX

50
 Building Blocks of a VLSI Circuit

Figure 4.1 (b): Displaying the Functional Diagram of 4 X 1 MUX

Multiplexer
Figure 4.1 (c): Displaying the Functional Table of 4 X 1 MUX
MUX is also called data selector since it selects one of many data inputs as output. Generally, more than
one MUXes are enclosed within a single integrated circuit package. Some of the applications of these
MUXes are logic function analyzer/generator, path selection for routing, and parallel-to-serial conversion.
The MUX is considered as a universal logic module since it can be used to design any combinational logic
circuit.

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Chapter 4

Decoder
A decoder is a digital circuit that converts the binary information from the n coded inputs and produces m
output lines. The value of m is equal to a maximum of 2n unique outputs. The decoders are represented as
n to m line decoders where n is the number of input lines and m is the number of output lines. The
decoder is also referred to as n x m (pronounced as n by m) decoder. The truth table or functional table
gives the behavioral description of the circuit for all the possible combinations of input values. For
example, consider the 2-to-4 line decoder. The truth table for the decoder has two input variables a and b
with four possible combinations of input values as 00, 01, 10 , 11 and four output variables as x, y, w, z.
The output value 1 represents the equivalent binary number of input value. The decoder circuit can be
implemented using the NAND and AND gates. Figure 4.2 (a), (b), and (c) shows the block diagram,
functional diagram, and truth table of a decoder:

Figure 4.2 (a): Displaying the Block Diagram of n X m Decoder

Figure 4.2 (b): Displaying the Functional Diagram of 2 X 4 Decoder

52
 Building Blocks of a VLSI Circuit

Figure 4.2 (c): Displaying the Truth Table of 2 X 4 Decoder

Decoder circuits are mainly used as code converter circuits, such as binary-to-octal converter and BCD-to-
seven segment display circuit.

Priority Encoder
An encoder is a combinational logic circuit that converts the 2n input lines into n output lines. The output
lines generate the binary code corresponding to the input value. The output value is based on the input
lines, that is, 2n input lines. A priority encoder is a combinational circuit with m = 2n inputs and n outputs.
Each of the m inputs is assigned a priority. The most significant bit of the input has the highest priority;
whereas, the least significant bit has the lowest priority. The n-bits of the output are represented in binary
form. For example, if n = 2, then m = 4, that is, 22 . The priority encoder is of 4-to-2 line device with four
input lines as i0, i1, i2, and i3 and two output lines as O1 and O2. These encoders are used in the
implementation of interrupt service routine. Figure 4.3 (a), (b), and (c) shows the block diagram, functional
diagram, and functional table of a priority encoder:

Figure 4.3 (a): Displaying the Block Diagram of m X n Priority Encoder

Figure 4.3 (b): Displaying the Functional Diagram of 4 X 2 Priority Encoder

53
Chapter 4

Figure 4.3 (c): Displaying the Functional Table of 4 X 2 Priority Encoder

Magnitude Comparator
Magnitude comparator is a combinational logic device used to compare two numbers or n-bit numbers
and determines the relation between two numbers. The relation is identified as greater than, less than, or
equal to. In the truth table and logic circuit, two 2-bit numbers and two output lines are identified as the
input and output lines of the circuit. These comparators are used mainly in digital control systems and
digital-to-analog devices. Figure 4.4 (a), (b), and (c) shows the block diagram, functional diagram, and
functional table of a magnitude comparator:

Figure 4.4 (a): Displaying the Block Diagram of a Magnitude Comparator

Figure 4.4 (b): Displaying the Functional Diagram of a Magnitude Comparator

Figure 4.4 (c): Displaying the Functional Table of a Magnitude Comparator

54
 Building Blocks of a VLSI Circuit

Bit-Adder
The most basic arithmetic operation is the addition of two binary digits. The combinational circuit that
performs the addition of two bits is called Half Adder. Figure 4.5 (a), (b), (c) shows the block diagram,
functional diagram, and functional table of a Half Adder:

Figure 4.5 (a): Displaying the Block Diagram of a Half Adder

Figure 4.5 (b): Displaying the Functional Diagram of a Half Adder

Figure 4.5 (c): Displaying the Functional Table of a Half Adder

In Figure 4.5, x and y are the input variables and Sum and Carry are the output variables of a Half Adder.
Similarly, Full Adder is designed to perform the addition of three binary digits. Figure 4.6 (a), (b), and (c)
shows the block diagram, functional diagram, and functional table of a Full Adder:

Figure 4.6 (a): Displaying the Block Diagram of a Full Adder

55
Chapter 4

Figure 4.6 (b): Displaying the Functional Diagram of a Full Adder

Figure: Full - Adder

Figure 4.6 (c): Displaying the Functional Table of a Full Adder
In Figure 4.6, the input variables are termed as x, y, and z; whereas, the output variables are termed as
Sum and Carry.
Half Adder and Full Adder are the basic bit adder circuits that are used to build the adder circuit for n-bit
numbers where n is greater than three.
To design an n-bit adder circuit, various circuits, such as ripple carry adder, parallel adder, carry save
adder, carry skip adder, and carry look ahead adder, have been implemented. Two binary numbers, each
of n-bits, can be added by using the simplest circuit called the ripple adder circuit. The n-bit ripple adder
circuit is designed using n-Full Adder circuits. These Full Adder circuits are cascaded to generate the sum
of two n-bit numbers and carryout of two n-bit numbers (Figure 4.7). The carryout of each Full Adder is
connected to the next carry input of the next most significant Full Adder circuit.
For example, let A and B are two 4-bit numbers indexed as A3, A2, A1, A0 and B3, B2, B1, B0. The sum S3, S2,
S1, S0 and carryout (termed as Cout) are generated using the Cascaded Full Adder circuit, as shown in
Figure 4.7:

56
 Building Blocks of a VLSI Circuit

Figure 4.7: Displaying the 4-bit Parallel Adder

Memory Architectures
A memory unit is a collection of data stored. The main memory of a computer is used for storing
programs, data, and operands. Memory stores the information in the form of group of bits called words.
These words in memory are organized in square form so that they have an equal number of rows (x) and
columns (y). Each intersection of a row and column comprises a memory word address. Each memory
address contains a memory word. Memory operations, such as read or write, operate on a request,
selection, and initiate basis. The data transfer from memory modules or units can be done in two ways:
serial access and parallel access. The circuits that are designed to access data serially are called shift
registers; whereas, the circuits associated with parallel access are called random memories. The two
different types of random memories used in computer systems are Read Only Memory (ROM) and
Random Access Memory (RAM). Let’s now learn about shifters, ROM, and RAM in detail.

Shifter
Shifter is a logic circuit designed to perform the logical shift left and logical shift right operations. Logical
shift left performs the shift operation on the bits of n-bit register by moving the bits one position to the left
and leaving the rightmost bit value as 0. Similarly, logical shift right performs the shift operation by
moving the bits of n-bit register one position to the right and leaving the leftmost bit value as 0. This
circuit can be designed using either MUXes or transistors. Figure 4.8 (a), (b), (c) shows the logic diagram,
functional table, and functional diagram of a shifter:

Figure 4.8 (a): Displaying the Logic Diagram of a Shifter

Figure 4.8 (b): Displaying the Functional Table of a Shifter

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Figure 4.8 (c): Displaying the Functional Diagram of a Shifter using a MUX

ROM
ROM is a memory device used to store the binary information permanently. Figure 4.9 (a) shows the block
diagram of ROM device where m is the number of output lines that are equal to the number of bits per
word to be stored in it permanently. The word that is available on the output lines at any given time is
determined by the values (binary information) at the input lines. ROM is constructed using decoders and a
set of OR gates. It is purely a combinational circuit as the data is permanently stored in ROM. An address
is a binary number that denotes one of the minterms of n-variables. The number of distinct addresses
possible with n-input variables is 2n. These circuits are used as basic building blocks in the Very Large
Scale Integration (VLSI) circuits to increase the memory capabilities.
Consider an example to store 1024 bits in ROM. To design the ROM device to store 1024 bits, 10 input lines
are required. Figure 4.9 (b) shows the block diagram of ROM with 1024 lines:

Figure 4.9(a): Displaying the Block Diagram of ROM

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 Building Blocks of a VLSI Circuit

Figure 4.9(b) – Displaying the Block Diagram of ROM with 1024 Lines

RAM
RAM is designed to access data parallely or randomly from any desired location. The time required to
access memory location is same irrespective of the physical location of data. RAM is also known as read or
write memory as both read and write operations can be performed on it. Read operation refers to the
retrieval of the stored data on demand; whereas, write operation refers to the modification in the stored
data. Each bit or word is stored or retrieved using address lines, which are specified as memory locations
of the data. As both read and write operations can be done randomly, read and write control signals are
used to control these operations. Read control signal is used to access the memory location to transfer the
data from specified address memory location onto output lines; whereas, write control signal is enabled or
activated to modify the data on specified address location by the input data lines. RAM can be classified
into two categories: Static RAM and Dynamic RAM.
Figure 4.10 shows the block diagram of RAM:

Figure 4.10: Displaying the Block Diagram of RAM

The n-data input lines and output lines provide the information to be stored in memory with k-address
lines, where k = log2 n. Read and write signals act as control signals. On accepting these signals, internal
circuitry of memory provides necessary function.

Communication Interfaces
The concept of multiprocessor system to meet system performance requirements, such as speed, has
become an attractive design possibility. The components, such as central processing units, I/O processors
connected to input and output devices, and memory units, form a multiprocessor system. The
interconnection among these components can have different physical configurations. These
interconnections are established using physical forms, such as time-shared common bus, multi-port
memory, and crossbar switch, called interconnection networks. Data transmission from one component to
another use these interconnection networks as a medium to transmit the data effectively.
To do this, first and foremost thing is to decide how to encode the data to be sent, that is, its computer
representation. This will differ according to the type of data, such as audio, text, and video.
Data representation can be divided into two categories:
 Digital: Refers to a representation where data is encoded as a set of binary values, that is, a sequence
of 0’s and 1’s
 Analog: Refers to a representation where data is denoted by the variation in a continuous physical
quantity

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Data transmission can be done in two ways:

1. Serial
2. Parallel

Serial Data Transmission

Data in the serial transmission technology is transmitted one-bit-at-a-time across the physical links known
as transmission lines. Serial Communication Interface (SCI) is a device that enables transmission of digital
data bit-by-bit serially. Multiprocessors, Internet, and peripheral devices, such as printers, external drives,
and scanners, are some of the examples of serial communications. A brief overview of SCI is discussed in
the next section.

SCI
SCI enables serial communication between microprocessors and peripheral devices or within an external
network. It contains data transmitter at the source end and data receiver at the destination end to ensure
serial data transmission. The basic component required to design data transmitter is parallel-to-serial
converter. Similarly, serial-to-parallel converter is used to design a data receiver. Along with these two
devices, enable and interrupt signals are used to perform the transmission of data serially. The speed of
these devices can be programmed based on the requirements. These devices can operate in the
synchronous mode or the asynchronous mode.
In the synchronous mode, the transmitter and receiver are paced by the same clock. The receiver
continuously receives the information at the same rate the transmitter sends it. During the synchronous
transmission, the bits are sent successively with no separation between each character. To ensure the
reliable data transmission, an additional character is necessary to insert that in turn ensures
synchronization between transmitter and receiver modules.
In the asynchronous mode, each character is sent at irregular intervals of time. Both source and destination
does not necessarily act at the same clock. Source can initiate the data transmission by sending a signal to
the receiver. Each character is preceded by some information indicating the start of character transmission
using the START bit. Similarly, each character is followed by some information indicating the end of
character transmission using the STOP bit. The START bit refers to the information that starts the
transmission and STOP bit refers to the information that ends the transmission. Asynchronous data
transmission is used for keyboard, mouse, modem, and serial printer.
The standard SCIs are Universal Synchronous Asynchronous Receiver Transmitter (USART), RS232, RS
422, RS485, Ethernet, Fiber Optics, Bluetooth, and Wi-Fi.

Parallel Data Transmission

As the name implies, parallel data transmission refers to the simultaneous data transmission. All the bits
or data can be transmitted at a time. To transmit data or bits, multiple lines are required across the media.
These bits are sent simultaneously over multiple different channels (wire or cable). For example, a 4-bit
parallel channel transmits 4-bits simultaneously across the 4-line wire. In addition to the four parallel data
lines, other lines are used to read status information and to send control signals. For n-bit data,
transmission over serial lines takes n-unit delay; whereas, parallel data lines require 1-unit of time to
transmit. When you compare the performance of parallel data transmission with serial data transmission,
parallel data transmission is faster but at the cost of multiple lines overhead.
For example, 4-bit data is transferred in 4-units of time over serial lines; whereas, 1-unit of time is required
for parallel transmission.

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 Building Blocks of a VLSI Circuit

Parallel Communication Interface

The parallel communication interface device supports the transfer of data across the lines between source
and destination by maintaining synchronization with respect to speed and availability of the resources.
This interface can perform synchronous and asynchronous mode of transmission over parallel ports.
Initially, parallel transmission was tested on dot-matrix printers and since then, portable disk drives have
adopted the parallel interface. Some examples of parallel communication interfaces are IEEE-488 parallel,
Centronics parallel protocol, Small Computer System Interface (SCSI), Integrated Drive Electronics (IDE),
and Peripheral Component Interconnect (PCI).

Mixed Signal Interfaces

For data transmission, data is converted into digital data to transmit across the signals either serially or
parallely. In real time applications, it is not possible to represent the data either only in digital or in analog.
For example, speech, music, light intensity, and color are not discrete values ("on" or "off"), but they are
analog in nature. Analog data is represented as a continuous data. Due to this, interface circuits are
needed in all these applications to interface the analog signals in the world around us with the digital core
of the electronic system.
Micro Electro Mechanical Systems are becoming an essential part of future VLSI systems, known as
embedded systems that include sensors, actuators, accelerometers, pressure sensors, switches, filters,
resonators, and supporting electronic devices.
Mixed signal interface components can communicate or transmit analog or digital data. Integration of the
analog interface electronics on the same digital chip is a common demand, resulting in mixed analog-
digital or mixed signal integrated systems. Applications where mixed signal interface components can be
extensively used are telecommunications, biomedical, consumer, and automotive systems. Components
that are essential in mixed-signal interface devices are data converters (Analog-to-Digital and Digital-to-
Analog), sensor interfaces, and actuators. Analog interfaces connect the analog sensors and actuators to
the digital system processor. Digital interfaces implement data communication channels, such as
Universal Asynchronous Receiver Transmitter (UART), RS232, RS422, and RS485.
Analog-to-Digital Converter: This converter has both analog and digital functions; therefore, it is termed
as mixed signal device. In other words, it is a device, which provides digital representation of analog data.
Analog data is given as an input to the device in terms of current or voltage. For example, 3-bit Analog-to-
Digital converter converts input voltage or current to 3-bit digital output representation. An input voltage
of 0 produces output code as 000. The number of output codes ranges from 0- to- 7 (that is, 000, 001, 010,
011, 100, 101, 110, and 111). As the input voltage increases, the output code varies with respect to the
threshold value. Threshold value is computed with respect to the number of bits to compute an accurate
conversion of input voltage. Difference between all the output codes ranges from 0-7 (0 to 2n-1).
An approximation is computed between input voltages to convert it into digital representation. Similarly,
Digital-to-Analog converter converts the digital representation of input to the analog representation of
output. These mixed signal devices are implemented for efficient implementation of embedded systems
applications.

Summary
This chapter has introduced the basic building blocks of computer hardware system and explained each of
these components and their impact on building efficient architectures. The basic hardware components,
such as MUX, decoder, and priority encoder, are used to select among the input lines onto output lines.
The MUX device is used to select one input among the 2n input lines, and it is also called universal device
because any logic circuit can be implemented using it. Decoder selects among the n-input lines and places
on a 2n-output line. Similarly, priority encoder device selects the input-line based on the priority assigned

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to each of the line. Relational operations of the input data are identified using magnitude comparator
device. Adder is an arithmetic device that performs addition of binary bits. Most important part of
hardware component is a device to store and retrieve data. Serial data retrieval is done using shifter
device; whereas, random access is done using random access memories. This chapter has also introduced
main features of communication interfaces. Communication interface devices are classified into serial
communication and parallel communication interfaces. The importance of these interfaces and concepts
are also discussed. Combination of digital data and analog data representation devices are called mixed-
signal devices. This chapter is concluded with insights of mixed-signal interface devices and their major
role in developing embedded system applications that include sensors, actuators, and other supporting
electro-mechanical devices.

Questions
1. Why MUX is called a universal circuit? Explain.
2. Explain the functionality of decoder circuit and its applications.
3. Discuss advantages of decoder and priority encoder circuits.
4. Write the functions of magnitude comparator and explain with circuit diagram.
5. Design n-bit adder with (n-1) delay using n-full adders.
6. Differentiate between synchronous and asynchronous mode of data transfer.
7. Write the applications of shift registers.
8. List the differences between ROM and RAM.

Exercises
1. Design a 16X1 using only 4x1 MUXes.
2. Design a 2-bit magnitude comparator using only NAND gates.
3. Draw the serial data transmission communication interface across serial-to-parallel converter.
4. Discuss the mixed signal interfaces with examples.
5. Design a 4- input NAND gate functionality using a MUX device.

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VLSI Design Issues
If you need information on: See page:
Design Process 64
Design for Testability 64
Technology Options 67
Power Calculations 70
Package Selection 70
Clock Mechanisms 71
Mixed Signal Design 73
Chapter 5

In this chapter, the process of designing the Very Large Scale Integration (VLSI) circuits and issues are
discussed in detail. The testing and verification procedure is been discussed in detail for the circuits.
This chapter describes the importance of testing, test process, design for test, fault models, and test
programs in detail. This chapter also provides an overview of various parameters involved for designing
efficient design of complex circuits with respect to the clock mechanism adopted, power consumption of
the device or chip, and appropriate package mechanism. Brief overview of mixed signal design is also
presented in the chapter.

Design Process
The sequence of steps required for VLSI designs to design a chip with constraints, such as size, area,
power, and delay, is called design process, which can vary on the basis of the type of chip (ASIC or
FPGA). However, the process of designing a VLSI circuit is a highly complex task. As the complexity of
the design increases, the design flow and its verification become tedious. Therefore, the Computer-Aided
Design (CAD) tools are used to ease the process of design flow by using the automation process. The
process for developing a chip from concept to Silicon is been divided into the four tasks. The brief
description of these tasks is given as follows:
1. Design: The process of designing starts with the description of the specifications of the system to be
designed. The description of the design can take place in any of the following three forms:
a. Behavioral Domain: Specifies the hardware implementation of the system’s functionality with
the help of a sequence of register transfer statements
b. Structural Domain: Refers to a domain where the design is described with a set of sub-modules
connected together to function the prescribed behavior based on the users specification
c. Physical Domain: Specifies the layout used to build the system according to the architect’s idea
at the transistor level
2. Verification: The process of verification is done to verify the functionality of a chip that is to be
performed according to its system requirement specification. Verification is an important step for
designing reliable designs. The verification of a design is done at various levels, that is, at the higher
level of abstraction (register transfer level) to the lower level of abstraction (transistor level).
3. Implementation: After the successful completion of the verification process, the required design can
be realized onto the hardware. The process of implementation is done for the physical
implementation of the required function with the actual hardware component that results in an entity
or product, which includes both the logical and physical implementations.
4. Software Development: The verified design with all the necessary hardware components is
considered to convert it into a stream of bits to program onto the target device. Due to this reason, the
task is termed as software development. This is the last task, that is, the process of programming the
brain of the chip for the desired functionality.

Design for Testability

This section describes the purpose of verification through test process and introduces the concept of
design for testability to ensure the reliability of the final product. The main purpose of the test process is to
verify the functionality of the circuit to meet the design constraints and measure the quality of the end
product in terms of response time and sustainability for extreme power dissipations to provide reliable
circuits. Testing is one of the important factors in manufacturing the product. The cost of testing process
plays a major impact on total cost of the product- approximately 60% of the cost of the product. Apart
from testing cost, total cost of the product depends on two other factors: Silicon cost and Packaging cost.
Testing cost is the time taken to verify the product (test time).

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What is testing?
Testing is a process of verification. It can be done when a known input is applied to a unit and a known
response can be evaluated. In other words, the response from a circuit is compared with a known response
or a predictable response. The testing process is equally applicable to circuits, chips, boards, and systems
from transistor level, gate level, microcells, chips, and printed circuit boards. Figure 5.1 illustrates the
block diagram of a testing unit:

Figure 5.1: Displaying the Block Diagram of a Testing Unit

As shown in Figure 5.1, Device Under Test (DUT) is a unit or a circuit to be tested. The circuit can be in
any form: transistors, gates, or macro cells. Testing a DUT requires a known input to verify the known
output. In case of digital circuits, the input given to a DUT as a group of bits in the form of 0’s and 1’s are
called vectors. The vectors, which are used to test the unit or device, are known as test vectors/ input
stimulus.
For any two-input circuit, the exhaustive testing for each input set can be done by using four test vectors.
Let’s take an example of a two-input XOR gate. For a two-input XOR gate, the test vectors are 00, 01, 10,
11 and the known output for the test vectors is 0, 1, 1, 0, respectively. Figure 5.2 displays a two-input XOR
gate:

Figure 5.2: Displaying the Two-Input XOR Gate

Similarly, for a three-input circuit, the test vectors are 000, 001, 010, 011, 100, 101, 110, and 111. Based on
the circuit specification and behavior, the output response is compared with the output of DUT. If the
results for every possible input is verified and are correct, then the DUT is considered for the further step,
that is, fabrication onto chip.
When a test vector is applied to a DUT circuit, the response is evaluated with the expected output. If the
evaluated response did not match, then a failure occurs; otherwise, DUT is considered for the next step,
that is, fabrication. The term defect or fault is used to define the failure in the DUT.
Defects are the problems that occur in Silicon. It is treated as a physical failure of the chip. Some of the
defects in a Silicon chip are listed as follows:
1. Processing defects: For example, power supply (VDD) or ground (VSS) shorts, gate-oxide shorts, open
and plugged Vias, and process or mask errors
2. Material defects: For example, surface impurities and crystal breakdowns
Fault relates the defect in circuit behavior. In other words, defect in a circuit is caused due to several
reasons, such as imperfect connections, poor insulation, grounding, or shorting. To measure the effect of a
fault, a model is required to detect the defect in the circuit. Similarly, to detect the fault or defect of the
circuit, testing process is required to identify the fault. The testing process to detect the defect or fault in
the circuit is called a fault model. In other words, fault models detect the faults in the circuit. The fault

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model varies based on the type of fault. The fault may be classified as undetected, detected, blocked, tied,
redundant, and untestable. Out of these, the undetected faults are those faults that are not detectable by
any test vectors.
Fault model is created to verify the DUT. A fault model identifies the targets for testing the device or chip
behavior. This model helps in analyzing the faults in the system such that to design a testing method, you
need to detect the fault in the circuit. The various fault models are listed as follows:
 Single stuck-at faults
 Transistor open and short faults
 Memory faults
 Functional faults
 Delay faults
 Analog faults
Stuck-at-fault and transistor open and short faults are two common fault models that are used in the
present day verification process. Before learning about the two fault models, let’s first learn about the fault
coverage.

Fault Coverage
Fault coverage is a measure to detect the percentage of faults by the applied test vectors. Testing involves
the detection of all the possible faults in a DUT. Performance of testing process is measured by the
percentage of fault coverage. For example, if a fault coverage is 100%, then the test process and test vectors
detect all the possible faults in DUT. In other words, fault coverage gives the measure of goodness of the
test program. The major issue of design for test is to improve the percentage of fault coverage.
Let’s now learn about the single stuck-at fault and transistor open and short faults models in detail.

The Single Stuck-At Fault Model

Single stuck-at fault is a fault model used to detect faults in digital circuits. This model defines the
following three properties to find the faults in the circuit:
1. Only one line is faulty The faulty line is permanently set to logic 0 or logic 1 The fault can be at input,
output, or internal wire of the circuit
Design for testability within ASICs and FPGAs are mainly based on this single stuck-at fault model.
To generate a test for a stuck-at fault on a single line, it must first be forced to a value that is opposite
to stuck-at value on the line. For example, for a line to find whether it is stuck-at logic 0 or not, that
line has to force with the logic 1. The ability to apply the input test vectors to the primary inputs of a
circuit to set up appropriate logic value (logic 0 or logic 1) is known as controllability. For example, in
the presence of fault, the primary input has to set logic 1 for stuck-at-0 fault and is known as 1-
controllability.
Similarly, observability is the ability to observe the response of a fault on an internal node through
primary outputs of a circuit.
These two major factors, controllability and observability, play a vital role to test the circuit in stuck-at
fault model.
Controllability and observability can be achieved by the functionality of the combinational circuit and
selection of appropriate test vectors. For a gate-level circuit, the fault can be at an input or output of every
gate and only one line can be detected at a time. These controllability and observability measures give the
actual behavior of the circuit.
Fault coverage for a test vector of the circuit measured using stuck-at fault model is given as follows:

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Number of stuck-at faults detected by test vector / 2 * (number of nets/wires) in the circuit
Example: For the given circuit (Figure 5.3), there are 12 fault sites to be tested and 24 single stuck-at faults.
The total number of fault sites for any Boolean circuit represented in gates is computed as follows:2 * Total
number of wires (primary inputs + primary outputs + internal wires).
The faults identified in Figure 5.3 are represented with an x mark:

Figure 5.3: Displaying the Faults by using an X Mark

The Transistor Open and Short Faults ModelMOS transistor switch is considered as a model to detect the
faults at transistor level. Stuck-open and stuck-short are two types of faults that are modeled to detect the
faults at transistor level.
Stuck-open fault means that the switch is permanently stuck in the open state.
Detection of stuck-open fault requires only two-vectors.
On the other hand, stuck-short fault occurs due to the short of its gate voltage and it is detected by
measuring the quiescent current.
In summary, a set of test vectors determines the inherent fabrication defects. There is a need for quick
method to sort out the bad and good chips in VLSI industry. More exhaustive search is required to avoid
the faulty chips. Fault simulation is used to determine how complete the test vectors are.

Technology Options
After the circuit is synthesized and verified during the physical implementation stage, the next step is to
fabricate the design onto a Silicon chip. Various options exist for creating the physical realization of a
digital circuit onto a Silicon chip. The two major options to fabricate the chip from the circuit level to the
physical realization are full-custom design and semi-custom design.

Full-Custom Design
A designer can handcraft all the digital circuits, such that it gives the possibility to use special circuit styles
and arbitrary sizing of transistors. Designer has the flexibility to choose the logic. This was the approach
followed in early days of digital design era. In this design methodology, large number of logic gates was

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available to a designer where the function and layout of every transistor was customized and optimized
by the designer.
Intel 4004 microprocessor and memory chips are some of the examples of full-custom designs.
Following are the advantages of full-custom designs:
1. High Performance can be achieved since the design can be created from scratch
2. Minimum area can be achieved
3. Maximum speed can be achieved
Following are the disadvantages of full-custom designs:
1. Requires great number of staff and labor
2. High cost and long time to market
3. High cost to design
4. Long time for verification

Semi-Custom Design
In the present day VLSI design era, alternative to full-custom design is semi-custom design method. Semi
means part of the design can be fixed with standard logic, so that each of these modules can be reused in
other designs based on the applications. This approach has shown better results in terms of design time,
cost, and effort. Through automation process, programmability is been achieved which in turn reduce the
design time drastically. Various approaches used to divide the complete design into modules that may be
reused by other designs are as shown in Figure 5.4:

Figure 5.4: Displaying the Classification of Semi-Custom Design

Let’s now learn about the various approaches used in semi-custom design.

Cell-Based Designs
In this process of design methodology, a logic element implemented by a circuit consists of one or more
primitive gates (AND, OR, and NOT) and universal gates (NAND and NOR). Some additional logic
elements (XOR and XNOR), sequential elements (flip-flops), and complex functions (AND-OR-INVERT,

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Multiplexer, Full adder, Comparator, Counter, Decoder, and Encoder) are also included that can be reused
by other designers. These cells are designed, verified, and optimized once, and can be reused many a
times. This reuse property reduces the design cost and time to market tremendously.
Challenging task in this type of cell-based design is to choose the cells and group them to meet the desired
objective. This complexity in library composition may affect area, delay, power consumption, and
dissipation of the circuit.
Following are the advantages of cell-based design:
1. It minimizes the design effort time due to reusable property
2. Pre-designed cells reduce the complexity of the circuit
Following are the disadvantages of cell-based design:
1. Fixed logic elements in library
2. It reduces the possibility of 100% designer’s choice based on objectives
3. Fan-out and fan-in are not known in advance
In general, cell-based designs are divided into three categories:
1. Standard cell-based designs
2. Compiled cell-based designs
3. Macro cell-based designs
Let’s now learn about these categories in brief.
 Standard Cell-Based Design—In a standard cell-based design, logic cells are placed in rows that are
separated by interconnections (or routing channels). Each logic cell can be of different size due to fan-
in variations of the cell. When the cells are placed in a row, cells placed in a row must be of same
height, but with different widths. To make connections among the cells that are placed in a row,
routing channels are used. In the standard cell-based design method, interconnection overhead is the
major issue to be addressed.
 Compiled Cell-Based Design—In a compiled cell-based design, designers have a choice of
customizing and optimizing the cells. A software library tool generates the cells as a function of user
supplied parameters. These generated cells are placed on cell architecture with predefined technology
rules, such as cell size parameters, power budget, routing style, and contact method.
 Macro Cell-Based Design—In this method, macro cells are pre-designed complex designs, such as
multipliers, data paths, memories, and DSPs, and embedded microprocessors. The functionality and
routing within the module is fixed or flexible.

Array-Based Designs
Array-based designs are alternative of cell-based designs. In cell-based designs, the complete process
of fabrication is required, which leads to the delay in introducing the product to the market. On the other
hand, dedication process of fabrication is avoided in array-based designs, which reduces the non-recurring
engineering cost. These designs fall into the following two categories:
 Pre-diffused—In this array-based design, array of primitive cells or transistors are manufactured by
the vendor. All the fabrication steps needed to make these primitive cells are standardized and
optimized irrespective of applications. Desired interconnections can be added with only a few
metallization steps. The example of pre-diffused category is Mask Programmable Gate Arrays.
 Pre-wired—In this array-based design, all the primitive cells are provided but manufacturing process
is separated from the implementation phase of circuits such that it can be performed at user’s site.
FPGA is an example of pre-wired category.

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Power Calculations
Power–aware designs in modern VLSI chips play a major role on VLSI industry. With the continuing
decrease in size and increase in chip density, impact on power consumption of chip has increased.
Clock frequency is another factor that contributes to the power consumption of VLSI design. In recent
years, various applications, such as portable or battery-powered electronics, are inaccessible to vendors,
due to the tight power constraints; and therefore, it has become a major issue for VLSI designers to design
a power optimized VLSI circuits.
Lowering power consumption in the digital circuits would minimize the packaging and cooling costs,
which in-turn leads to the increase in the life span of a chip. High power dissipation or power
consumption leads to the drop down not only in the performance of chips but also in extreme cases, such
as burnouts and damage to circuits. Therefore, extensive researches have been directed towards low
power VLSI circuits.
Power issues in VLSI circuits are addressed in two different aspects: one is to decrease the power
consumption of the VLSI circuits by reducing the logic density and second is to estimate the power
dissipation of the circuit in the early design cycle where the target device can be either ASIC or FPGA.
Let’s now learn about the major sources involved in calculating the power consumption and power
dissipation in VLSI circuits.
 To calculate the total power consumption in the digital circuit, one should have the knowledge of
sources involved for power consumption in VLSI circuits. The primary sources of power in VLSI
circuits are as follows: Static powerShort circuit current
 Dynamic power
 Inductance and resistance of wires
The major contributions to total power consumption in VLSI circuits are static and dynamic power.
Static power, also referred as leakage power, is consumed when a logic circuit is in a quiescent or idle
state. The idle state means without functioning or operating the circuit.
Dynamic power is consumed due to signal transitions in the circuit, that is, switching from 0 → 1 or 1 → 0.
In well-designed circuits, short-circuit current typically represents only 5-10% of dynamic power. There
are two types of signal transitions, given as follows:
 Functional transitions—Transitions necessary to perform the required logic functions
 Spurious transitions or glitch—Unnecessary signal transition due to the unbalanced path delays to
the input signals of a gate
All the sources of power can be accurately estimated or predicted except the dynamic power because it
depends on the functionality of the circuit and the input vectors that are applied to it. Dynamic power
dissipation or consumption occurs because of switching activity in the circuit. This switching activity is
due to the charging or discharging of the load capacitances.
The power estimation in FPGA designs are calculated by estimating the dynamic power dissipation of the
circuits that are mapped onto FPGA such that the average power consumption of circuits can be estimated
before the fabrication of FPGA to identify the possible power violations during the design process.
Therefore, power estimation is required across the various levels in the design hierarchy to effectively
control and reduce the power consumption of the end product mapped onto the target device.

Package Selection
After the successful completion of verification process, the next step is to place the design onto a board.
Chip package plays a vital role in chip manufacturing, in which the chip resides for plugging into or
soldering onto the printed circuit board. We face the challenge of how to package the monster chips, as we

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approach the scenario of having hundreds of millions of transistors, thousands of inputs and outputs, and
hundreds of watts of power on a chip.
 Package selection is another major issue that affects the physical design of the circuit. The selection of
the package is based on a number of factors, such as die size, price, chip input, output pins, and
power consumption. The major challenges in package selection are as follows: How to minimize the
signal distortion introduced by the package
 How to package the chip efficiently
 How to reduce the footprint of the package
The multiple stacked-die System-in-Package (SiP) method is an alternative to the System-On-Chip (SoC)
approach. This is also known as the Multi-Chip Module (MCM).
Traditionally, the system could be constructed using discrete components of individual packages. The SoC
approach packs the multiple dies into one package. These multiple dies are internally connected either by
fine wires that are buried in the package or by using solder bumps to join the stacked chips together.

Clock Mechanisms
A mechanism known as clock allows hardware to operate without requiring the input to change. All the
digital circuits are said to be clocked, which implies that all the components of digital circuit ensure that
they work together. In other words, they are synchronized to do an intended task.
A clock is a mechanism that emits an alternating sequence of logic 0 and logic 1 at a regular interval of
time. The speed of the clock is measured as Hertz (number of clock cycles per second). A clock is an
electrical signal that oscillates between a high state and a low state. It is usually a square wave with a
predetermined period, as shown in Figure 5.5:

Figure 5.5: Displaying the Clock Pulse

The timing factor is an important aspect that the designers must consider while designing the circuit, as
the components of the circuit takes time to settle (time to change the output once the input changes). For
example, a basic AND gate takes time to change the output once the input changes. As VLSI circuits
operate at high speed, designers must keep in mind the two factors. One is to calculate the time required
for all the components to settle and second is the time required to reach the clock to the component (i.e.,
the length of the wire between the clock and a given circuit component). Figure 5.6 shows a sequential
circuit designed with D flip-flops and a common clock signal:

Figure 5.6: Displaying the Clock Skew within the Component

In Figure 5.6, you can observe that the time to reach clock signal to the first D flip-flop is not the same as
the time to reach the last D flip-flop. Similarly, the difference can be observed from one chip to another, as
shown in Figure 5.7:

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Figure 5.7: Displaying the Clock Skew from Chip-to-Chip

In synchronous digital circuits, the clock signals coordinate the actions of all the circuit components on a
chip. For example, if a clock is positive edge-triggered, then the components of a chip trigger whenever the
clock is at logic 1; whereas, if it is negative edge-triggered, then the components trigger at logic 0. In other
words, the components become active at either the rising edge (positive-triggered clock), the falling edge
(negative-triggered clock), or both the edges of the clock signal for synchronization.
Synchronizing is a most important task in timekeeping that requires the coordination of events to achieve
the desired functions. During the process of synchronization, for some applications, relative timing offsets
between events must be known or determined prior its usage. The synchronous design principle can
significantly simplify the implementation task in a chip design.
In today’s VLSI chip design environment, most integrated circuits of sufficient complexity require clock
signals to synchronize different parts of the chip and to account for propagation delays.
As chips get more complex and clock speeds approach the gigahertz range, the task of supplying accurate
and synchronized clocks to all the components become tedious.
Clock skew is the difference in clock signal arrival times across the chip. Clocking sequentially-adjacent
registers on the same edge of a clock can potentially cause timing violations or even functional failures.
Figure 5.6 and Figure 5.7 clearly show that clock skew is apparent. This also shows that routing is also one
of the factors for clock skew.
Following are the steps to resolve the clock skew problem:
 Measure the clock skew of the design before fabrication of chip
 Perform static timing analysis of the design after place and route to determine the amount of clock
skew
 Minimize the clock skew
The following two methodologies are developed to avoid clock skew issues:
1. Clocking on alternate edges
2. Clocking with two phases
Clocking on alternate edges can be given for each component, as shown in Figure 5.8:

Figure 5.8: Displaying the Clocking on Alternate Edges

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 VLSI Design Issues

In Figure 5.8, first D flip-flop is provided with positive edge-triggered clock and another is provided with
negative edge-triggered clock. This can be extended for any number of components. Another solution to
minimize the clock skew is to provide multiple clocks. As global clock for large systems gives rise to clock
skews, several clocks are used with each clock controlling one part of the system. In particular, clocks that
run at highest rates are used in small physical areas. Though multiple clocks solve the problem of clock
skew, clock synchronization problem arises for large systems. This is an open issue for VLSI designers.

Mixed Signal Design

In day-to-day applications, demand for digital signal processing of data is increasing tremendously due to
increase in performance of digital systems. This raises the demand for mixed signal designs to interface
with analog and digital world. Therefore, semiconductor industries are trying to integrate functionality of
both the worlds onto a single Silicon chip.
Mixed signal designs have both analog and digital systems combined, where the functionality of the
systems relies on both the systems. The most common building blocks of analog and mixed signal designs
are Analog-to-Digital Converter (ADC), Digital-to-Analog Converter (DAC), Phase Locked Loop (PLL),
Operational Amplifiers (OPAMP), and Digital Signal Processors (DSP).
The mixed signal design is shown in Figure 5.9:

Figure 5.9: Displaying the Mixed Signal Design

In Figure 5.9, the analog data is taken as an input and is converted to digital data to process the
computation. It then releases the digital output, which in turn converts into analog output. Advantages of
mixed signal designs are lower cost, fewer devices with minimum area, and flexibility with analog and
digital components.
The issues in designing mixed signal systems are as follows:
1. Compatibility in speed of both analog and digital systems
2. High level integration
3. Low cost and low power
4. High accuracy
5. To suppress phase noise
6. High switching speed
7. Optimum conversions capabilities with least power dissipation
The design flow for mixed design systems is shown in Figure 5.10:

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Figure 5.10: Displaying the Ideal Design Flow for Mixed Signal Design
Design flow of mixed signal designs is not well structured as digital systems. Reason behind this design
flow is that digital systems are compatible with the top down approach; whereas, analog designs are
compatible with the bottom up approach. The ideal flow of design process is shown in Figure 5.10. The
digital components are simulated with digital simulators; whereas, analog simulators are simulated with
analog components. Combined top-level designs are simulated and synthesized at the synthesis stage and
finally to the physical design process.

Summary
In this chapter, the process of verification at physical level design is been discussed in detail. Verification
is a process of identification of faults in the systems. Faults in a system lead to failures of the chip. In
general, faults occur due to power failures or short circuits. Functional faults, memory faults, transistor
faults, and analog faults are some of the faults occur in VLSI systems. Fault models are developed to detect
faults. Single stuck-at fault model is one of the fault models to detect functional faults. Design for
testability is a process to design a set of models to detect the faulty chips based on functional behavioral.
Fault coverage factor determines the quality of the design for testability process to detect the faults. Full-
custom and semi-custom designs are the two major technology options to fabricate the design onto Silicon.
Full-custom designs are suitable for microprocessors; whereas, semi-custom designs are used for
designing embedded processors. Clock mechanism, power calculations, and package selection are other
important criteria to design reliable chips. Power calculations give input for package selection based on
cooling capacity requirements. Finally, mixed signal design systems and ideal design flow is been
discussed in this chapter.

Review Questions
1. Write the differences between faults and fault coverage.
2. Explain the stuck-at fault model with example.
3. Define controllability and observability.
4. Design a procedure to detect the untestable faults.
5. Explain any method to minimize the clock skew in digital systems.
6. What is dynamic power and static power?
7. Write a procedure to estimate the total number of toggles of a XOR gate using NAND realization in a
cycle.
8. Write the advantages and disadvantages of cell-based and array -based designs.
9. Give two reasons about the importance of package selections.
10. Write the differences between detectable and undetectable faults.

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 6
EDA Tools: An Overview
If you need information on: See page:
EDA 76
Architecture Design 79
Design Entry 81
Synthesis Tools: XST, Synplify, and Leonardo Spectrum 83
Functional Verification 97
Timing Verification 99
On-Chip Debugging 99
Chapter 6

To achieve large-scale integration, the importance of tools cannot be overemphasized. The ultimate
objective of tools is to automate the entire design process. Of course, we are nowhere near achieving this
ultimate objective, but certainly, the present available tools are sophisticated enough to represent the
design of a system at an abstract level (block diagrams level) or using Hardware Description Language
(HDL). The tools that help in converting this representation of the design into the chips are the Electronic
Design Automation (EDA) tools. In this chapter, an overview of some of the popular EDA tools is given.
As there is a good demand for such tools, a very large number of tools are available in the market. This
chapter is an attempt to describe some tools that help in understanding the role of tools in chip design.

EDA
With the advent of advanced technologies, shrinking size of transistor leads to an extent where millions of
transistors can be built on a single integrated chip. Design of Very Large Scale Integration (VLSI) circuits
with very complex combinational or sequential circuits is made easy to integrate on a single chip. Due to
the complexity involved in these circuits, the manual process of designing, testing, and verification of the
designed circuits on breadboard has become a tough task. Therefore, designers felt the necessity to
automate the design flow of logic circuits. EDA or Computer Aided Design (CAD) tools are evolved to
automate the process of design flow for electronic circuits. EDA is a software tool used to provide the
automation procedure to design and verify circuits.
Till 1960s, circuits were drawn manually on drafting boards. During 1960s to 1970s, CAD was used to
create the schematics (layout of the circuit) and analyze the functionality of designs. During 1980’s, CAD
or EDA tools were introduced for designing complex electronic circuits. EDA for electronics has rapidly
gained importance with the enhancements in technology.
Several companies that specialize in EDA tools are Cadence Design Systems, Magma Design Automation,
Synopsis, Mentor Graphics, and Xilinx. These tools perform the logic optimization and functional
verification (logic synthesis). In addition, these tools help in transform the synthesized netlist to an
equivalent hardware implementation file for an Application Specific Integrated Circuit (ASIC) or Field
Programmable Gate Array (FPGA).
Some of the leading software vendors for EDA tools are given as follows:
 Altera
 Magma Design Automation
 Mentor Graphics
 Microwind
 Synplicity
In addition to these commercial tools, various open source tools are used extensively in the academic
institutions.

Taxonomy of Tools
The tools, broadly categorized based on the flow of design process, are given as follows:
 Front-end tools
 Back-end tools

Front–End Tools
The steps involved in designing with the help of flow diagram for the required logic are shown in
Figure 6.1:

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 EDA Tools: An Overview

Figure 6.1: Displaying the Front-End Design

These steps are sequential and considered as a front-end process. The tools that support these front-end
process steps are considered as front-end tools. The detailed description of the stages in the design is listed
as follows:
1. Specification—The functionality, interface, and overall architecture description is given in this step.
2. Behavioral description—Based on the specifications, behavioral description of a circuit is written in
any Hardware Description Language (HDL), such as Verilog and VHDL, considering all the
requirements, such as input, output, and connectivity, among the variables.
3. Functional verification—After the behavior of the circuit is defined, the circuit is to be verified by
giving the input values. In the functional verification stage, the behavior of the designed circuit is
verified using a set of input test vectors.
4. Synthesis—Synthesis is a process of translating the HDL code into a circuit, that is, gate level netlist.
This netlist is the schematic of the circuit designed using gates and flip-flops.
5. Static timing analysis—This step is considered to verify the critical path delay of the designed circuit.
The critical path delay is defined as the time taken to pass the signal value from primary input to
primary output. The path delay is estimated statically in this stage of the design process.
Major vendors and their front-end tools available in commercial market are listed as follows:
1. Cadence Systems—NV Verilog and Verilog-XL are functional simulators that act as front-end tools
2. Synopsis—VCS and VHDL simulators perform the functional and timing verification of a circuit
3. Altera—Quartus II A-HDL is a front-end simulator that performs functional simulation
4. Mentor Graphics—Model Sim, QuestaSim, and NCsim are used for functional simulation and timing
verification of FPGA circuits
5. Xilinx—Integrated Simulator Environment (ISE) simulator is used for functional verification of
FPGAs

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Back-End Tools
The back-end process takes place after the synthesis step successfully completes the design process. The
steps in the process of back-end design are shown in Figure 6.2:

Figure 6.2: Displaying the Back–End Design

The functionality of each step is described as follows:
1. Layout design—After the circuit design is functionally verified, it is necessary to provide an area
efficient layout of the circuit to generate the masks for fabrication.
In this step, automation procedure for layout design takes place to meet the area constraints, such as
chip size and density.
2. Placement and routing—In this phase, the logic components of the design are placed in predefined
locations and checked for the area constraints. After the area constraints meet the requirements, the
actual connection establishes and estimates the wire length. This phase is one of the most important
phases that help in identifying the circuit delay constraints.
3. Mask preparation—During this phase, the chip layout is generated and fabricated onto a chip. It is
also called the packaging phase for chip level designs and layout phase for board level designs.
The final output of the back-end process is sent to the fab for fabrication and packaging of the chip.
The back-end design is called physical design and the front-end design is called logical design. Some of
the major tools associated with back-end task and its vendors are listed as follows:
1. Cadence—CTgen back-end tool for ASIC
2. Synopsis—Design Compiler and Test Compiler are back-end design tools for ASIC and FPGA
3. Magma Design Automation—Back-end tool for ASIC designs
4. Leonardo Spectrum—Synthesis tool for ASIC designs
5. Leonardo Insight—Performance analysis and debugging for ASIC design
5. Mentor Graphics—MaXPlus tool for FPGA designs
6. Xilinx XST—Synthesis, implementation (translation, mapping, place, and route), and bit file
generation for FPGA designs

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7. Altera Quartus—Both front-end and back-end tools for FPGA design

Some of the major EDA tools and their features are explained briefly in the next section.

Altera’s Quartus II Software

Altera’s Quartus II software is for designing high-density FPGAs. It provides advanced features that are
given as follows:
 RTL viewer—VHDL and Verilog designs can be used to analyze design structure and then carry out
simulation, synthesis, and place and route
 Chip editor—Using this editor, Altera devices are used to edit incrementally to identify the resource
functionality and parameter settings
 Signal Tap II Advanced Triggering—This feature is used to implement user-defined trigger logic to
compare bus states and individual signals to these buses
 Logic block-based design methodologies—This feature is used to design and implement sub-
modules independently for the given design

Microwind Tools
Microwind Inc. (www.microwind.net), based in France, has a set of powerful tools for both front-end and
back-end for VLSI design. These tools include features that are listed as follows:
 The front-end tool, DSCH, is a schematic editor and a simulator used to generate an equivalent
Verilog Register Transfer Language (RTL) code description for the given schematic in the layout
editor
 VirtuosoFab is a three-dimensional (3D) fabrication process simulator with cross sectional viewer
feature
 MEMsim is a simulator that simulates the non-volatile memory (EPROM, EEPROM, and Flash)
 PROthumb is used for mixed signal simulation and analysis of the design

Xilinx Tools
Xilinx Inc. (www.xilinx.com) has a set of tools for simulation, synthesis, and power estimation for VLSI
designs. These tools also include front-end and back-end tools for FPGA design, on-chip verification tool,
and timing analysis tool for both ASIC and FPGA designs. Some of the Xilinx tools are given as follows:
1. ISE® Simulator—It provides a complete, full-featured HDL simulator.
2. XST Synthesis—It provides the simulation, placement and route, and bit generation stream for FPGA
and ASIC designs.
3. PlanAhead Design and Analysis—It provides timing analysis of the designed circuit, structure of the
components, and wiring between the components and enables the routing feature.

Architecture Design
The major challenges to design a digital system are that it must execute the desired function and meet the
area, performance, and timing constraints. During the design process, modeling is an important aspect to
meet the required specifications. The HDLs allow designing any digital systems using RTL at various
levels of abstraction. The two major approaches followed in the process of design flow are top-down
approach and bottom-up approach.

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Top-Down Design
This is one of the approaches to design any digital system from simple to complex design. The design
starts at the highest level of a design concept as specifications, algorithm, and implementation using HDL
and proceeds towards the lowest level, that is, gate level netlist.
The top-down design methodology takes the HDL model of hardware as an abstract level input. The
design steps down until gate or transistor level of the circuit. Figure 6.3 represents the top-down design
flow for electronic hardware component:

Figure 6.3: Displaying the Top-Down Design Flow Environment

The first level is the system specification followed by algorithm and architecture specifications. The step
followed by the architecture is HDL model, which is hardware model of the design represented in RTL.
The RTL model is synthesized to gate-level netlist and then to transistor level netlist. This approach is best
suitable to design complex designs, such as very large integrated circuits.
Advantages of this approach are as follows:
1. Ease of design modifications
2. Verification can be done at every stage
3. Validation of the design takes place at every stage of design, such as RTL level, gate-level, layout
level, and placement and route, to meet the design requirements

Bottom-Up Design
This design approach is a traditional method of electronic design. Each design is performed at gate level
using standard gates. The basic logic units, such as primitive gates, adders, and registers, are designed as a
first step in the design process. These are combined to create designs that are more complex. This
approach is best suitable for small projects, such as arithmetic logic unit, parallel adder, and Wallace tree
multiplier. As the complexity of circuit increases, this approach is not suitable. For example, 64-bit
microprocessor is difficult to design using the bottom-up design approach, as there are large numbers of
complex designs to be designed using existing logical components.

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Advantages and disadvantages of the bottom-up design approach are:

1. Easy to design small circuits
2. Easy to understand the flow of logic components
3. Difficult to implement for large designs, such as microprocessors
Nowadays, a combination of both top-down and bottom-up design approaches is followed to design
complex circuits.

Design Entry
The purpose of design entry is to describe the digital electronic systems to EDA tools.
During the design entry stage, designers have several options for the selection of tool to enter the design
specifications, to simulate and synthesize using EDA tools. The purpose of these design entry tools are
given as follows:
1. To reduce the effort to enter the design specifications as input to EDA tool
2. To reduce the size and cost of the system
3. To estimate the power parameters, such as power consumptionTo increase the productivity of the
electronic systems
4. To increase the reliability
After the design specifications are ready, a design entry tool is selected to enter the design into an
automation tool to analyze the functionality of the circuit. Some of the popular automation tools used to
enter the design are listed as follows:
1. Schematic editor
2. VHDL editor
3. Verilog editor
4. Block editor
5. Third party editor
Let’s discuss the features of these editors in detail.

Schematic Editor
Schematic editor is a drawing tool editor that provides the following features:
1. It shows the connectivity of all the components of a design
2. All the components are created using built-in objects, and connectivity between them is established
using nets
3. Nets are represented as a direction line, which is used to show the interconnections of a design
4. Netlist is generated for the given schematic as input to the schematic editor
5. All the components in a design and their interconnections are either in the binary or American
Standard Code for Information Interchange (ASCII) format
6. The complex components can be arranged in the following two ways:
a. Hierarchical design
b. Flat design
Hierarchical design of 4x1 multiplexer is shown in Figure 6.4:

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Figure 6.4
Flat design of 4x1 and 2 X 1 multiplexer is shown in Figure 6.5:
Figure 6.5 Flat design of 2x1 Multiplexer and 4XI Multiplexer

Figure 6.5

VHDL Editor/Verilog Editor

The VHDL or Verilog is a text editor tool for entering text-based designs in VHDL or Verilog HDL
languages. This text editor is used to edit, enter, and view the files in the ASCII text format. The text editor
also allows you to insert a template for any HDL statement or section. The VHDL and Verilog HDL
templates provide an easy way to enter HDL syntax that in turn increases the speed and accuracy of
design entry.

Block Editor
The block editor tool provides features to enter and edit schematics. This editor reads and edits block
design files. Each block design file contains blocks and symbols that represent logic in the design. This
editor also incorporates the design logic represented by each block diagram, schematic, or symbol into the
project. The block editor helps in connecting blocks and primitives that include both data path connections
and mapping signals.

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Synthesis Tools: XST, Synplify, and Leonardo Spectrum

After the specification is completed using any design entry tool, the design is entered and parsed for
syntax errors. Then, the design is minimized and optimized for the target architecture based on the
specification. The next step of the front-end design is to convert all the structural elements by library
elements, that is, Look Up Table (LUT) or slices in case of FPGA; whereas, library cells for ASICs. The final
step is to convert the design into netlist format with estimated timing and resource requirements.
In this section, the flow of front-end process is illustrated with snapshots taken from the Xilinx simulator
and the synthesis tool. Xilinx is an open source simulator; whereas, the synthesis tool is mainly used by
academic institutions for research and development projects. Xilinx ISE is an integrated simulation
environment tool for simulation and synthesis of a design.

Creating a new Project using the Xilinx Project Navigator

To open the Xilinx ISE Project Navigator, double-click the shortcut Xilinx ISE 8.2i on the Desktop or select
StartProgramsXilinx ISE 8.2i Project Navigator from the Start menu.
The main screen of the Xilinx ISE Project Navigator appears, as shown in Figure 6.6:

Figure 6.6: Displaying the Xilinx ISE Project Navigator

Perform the following steps to create a new ISE project:
1. Select File  New Project. The New Project Wizard– Create New Project window appears, as shown
in Figure 6.7:

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Figure 6.7: Displaying the New Project Wizard – Create New Project Window
2. Type a name for the project in the Project Name field.
3. Browse to a location or enter a location (directory path) for the new project in the Project Location
field.
4. Select an option from the Top-Level Source Type list. In our case, we have selected HDL.
The options in the Top-Level Source Type list are as follows:
i. HDL—Choose this option for VHDL / Verilog
ii. Schematics—Choose this option to work on Schematics
iii. EDIF—Choose this option to skip project navigator synthesis process and to start the
implementation process
iv. NGC/NGO—Choose this option to skip project navigator synthesis process and to start the
implementation process
5. Click the Next button to open the New Project Wizard – Device Properties window, as shown in
Figure 6.8:

Figure 6.8: Displaying the New Project Wizard – Device Properties Window
6. Enter the values in the Device Properties table as follows:
 Product Category: All

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 Family: Vertex4
 Device: XC4VFX12
 Package: SF363
 Speed: -10
 Top-Level Source Type: HDL
 Synthesis Tool: XST (VHDL/Verilog)
 Simulator: Modelsim-SE VHDL
7. Select the Enable Enhanced Design Summary checkbox.
8. Click the Next button to proceed. The New Project Wizard – Create New Source window appears, as
shown in Figure 6.9:

Figure 6.9: Displaying the New Project Wizard – Create New Source Window
9. Click the Next button, as we are using an existing source. The New Project Wizard – Add Existing
Sources window appears, as shown in Figure 6.10:

Figure 6.10: Displaying the New Project Wizard – Add Existing Sources Window

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10. Click the Next button to proceed. The New Project Wizard - Project Summary window appears, as
shown in Figure 6.11:

Figure 6.11: Displaying the New Project Wizard – Project Summary Window
11. Click the Finish button to complete the creation of new project. The New Project Main Screen appears,
as shown in Figure 6.12:

Figure 6.12: Displaying the Project Window after Creating the New Project
Perform the following steps to create VHDL/Verilog source code:
1. Select a device from the Sources tab in the Sources panel. In our case, we have selected XC4VSX35-
10ff668 (Figure 6.12). A pop-up menu appears.
2. Select New Source from the pop-up menu. The New Source Wizard – Select Source Type window
appears (Figure 6.13).

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3. Select VHDL Module as a type of source from the list box and enter the file name of the source code as
Counter in the File name field, as shown in Figure 6.13:

Figure 6.13: Displaying the New Source Wizard – Select Source Type Window
4. Click the Next button. The New Source Wizard – Define Module window appears (Figure 6.14).
5. Declare the ports for the entity (which contains all the inputs and outputs) by filling the port
information, as shown in Figure 6.14:

Figure 6.14: Displaying the New Source Wizard - Define Module Window

You can skip the window if you do not want to declare the entity now.

6. Click the Next button. The New Source Wizard – Summary window appears, as shown in Figure
6.15:

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Figure 6.15: Displaying the New Source Wizard - Summary Window

7. Click the Finish button. The VHDL program structure is displayed in the Main GUI of Xilinx ISE, as
shown in Figure 6.16:

Figure 6.16: Displaying the VHDL Program Structure

8. Write the VHDL code for Counter in the Xilinx main text window (Figure 6.16) and save it by
selecting the Save option in the File menu.

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Listing 1 shows the code for Counter:

Listing 1: Showing the Code for Counter
-------------------------Code for Counter-----------------------------

-- Filename: Counter.vhd
-- Create Date: 01/18/2009
-- Module Name: Counter
-- Project Name: Counter
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 8.1i
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
--library declaration

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--entity Declaration

entity Counter is
Port (c: in STD_LOGIC; --Input
clr: in STD_LOGIC; --Input
q_out: out STD_LOGIC_VECTOR (3 downto 0) --output
);

end Counter;

--architecture Declaration

architecture Behavioral of Counter is

--signal Declaration

signal tmp: STD_LOGIC_VECTOR (3 downto 0);

begin
process(clr,c)
begin

if (clr='1') then

tmp <= "0000";

elsif(c'event and c = '1') then

tmp <= tmp + 1;

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end if;

end process;

q_out <= tmp;

end Behavioral;
Simulation process takes place by selecting the Check Syntax option in the Xilinx XST tool. Perform the
following steps to check the syntax and simulate and synthesize the design:
1. Verify whether the Check Syntax option is available in the Process window (Figure 6.17). After saving
the code, you need to check whether the syntax is correct or not. This is done by using the Check
Syntax option.
2. Right-click the Check Syntax option if it is available. A pop-up menu appears.
3. Select the
4. Run option from the pop-up menu.
5. Select the Synthesize-XST option from the Process window to expand it, if the Check Syntax option
is not available. From the expanded list, select the Check Syntax option.
The Process “Check Syntax" completed successfully message is displayed in the Transcript window if the
architecture behavioral of Counter entity is up to date, as shown in Figure. 6.17:

Figure 6.17: Displaying the Check Syntax Option

If there are errors, modify the code and follow the procedure to keep checking the syntax until the code is error-free.

5. Verify whether the Synthesize-XST option exists in the Process window after getting the Process
"Check Syntax" completed successfully message.
6. Select Synthesize-XST Right-clickRun in the Process window, if the option exists in the window.

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7. Select Source window  Module Name (Counter)  Set as Top Module, if the Synthesize-XST
option does not exist in the Process window. Several options appear as a list in the Process window.
Select the Synthesize-XST option from the list and follow the procedure in the step 6.
The Process "Synthesize" completed successfully message appears in the Transcript window, if the
synthesize step is completed without error, as shown in Figure 6.18:

Figure 6.18: Displaying the Synthesize Step Report

8. Select Processes windowView Design Summary Right-clickRun. This shows the new
window in the Xilinx main window that contains all the design summary of the module (Counter), as
shown in Figure 6.19:

Figure 6.19: Displaying the Design Summary Report

9. Select Synthesize-XST View Synthesize ReportRun after the Process "Synthesize" completed
successfully message appears. This generates a new file called Synthesize Report in the main text
window.

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This file contains the detailed information about the Synthesis Report, Design Hierarchy, HDL
Synthesis Report, Low Level Synthesis, Device Utilization Summary, and Timing Constraints.
10. Select Synthesize-XST RTL SchematicRun to view the RTL Schematic of the module.
The RTL Schematic window appears, as shown in Figure 6.20:

Figure 6.20: Displaying the RTL Schematic View

The RTL Schematic window depends on the module inputs and outputs.
11. Select Module name (Counter) Show Schematic from the Process window, if the RTL window
does not show anything on the main window.
12. Select SourceSchematic-XST--->View Technology SchematicRun to view the View Technology
Schematic. The Technology Schematic appears in the window (Figure 6.21).
13. Double-click any block from the schematic diagram to get the inner schematic of the block, as shown
in Figure 6.21:

Figure 6.21: Displaying the Technology Schematic View of counter.vhd

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14. Select Schematic-XSTGenerate Post-Synthesis Simulation Model Post-Synthesis Simulation

Model ReportRun from the Process window. It will generate the Post -Synthesis Simulation Model
report called Counter_synthesis.nif, as shown in Figure 6.22:

Figure 6.22: Displaying the Post Synthesis Simulation Model

The generated VHDL netlist contains the Xilinx UNISIM simulation primitives that should be used
with the UNISIM library for the correct compilation and simulation.
15. Select Implement Design from the Process table to expand it. Translate is one of the main options of
Implement Design that contains the following important sub-options:
i. Implement Design----->Translate---->Translation Report Run: It will generate a file in the
main text window named as Translation Report, as shown in Figure 6.22:

Figure 6.22: Displaying the Translation Report Window

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ii. Implement Design----->Translate---->Floorplan DesignRun: If this process runs successfully,

then the Process "Floorplan Design" completed successfully message appears in the Transcript
window.
A new pop-up window will appear for the UCF file for the module. If the UCF file exists, select YES;
otherwise, select NO. After selecting the option from YES or NO, a new window appears called Xilinx
Floor planner, which shows the Floor Planner of the module (Counter), as shown in Figure 6.23:

Figure 6.23: Displaying the Floor Planner

iii. Implement Design---> Translate--->Generate Post-Translate Simulation Model----> Post-Translate
Simulation Model ReportRun:
It will generate a file named Counter_translate.nlf in the main text window. The generated file
carry the information about reading design Counter.ngd, flattening design, processing design,
preparing design's networks, and preparing design's macros.
The process will assign Package Pins for a module according to the data sheet of the module by
selecting the option from Implement Design.
The second main option in Implement Design is Map. It contains several sub-options, such as Map Report
and Generate Post-Map Static Timing.
For Map Report, the process generates a file named Map Report for the module (Counter), as shown in
Figure 6.24:

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Figure 6.24: Displaying the Map Report

The generated file lists the information about the parameters as design information, design summary with
errors, warnings, input and output buffer properties, and timing report.
After the selection of the second option of Map menu as Generate Post-Map Static timing, the Process
"Generate Post-Map Static Timing" completed successfully message is displayed in the Transcript
window, if the process is completed successfully. You can also select the Analyze Post-Map Static Timing
option as a sub-option of the Generate Post-Map Static Timing option. Right-click the option and select
Run from the pop-up menu. If the process is completed successfully, the Process "Analyze Post-Map
Static Timing" completed successfully message appears in the Transcript window.
The third option in the Map menu is Floor plan Design Post-Map (Floor planner). After the successful
completion of this process, the Process "Floor plan Design Post-Map (Floor planner)" completed
successfully message is displayed on the Transcript window.
Another option in the Map menu is Generate Post-Map Simulation Model. You can right- click it and
select the Run option from the pop-up menu. If the process is completed successfully, the Process
"Generate Post-Map Simulation Model" completed successfully message is displayed in the Transcript
window. The process will generate a file in the main text window named Counter_map.nlf, which
contains the information version 3.1, device xc4vfx12, package sf363, and speed –10 loading constraints
from Counter.pcf.
The speed grade (-10) differs from the speed grade specified in the .ncd file. The number of routable
networks is 14.
The third option in the Implement Design menu is Place and Route. Generate Post-Place & Route Static
Timing is the first option in the Place and Route menu.
If the process is completed successfully, then the Process "Generate Post-Place & Route Static Timing"
completed successfully message will appear in the Transcript window. It will generate a file in the main
text window named Place and Route Report for the model. Place and Route will run in Performance
Evaluation Mode to improve the performance automatically of all the internal clocks in this design. The
PAR-timing summary will list the performance achieved for each clock.

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For the fastest runtime, set the effort level to std; for the best performance, set the effort level to high; and for a balance
between the fastest runtime and the best performance, set the effort level to med.

The second option in the Place and Route menu is Clock Region Report. If the process is completed
successfully, then the Process "Clock Region Report" completed successfully message appears in the
Transcript window. It will generate a file in the main text window named Clock Region Report for the
module. The generated file contains all the information about Clock Reports by Clock Regions.
The third option in the Place and Route menu is Asynchronous Delay Report. If the process is completed
successfully, then the Process "Asynchronous Delay Report" completed successfully message appears in
the Transcript window. It will generate the file in the main text window named Asynchronous Delay
Report for the module. The file contains all the information about the delay parameters. For the Counter
module, the results are the 20 worst nets by delay.
The fourth option in the Place and Route menu is Pad Reports. It will generate a file in the main text
window named Counter_pad.txt for the module. The generated file contains the information about
Pin Number, Signal Name, Pin Usage, Pin Name, Direction, IO Standard, IO Bank Number, Drive
(mA),Slew Rate, Termination, IOB Delay, Voltage, Constraint, DCI Value, IO Register, and Signal
Integrity.
The important option in the Place and Route menu is Analyze Power of the designed circuit. The process
is started as Implement Design ---> Place and Route--->Analyze Power (XPower)--->Right click-----
>Run. If the process is completed successfully, then the Process "Analyze Power (XPower)" completed
successfully message appears in the Transcript window and it generates a new window of Xilinx XPower.
The Xilinx XPower window contains all the information regarding the values, such as Voltage(V),
Current(mA), Power(mW), Data Types, and Report views, as shown in Figure 6.25:

Figure 6.25: Displaying the Xilinx XPower Window to Analyze the Power
The Power Report can be generated using an option in the menu of Place and Route as Implement Design
---> Place and Route--->View XPower Report----->Right click--->Run. If the process is completed
successfully, then it will generate a report named Power Report of the module regarding the power
summary and the temperature summary in the main text window of Xilinx, as shown in Figure 6.26:

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Figure 6.26: Displaying the XPower Report

Functional Verification
EDA refers to a set of computer programs used to facilitate the design and physical realization of
electronic circuits. Typically, this can be done on a chip or Printed Circuit Board (PCB), and involves
layout, verification, and performance simulation of electronic circuits. The most important factor in these
tools is the verification process. Verification is a process of examining the behavior of the implementation.
In other words, verification implies pre-silicon testing, that is, functional verification of Verilog or VHDL
RTL code. Functional verification is essential in the development of complex digital design. To verify
whether the chip is functionally correct, exhaustive check is required to ensure the correct behavior. As the
complexity of the circuit increases, the search state space increases. To overcome this, verification process
takes place for sub-components of chip and finally, stitched these components after the completion of
verification process for all its sub-components.
Standard procedure of verification is done at each level of the design. The various levels at which the
verification is done are system level, abstract level, and board or chip level testing. Functional verification
and equivalence checking are the systematic procedures to verify the design at abstract level.
General procedure of verification is done at each level of the design. The components at abstraction level
are verified with the functional behavior with the set of data inputs. The datasets, also called stimulus, are
applied to design and verify the functional behavior with respect to the given specifications.
The major challenges in verification process are as follows:
 Total amount of space
 Detection of incorrect behavior
 Reference model to verify the design
 Parameters to measure functional coverage
EDA tools are used to design automatic test pattern generators called functional verification tools. These
tools generate the test vectors to perform the logic simulation of the circuit. Two types of verification
methods are used: black box verification and white box verification. The black box verification method
includes Simulation and Emulation; whereas, the white box verification method is used for formal
verification called Assertion-based Verification.

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Black Box Verification

In this verification method, the test vectors (or stimulus) are applied to the input pins of a design and they
verify the results at output pins with the expected behavior of the design.
The test vectors are applied to a design and they verify the functional behavior with respect to the given
specifications. Depending on the logic, the input test vectors are generated. These test vectors are applied
to the design and the behavior of the design is observed over a number of clock cycles. The state of the
design for each input test vector is tested and verified with the expected behavior or golden reference
model. Figure 6.27 shows a block diagram of combinational circuit whose input pins are a, b, and c and
output pins are d, and e:

Figure 6.27: Displaying the Combinational Circuit

As the circuit complexity increases, input test pattern generation time increases, which in turn increases
the search space. To overcome this, random test pattern generation is introduced to reduce the search
space.
Major issue in random generation is that coverage area of the design becomes an unbounded problem.
Therefore, automatic test pattern generator is used to generate the random test vectors and compute the
coverage area.
For example, consider two circuits, full adder and parallel adder. The functional verification is carried out
by generating test vectors. The test vectors to verify these circuits are discussed in the following two
examples.
Example 1: Full Adder The three-bit input test vector is given to verify the behavior of the circuit for
all the eight combinations as 000,001,010,011,100,101,110,111.
Example 2: 4-Bit Parallel Adder For the 4-bit parallel adder, the test vector must be two 4-bit numbers.
Total number of test vectors required to test the circuit is 16 combinations with other 16 combinations, that
is, 0000 with all 16 combinations.
The test vectors for the parallel adder are listed as follows:
0000 + 0000
0000 + 0001
0000 + 0010
0000 + 0011
Similarly, for other combinations, such as 0001, 0010, 0011,………1111, total number of test patterns to be
generated is n.2n. Therefore, the total number of input test vectors is required based on the number of
inputs and functionality of the circuit. As the input parameters of a circuit increase, the complexity
increases. Another major drawback is that if a failure occurs inside the design, then it might propagate to
the output pins. Such cases cannot be identified using the black box verification method.

White Box Verification

In this method, the internal components of the design are verified thoroughly with the help of assertions.
The assertions are monitors included in the circuit at every stage of internal wires and components. These
assertions increase the observability, which in turn increases the quality of the design. In case of RTL

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designs, the assertion notifies to designers at the end of design process. This report helps to re-design the
process to ensure the correctness of the circuit.
Some of the commercial verification tools available in the market are as follows:
i. Verilog–XL—It is a compiler and functional simulator for Verilog code
ii. NC-Verilog—It is a compiler and functional simulator for Verilog code
iii. VCS tool—It is a fastest compiler and functional simulator for Verilog RTL code
iv. Modelsim—It supports systemC, Verilog, SystemVerilog, and VHDL
v. Specman—This simulator is for ‘e’ Hardware Verification Language (HVL)
vi. Vera—This simulator is for VERA HVL

Timing Verification
Timing verification is the process of determining that a given design can be operated at a specific clock
frequency without errors. In other words, timing verification determines whether timing requirements are
being met to ascertain the absence of timing violations, such as setup time, hold time, inertial delay, and
transport delay. For example, if the data input of a latch arrives after closing the edge of the clock or if the
data input changes before the closing edge of previous clock, then violation occurs. As the latch is level
sensitive clock, this type of violation is highly predictable.
Timing analysis is classified into two methods: static and dynamic. The differences between these two
approaches are listed as follows:

Static Timing Verification

 Timing analysis does not consider the simulation behavior of the circuit
 Delay is estimated without simulation
 Inaccurate estimation
 Analysis depends upon the delay modeling and interconnections in the circuit
 Analysis time is linear in size of the circuit

Dynamic Timing Verification

 Timing analysis is estimated based on the input pattern simulation
 Delay of the circuit is estimated by simulating the circuit with test vectors
 Approximately 100 percent accuracy is achieved
 Analysis depends on the simulation and input patterns for simulation
 Insufficient simulation due to exponential patterns leads to partial coverage

On-Chip Debugging
As the design complexity increases, the complexity involved in the functional and timing verifications
increases exponentially. Functional verification using simulation is a highly complicated task. To simplify
the verification process of high performance processors or VLSI designs, on-chip debugging is introduced.
On-chip debugging means built-in microprocessor debugging. Addition of on-chip hardware is embedded
on the chip itself to diagnose the system. Software program monitors the hardware functionality and
generates the reports. Some of the EDA tools that support on-chip debugging and its software are listed as
follows:
 Altera product: Quartus-II software with on-chip debugging using external interfaces as SignalProbe
and External Logic Analyzer

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 Open On-Chip Debugger with JTAG as external interface

 Flash Pro On-Chip Debugger for Actel FPGAs
 Xilinx product: Chip scope for FPGAs

Summary
This chapter has described the design automation procedure for VLSI design process and the
characteristics of such design as a foundation for understanding CAD systems. EDA refers to a set of
computer programs used to facilitate the design and physical realization of electronic circuits. Typically,
this can be on a chip or PCB, and involves layout, verification, and performance simulation of electronic
circuits. The two major approaches to design the complex circuits are discussed and in present day
scenario, both approaches are combined to design the digital circuits. The various tools and vendors
associated with front-end and back-end tasks are listed with brief description of editors. Finally, the
synthesis and simulation results simulated using Xilinx tools are discussed with all the parameters of the
design constraints, such as area and power. Simulation procedure using deterministic and random
approaches gives the detailed verification of the logical components. Static and dynamic timing
verification and on-chip debugging sets the stage for the computer-aided design tools described in this
book.

Questions
1. Write the importance of EDA tools. Explain the process of design flow for ASICs and FPGAs.
2. What is the difference between top-down design approach and bottom-up design approach? Illustrate
with example.
3. What is the major bottleneck in design automation tools?
4. Illustrate the functional and timing verifications for a 2x2 multiplier circuit.
5. Write the test vectors for logic simulation of 4x1 multiplexer.
6. Discuss the factors involved in timing verification for large circuits.
7. Why on-chip debugging is required to verify the circuits?

Exercises
1. Write the procedure to design 8x1 multiplexer with only 2x1multiplexers using top-down approach.
Draw the design process flow.
2. Draw the flow-chart to design a 4-bit parallel adder and full adder with bottom-up approach.
3. Give two examples where top-down and bottom-up approaches are required to design a given task.
4. What is the difference between simulator, emulator, and on-chip debuggers? Explain the differences
with example.
5. Explain why timing verification is a necessary step in the process of design flow.
6. Generate the simulation report using Xilinx ISE tool for a grey code to binary code converter.
7. Generate the random test vectors to verify the 2-bit binary counter.
8. List some verification tools and its features in detail.

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HDL Simulation
and Synthesis
If you need an information: See page:
Overview of VHDL 102
Overview of Verilog 127
Simulation 136
Synthesis 137
Behavioral Modeling 140
Timing Analysis 141
RTL Simulation 141
VITAL Simulation 141
Chapter 7

This chapter introduces the fundamentals of the VHDL and Verilog Hardware Description Languages
(HDL). These languages are used to implement and analyze primitive gates as well as complex
combinational and sequential logic circuits. Verilog is popular in North America and Japan; whereas,
VHDL is popular in Europe. A detailed description of VHDL and Verilog code structure to write an
expression of subsections within a design unit, such as assignments, expressions, operands, and operators,
is given. A study on basic constructs of VHDL and Verilog is discussed with examples including
simulation and synthesis details. A detailed description is given to verify the design and synthesize the
circuit using Electronic Design Automation (EDA) tools.

Overview of VHDL
VHDL stands for VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed
Integrated Circuit. Nowadays, VHDL is a very popular language along with Verilog for simulation,
modeling, documentation, and synthesis of high-speed integrated circuits. Due to complex circuits for
large systems, entering the circuit schematic manually is a very difficult task. Therefore, VHDL or Verilog
can be used to describe a system. In addition, writing Boolean expressions using any of these languages is
similar to a programming language method.
VHDL is a very popular language particularly in the academic community. However, the academic
industry uses both Verilog and VHDL equally well. The VHDL language was introduced in the year 1983
by the joint effort of IBM, Texas Instruments, and Intermetrics. The Institute of Electrical and Electronics
Engineers (IEEE) standardized this language in the year 1987 as IEEE1076 and revised to IEEE 1076 in
1993. VHDL has set a new standard for modeling Application Specific Integrated Circuit (ASIC) and Field
Programmable Gate Array (FPGA) libraries.
A system described using VHDL has a number of advantages, which are given as follows:
 Documenting the design—Instead of explaining the design in natural language sentence, if the
design is expressed in VHDL, then it will result in a very precise description of the system with no
ambiguities.
 Modeling and simulation of the system—A system can be modeled and simulated on a desktop or
workstation and its behavior can be studied without actually implementing the prototype. This saves
lot of time and cost. VHDL is used not only for modeling and simulation of electronic systems but
also for electromechanical and chemical systems.
 Synthesis of the system—Tools are available that can take the VHDL input and generate the circuit
diagram using primitives, such as gates and flip-flops.
A system can be described in VHDL in one of the two forms:
 Behavioral description—In this description, the system is described based on how it works and not
based on how it is implemented. The relationship between the input and output signals is specified
using sequential or concurrent statements. The two approaches in this description style are data flow
model and algorithmic flow model. In data flow model, the system is described using concurrent
statements in VHDL that are executed in parallel as soon as the data arrives at input. The register
transfer statements are used to write the concurrent statements. On the other hand, in algorithmic
flow model, the statements describe the sequence of flow of execution of the statements as per the
system requirements.
 Structural description—In this description, the system is described based on how it is implemented.
In other words, the system is described in terms of interconnection of gates to perform a desired
function.
Let’s observe the difference between two description styles in the following example.

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Example: Perform the addition of two bits.

Behavioral style:
input a,b; output c;
c = a+ b;
Structural style:
input a,b; output c;
c = a or b;
HDLs are used for designing and modeling any digital systems. It is necessary to partition the design into
abstract blocks called components where each component is the instantiation of a design entity. These
components are compiled by simulation using the Modelsim tool and synthesized using Xilinx synthesis
tools. The design entities, code structure, modular structure, data types, variable declarations, and logical
and structural syntax to program in VHDL are discussed in subsections.

VHDL Code Structure

Basic structure of a VHDL file consists of primary and secondary units. The description of the units is
given as follows.

Primary Units
The design units that are visible in library are called primary units. The primary design units are
configuration declaration, entity declaration, and package declaration. These declarations act as an
interface to the external world that defines the input and output signals.
The primary units are described as follows:
 Configuration declaration—A configuration declaration describes the binding between the entity and
architecture. Single configuration can specify multiple entity architecture bindings.
Syntax for the configuration description is as follows:
configuration identifier of entity_name is
[ declarations…]
end architecture identifier ;
 Package declaration: The global variable declarations are declared using the package declaration
design entity. The variables declared in package declaration are treated as global variables and are
accessible across multiple design units. Syntax for the package description is as follows:
package identifier is
[declarations…]
end package identifier;
 Entity declaration: An entity declaration describes the interface of a design entity through which it is
communicated to other entities in the same environment. An entity provides the port information of a
particular design entity while the architecture provides the functional body description of a design
entity. In other words, it describes the interface of a design entity through which it communicates
with other design entities. The interface includes the output, input, and bidirectional signals defined
in port declaration section.
Syntax for the entity description is as follows:
entity <entity_name> is
port(
port assignments
...
);

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The name of the system is the name of the entity itself. The port statement involves declaration of the
inputs and outputs of the design. These input and output ports act as an interface to the design, and the
declarations are read or set within the accompanying architecture.
For example, to describe a system MobilePhone, its entity is written as follows:
entity MobilePhone is
….
end entity MobilePhone;
Similarly, if the system to be described is CDROM, then its entity is written as follows:
entity CDROM is
….
end entity CDROM;
Again, if the system to be described is a basic gate, such as AND gate, then its entity is written as follows:
entity ANDGATE is

port(a,b : input; c: output)

end entity ANDGATE;

Secondary Units
The design units that are not visible in library are called secondary units. These units are interconnected
components of the design. The secondary units in VHDL are package body declaration and architecture
body declaration. These are discussed with the syntax as follows:
 Package body declaration—Package body declaration is associated with the package declaration.
This declaration is used to implement the subprograms declared in the package declaration. Syntax
for package body description is as follows:
package body identifier is
[ declarations]
end package body identifier ;
 Architecture body declaration:—Architecture body declaration is used to implement a design entity.
There can be more than one architecture for a design entity. The architecture can be described as a
behavior style, structural style, or data flow style. Syntax for architecture body description is as
follows:
architecture identifier of entity_name is
[ declarations]
begin -- optional
[ statements]
end architecture identifier ;

Syntax and Semantics of VHDL

Comments
An important utility of VHDL is to document the design. Therefore, the VHDL code must have enough
comments that make the code understandable. In VHDL, every comment must begin with -- (two hyphens
without any space in between). The entire string from the beginning of -- till the end of line is considered
as a comment. Syntax for a comment is as follows:
-- <statements>
For example:
-- Architecture of NOR Gate

generic (loopcounter := 3); -- loop counter is a temporary variable

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In addition, it is important that every file should have a header that contains the following information
about the file:
-- File name:
--Purpose:
--Development tools used:
--Author:
--Known bugs if any:
--Version history
--version no. 1.0 dated 12 Jun 2010
This type of header will be very useful for the maintenance of code.

Library
The VHDL library contains the design elements that can be used in VHDL source files to design any
digital systems. These libraries are platform independent. These libraries are user defined and built in
packages. To use the packages defined in a library, the use statement is used in VHDL. The syntax of the
use statement is given as follows:
Syntax:
Library < library_name>;
use < library_name > <package_name> [all|<part>];
The standard library IEEE is used and its package, IEEE.numeric_std.all is defined using the library
statement and the use statement respectively as follows:
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

Identifiers
VHDL identifier consists of letters, digits, and underscores (_). An identifier is used to give a name to a
data object. A VHDL identifier is case insensitive.
For example: a1, sum, carry12, and carry_1.

Data Types and Objects

Data types in VHDL are categorized as scalar and composite data types. Enumerated and integer data
types are known as scalar data types; whereas, array and record data types are known as composite data
types.

Scalar data types

 Enumerated data type—It consists of a set of user defined data values. The order in which
enumerated values are declared determines the numerical order. Syntax of the enumerated data type
is as follows:
type enum_type_name is (enum_value{enum_value});
Where, enum_type_name is the identifier name of the enumerated data type
enum_value is an identifier or character literal
 Integer data type—It defines a range of integers. Syntax of the integer data type is as follows:
Type type_name_identifier is range integer_range;
Where, type_name_identifer is an identifier
 Composite data types —The data types that are used as a collection of data are called composite data
types. If the collection of data is homogeneous, then they are called array data type; otherwise, they
are called record data type. Syntax of the composite data type is as follows:

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Syntax:
type type_name_identifier is array (range integer_range) of std_logic;
type type_name_identifier is record (range integer_range) of std_logic;

Data Objects
Data object is a collection of possible values of any data type. Depending on the type of data that holds
varies the name of the object. The different data types that are supported in VHDL are signal, constant,
variable, and file.
In the next subsection, you learn how to implement commonly used digital circuits in VHDL. You also
learn how to use Xilinx ISE and ModelSim together for the simulation. In addition, you learn how the
resources of a Xilinx FPGA device are utilized for each circuit.

When you implement a circuit in an FPGA, it is important to find out the resources utilization. This knowledge is very
useful when you have to actually design hardware built around an FPGA, as you need to estimate the FPGA resources
required.

NOT Gate
The function of a single input NOT gate is to invert the input. Figure 7.1 shows a NOT gate:

Figure 7.1: Displaying the NOT Gate

The truth table of NOT gate is as follows:
Input Output

0 1

1 0

VHDL Implementation
Following is the VHDL implementation of NOT gate:
-- File name: NotGate.vhdl
-- Create Date: 11:13:21 17/03/2010
-- Module Name: NotGate
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 10.1i,ModelSim SE 6.0

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
---------------------------------------------------------------
--library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

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---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity NotGate is -- entity declaration

port (input : in std_logic; -- input port

output: out std_logic -- output port

);

end NotGate;

architecture NotGateArch of NotGate is -- architecture declaration

begin

output <= not input;

end NotGateArch;

Simulation Results
Modelsim 6.0 simulator is used to test the design and generate waveforms for the given input test vectors.
This simulator generates the waveform for all the possible input vectors to the given design. The timing
summary and device utilization summary reports are given for each VHDL code segment for information
about resource utilization. The Xilinx ISE tool generates these reports. The details of speed grade and
maximum combinational path delay are given in the timing summary report. The speed grade influences
various timing parameters in the FPGAs, such as logic blocks and memory blocks. To meet the timing
constraints of the target device, the speed grade is considered as high or low based on the target device
speed. For the Virtex -4 device, speed grades are -10 (slowest), -11, and -12 (fastest); whereas, for the
Virtex-5 device, speed grades are -1 (slowest), -2, and -3 (fastest). Combinational path delay is defined as
the longest path delay from the primary input to primary output. The device utilization summary report
displays the detail information related to the logical components in terms of slice and Look Up Table
(LUT) required to implement the given design. The utilization ratio of slices, LUTs, and I/O blocks
information is generated by the Xilinx ISE tool in the synthesis report. The total number of slices in target
device is 5472, number of LUTs is 10944, and I/O buffers are 240. For all the basic gates, VHDL and
Verilog code fragment is given with simulation waveforms and device utilization summary.

Timing Summary
Speed grade: -10
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.415ns

Device Utilization Summary

The project status that will be displayed is as follows:

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Chapter 7

Device Utilization Summary (Estimated Values)

Logic Utilization Used Available Utilization

Number of Slices 1 5472 0%

Number of 4-input LUTs 1 10944 0%

Number of bonded IOBs 2 240 0%

Fig 7.2 shows the NOT gate simulation results:

Figure 7.2: Displaying the NOT Gate Simulation Results

In Figure 7.2, the tool generates the waveform when the input is 1 and the output is 0. Similarly, for the
input 0, the output is 1.

OR Gate
The output of the two-input OR gate is high when any one of the inputs is high or when both the inputs
are high. When both the inputs are low, the output is low. The two-input OR gate takes two inputs,
inputs(1) and inputs(0), as shown in Figure 7.3:

Figure 7.3: Displaying the OR Gate

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 HDL Simulation and Synthesis

The truth table of OR gate is as follows:

Inputs(1) Inputs(0) Output
0 0 0
0 1 1
1 0 1
1 1 1

VHDL Implementation
Following is the VHDL implementation of OR gate:
-- File name: OrGate.vhdl
-- Create Date: 11:26:37 17/03/2010
-- Module Name: 2 Input OrGate
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 9.1i,ModelSim SE 6.0

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------
--library declaration

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

-- entity declaration

entity OrGate is

-- input ports

port (inputs : in std_logic_vector(1 downto 0);

-- output ports

output : out std_logic

);

end OrGate;

-- architecture declaration

architecture OrGateArch of OrGate is

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Chapter 7

begin

output <= inputs(0) or inputs(1);

end OrGateArch;
Note that we have taken the two inputs, inputs(0) and inputs(1), as a vector.

Device Utilization Summary

The project status that will be displayed is as follows:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 1 5472 0%

Number of 4-input LUTs 1 10944 0%

Number of bonded IOBs 3 240 1%

Figure 7.4 shows the OR gate simulation results:

Figure 7.4: Displaying the OR Gate Simulation Results

In Figure 7.4, when the input vector is 00, the output is 0. For all the other input values, that is, 01, 10 and
11, the output is 1.

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 HDL Simulation and Synthesis

AND Gate
The two-input AND gate’s output is high only when both the inputs are high. The two-input AND gate is
represented, as shown in Figure 7.5:

Figure 7.5: Displaying the AND Gate

The truth table of AND gate is as follows:
Input a Input b Output
0 0 0
0 1 0
1 0 0
1 1 1

VHDL Implementation
Following is the VHDL implementation of AND gate:
-- File name: AndGate.vhdl
-- Create Date: 09:47:22 18/03/2010
-- Module Name: 2 Input AND Gate
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 9.2i, ModelSim SE 6.0

-- Revision 0.01 - File Created

-----------------------------------------------------------
--library declaration

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--entity declaration

entity AndGate is

-- input ports

port (inputa : in std_logic;

inputb : in std_logic;

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Chapter 7

-- output ports

output : out std_logic

);

end AndGate;

-- architecture declaration

architecture AndGateArch of AndGate is

begin
output <= inputa AND inputb;

end AndGateArch;

Device Utilization Summary

The project status that will be displayed is as follows:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 1 5472 0%

Number of 4-input LUTs 1 10944 0%

Number of bonded IOBs 3 240 1%

Figure 7.6 shows the AND gate simulation results:

Figure 7.6: Displaying the AND Gate Simulation Results

In Figure 7.6, observe that the output is 1 only when both the inputs are 1; for all other cases, the output is
0.

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 HDL Simulation and Synthesis

NOR Gate
The NOR gate is a two-input gate whose output is high when both the inputs are low. When any one of
the input is high, then the output is low. The block diagram of NOR gate is shown in Figure 7.7:

Figure 7.7: Displaying the NOR Gate

The truth table of NOR gate is as follows:
Inputs(1) Inputs(0) Output
0 0 1
0 1 0
1 0 0
1 1 0

VHDL Implementation
Following is the VHDL implementation of NOR gate:
-- File name: NorGate.vhdl
-- Create Date: 10:51:58 17/03/2010
-- Module Name: 2 Input Norgate
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 9.2i,ModelSim SE 6.0

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
------------------------------------------------------------------
--library declaration

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--entity declaration

entity NorGate is

-- input ports

port (inputs : in std_logic_vector( 1 downto 0 );

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Chapter 7

-- output ports

output : out std_logic

);

end NorGate;

-- architecture declaration

architecture NorGateArch of NorGate is

begin

output <= inputs(0) nor inputs(1);

end NorGateArch;

Device Utilization Summary

The project status that will be displayed is as follows:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 1 5472 0%

Number of 4-input LUTs 1 10944 0%

Number of bonded IOBs 3 240 1%

Figure 7.8 shows the NOR gate simulation results:

Figure 7.8: Displaying the NOR Gate Simulation Results

In Figure 7.8, you can observe the waveforms for all the possible combination of input values for a two-
input NOR gate.

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 HDL Simulation and Synthesis

NAND Gate
The output of the two-input NAND gate is high when one of the inputs is low. However, when all the
input values are high, the output is low. The realization of NAND gate is as shown in Figure 7.9:

Figure 7.9: Displaying the NAND Gate

The truth table of NAND gate is as follows:
Input a Input b Output
0 0 1
0 1 1
1 0 1
1 1 0

VHDL Implementation
Following is the VHDL implementation of NAND gate:
-- File name: NandGate.vhdl
-- Create Date: 10:27:48 19/03/2010
-- Module Name: 2 Input NandGate
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 9.2i,ModelSim SE 6.0
-- Revision:
-- Revision 0.01 - File Created

-----------------------------------------------------------------
--library declaration

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- entity declaration

entity NandGate is

-- input ports

port (inputs : in std_logic_vector( 1 downto 0 );

-- output port

output : out std_logic

);

end NandGate;

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Chapter 7

--- architecture declaration

architecture NandGateArch of NandGate is

begin

output <= inputs(0) nand inputs(1);

end NandGateArch;

Device Utilization Summary

The project status that will be displayed is as follows:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 1 5472 0%

Number of 4-input LUTs 1 10944 0%

Number of bonded IOBs 3 240 1%

The simulated results for the NAND gate are shown in Figure 7.10:

Figure 7.10: Displaying the NAND Gate Simulation Results

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 HDL Simulation and Synthesis

XOR Gate
The output of the two-input XOR gate is high when both the inputs are different. However, when both the
inputs are same, output is low. Realization of XOR gate is shown in Figure 7.11:

Figure 7.11: Displaying the XOR Gate

The truth table of XOR gate is as follows:
Inputs(1) Inputs(0) Output
0 0 0
0 1 1
1 0 1
1 1 0

VHDL Implementation
Following is the VHDL implementation of XOR gate:
-- File name: XorGate.vhdl
-- Create Date: 12:26:35 20/03/2010
-- Module Name: 2 Input XorGate
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 9.2i,ModelSim SE 6.0

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------
--library declaration

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

-- entity declaration

entity XorGate is

-- input ports

port (inputs : in std_logic_vector( 1 downto 0 );

-- output ports

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Chapter 7

output : out std_logic

);

end XorGate;

-- architecture declaration

architecture XorGateArch of XorGate is

begin

output <= inputs(0) xor inputs(1);

end XorGateArch;

Device Utilization Summary

The project status that will be displayed is as follows:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 1 5472 0%

Number of 4-input LUTs 1 10944 0%

Number of bonded IOBs 3 240 1%

The simulation results of the XOR gate are shown in Figure 7.12:

Figure 7.12: Displaying the XOR Gate Simulation Results

The number of LUTs required to implement XOR gate is 1 over 10944.

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 HDL Simulation and Synthesis

XNOR Gate
The output of the two-input XNOR gate is high when both the inputs are same. However, when the input
values are different, output value is low. Figure 7.13 shows the XNOR gate:

Figure 7.13: Displaying the XNOR Gate

The truth table of XNOR gate is as follows:
Inputs(1) Inputs(0) Output
0 0 1
0 1 0
1 0 0
1 1 1

VHDL Implementation
Following is the VHDL implementation of XNOR gate:
-- File name: XnorGate.vhdl
-- Create Date: 12:11:45 20/03/2010
-- Module Name: 2 Input XnorGate
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 9.2i,ModelSim SE 6.0

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------
--library declaration

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.V Components.all;

-- entity declaration

entity XnorGate is

-- input ports

port (inputs : in std_logic_vector( 1 downto 0 );

-- output port

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Chapter 7

output : out std_logic

);

end XnorGate;

-- architecture declaration

architecture XnorGateArch of XnorGate is

begin

output <= not (inputs(0) xor inputs(1));

end XnorGateArch;

Device Utilization Summary

The project status that will be displayed is as follows:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 1 5472 0%

Number of 4-input LUTs 1 10944 0%

Number of bonded IOBs 3 240 1%

The simulation results of the XNOR gate are shown in Figure 7.14:

Figure 7.14: Displaying the XNOR Gate Simulation Results

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 HDL Simulation and Synthesis

D Flip-Flop
The feature of D flip-flop is that it can hold the last value stored; and therefore, can be considered as a
basic memory cell. Figure 7.15 shows a positive edge triggered D flip-flop:

Figure 7.15: Displaying the D Flip-Flop

As shown in Figure 7.15, the D flip-flop samples its input and changes its output q and q_bar at the rising
edge of the controlling clock. The two types of flip-flops with enable are shown: one with synchronous
reset and another with asynchronous reset. The function of enable is that when it is high, the external
input is selected and used; however, when the enable is low, flip-flop’s current output is used.
The truth table of D flip-flop is as follows:
idata Q qbar
0 0 1
1 0

The VHDL code for the function of D flip-flop is given as follows:

VHDL Implementation
Following is the VHDL implementation of D flip-flop gate:
-- File name: D-FlipFlop.vhdl
-- Create Date: 09:45:09 21/03/2010
-- Module Name: D-FlipFlop
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 9.2i,ModelSim SE 6.0

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------

121
Chapter 7

--Libarary declaration

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--entity declaration

entity Dff is

--inputs

port (idata,idata1 : in std_logic;

clk,clk1 : in std_logic; -- clk input
rst,rst1 : in std_logic; -- reset
enb,enb1 : in std_logic;
--outputs
q : out std_logic; -- output Q
q1 : out std_logic;
qbar : out std_logic; -- output qbar
qbar1 : out std_logic
);
end Dff;

-- architecture declaration

architecture DffArch of Dff is

--signal declaration

signal tempq, tempq1 :std_logic;

begin

-- process sync

sync : process (clk, rst) -- synchronous reset dff

begin

-- activities triggered by rising edge of clock

if clk'event and clk = '1' then

-- activities triggered by synchronous reset (active high)

if rst = '1' then

tempq <= '0';

else
if enb ='1' then -- enable input(active high)

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 HDL Simulation and Synthesis

tempq <= idata;

else
tempq <= '0';

end if;

end if;

end if;
end process sync;

qbar <= not tempq;

q <= tempq;

-- process async

-- asynchronous reset d flip flop

async : process (clk1, rst1)

begin

-- activities triggered by asynchronous reset (active high)

if rst1 = '1' then

tempq1 <= '0';

-- activities triggered by rising edge of clock

elsif clk1'event and clk1 = '1' then

if enb1 = '1' then -- enable input(active high)

tempq1 <= idata1;

end if;

end if;
end process async;

qbar1 <= not tempq1;

q1 <= tempq1;
end DffArch;

Device Utilization Summary

The project status that will be displayed is as follows:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 2 5472 0%

Number of Slice Flip-Flops 4 10944 0%

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Chapter 7

Device Utilization Summary (Estimated Values)

Logic Utilization Used Available Utilization

Number of 4-input LUTs 3 10944 0%

Number of bonded IOBs 12 240 5%

Number of GCLKs 2 32 6%

Based on the device utilization summary, the number of LUTs required to synthesize the design is 3;
whereas, slices are 2.

Simulation Results
The simulation results are shown in Fig. 7.12. where the inputs to the two-input XOR gate are termed as
inputs(0) and inputs(1) and output of the D flip-flop are shown in Figure 7.16. The number of LUTs
required to implement XOR gate is 1 over 10944.

Figure 7.16: Displaying the D Flip-Flop Simulation Results

Decade Counter
Decade counter is a 4-bit counter. The input ports of the decade counter are as follows:
 rst: It is an active high reset
 clock: It is a clock whose maximum operating frequency is 405.301 MHz
The output ports of the decade counter are as follows:
 output (9:0): Out of the ten outputs, only one will be high at a time for one clock cycle and others will
be low
 counth: After completing the counting, it will be high for one clock cycle

124
 HDL Simulation and Synthesis

Figure 7.17 shows the decade counter:

Figure 7.17: Displaying the Decade Counter

VHDL Implementation
Following is the VHDL implementation of decade counter:
-- File name: DecadeCounter.vhdl
--
-- Create Date: 15:01:57 21/03/2010
-- Module Name: Decade Counter(0-9)
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 9.2i,ModelSim SE 6.0

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------
-- library declaration

library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- entity declaration

entity CountDec is

-- input ports

port (clk : in std_logic; -- clock input

rst : in std_logic; -- reset input

-- output ports
output : out std_logic_vector(9 downto 0);

-- it will be high for one clock cycle after counting specified no. of count value

counth : out std_logic

);
end CountDec ;

-- architecture declaration

architecture CountDecArch of CountDec is

125
Chapter 7

-- signal declaration

signal count : std_logic_vector(3 downto 0);

signal countpoint : std_logic;

begin

process (clk, rst) --- process

begin

-- activities triggered by asynchronous reset (active high)

if rst = '1' then

count <= (others => '1');

-- activities triggered by rising edge of clock

counth <= '0';

elsif clk'event and clk = '1' then

if conv_integer(count) = 9 then -- counter

countpoint <= '1';
count <= (others => '0');

else
countpoint <= '0';
count <= count + '1';

end if;

end if;
end process;

output(0)<= (not count(3)) and(not count(2))and(not count(1))

and(not count(0));
output(1)<= (not count(3)) and(not count(2))and(not count(1))
and(count(0));
output(2)<= (not count(3)) and(not count(2))and( count(1))
and(not count(0));
output(3)<= (not count(3)) and(not count(2))and( count(1))and( count(0));
output(4)<= (not count(3)) and( count(2))and(not count(1))
and(not count(0));
output(5)<= (not count(3)) and( count(2))and(not count(1))and( count(0));
output(6)<= (not count(3)) and( count(2))and( count(1))and(not count(0));
output(7)<= (not count(3)) and( count(2))and( count(1))and( count(0));
output(8)<= (count(3)) and(not count(2))and(not count(1))
and(not count(0));
output(9)<= (count(3)) and(not count(2))and(not count(1))
and( count(0));
counth <= countpoint;

end CountDecArch ;

126
 HDL Simulation and Synthesis

Device Utilization Summary

The project status that will be displayed is as follows:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 9 5472 0%

Number of Slice Flip-Flops 5 10944 0%

Number of 4-input LUTs 15 10944 0%

Number of bonded IOBs 13 240 5%

Number of GCLKs 1 32 3%

Simulation Results
Figure 7.18 shows the simulation results of decade counter:

Figure 7.18: Displaying the Decade Counter Simulation Results

As shown in Figure 7.18, the simulation results for the functionality of decade counter is apparent.

Overview of Verilog
Verilog is the registered trademark of Cadence Design Systems Inc. Philip Moorby developed the Verilog
language in the year 1985. IEEE has standardized Verilog in the year 1995 as IEEE Standard 1364. Open
Verilog International (OVI), established in 1991, has been promoting this language. You can get the latest
updates on Verilog from the website www.verilog.com.
One of the most attractive features of Verilog is that it is very easy to learn. If you know the C language,
then it is much more easy, as the syntax is very similar to C. Simulation and synthesis can also be done
very fast using this language, and several tools are available that support this language. This language is
very popular in North America and Japan.

127
Chapter 7

Verilog Code Structure

Suppose you want to develop a mobile phone. It is a system, which must have an electronic circuit. This
circuit is called a module in Verilog. You can represent the module in Verilog as
module MobilePhone;
…
…
endmodule
Another example of a module is
module Calculator;
…
…
endmodule
Every system is meant to do some work. It can be calculations or to make you talk to someone. This work
is described in the body of the module. Every system has to communicate with external world; for
example, if your mobile phone has no keypad to key in the telephone numbers or a display, then it is a
useless mobile phone. A module communicates with the external world using an interface. Therefore,
every module must have an interface. In addition, you can enhance the functionality of a module through
add-ons. Therefore, a Verilog module with all these features will look as follows:
module MobilePhone (…);
input …;
output …;
`include “Bluetooth”
…
endmodule
The module is the basic building block. The general structure of a Verilog module is as follows:
module modulename (portlist);
port declarations;
parameter declarations;
`include directives
body of the module
endmodule
The body in turn contains:
Variables declaration
Assignments
Low-level module instantiations
Initial block
Always blocks
Tasks and functions
Note that the port list and the parameter declarations specify the interface of the module.
Module name is called identifier. An identifier can have letters, digits, $ sign, and underscore character.
Spaces are not allowed in between the letters. Identifiers must start with a letter or underscore. You need
to remember that Verilog is case sensitive, that is, Calculator and calculator are two different identifiers.
Keywords (words that have special meaning in Verilog) cannot be used as identifiers. You should give
meaningful and readable names to the identifiers. It will help others to understand your program.
Some examples of identifiers are CPU, Memory, Modulator, Demodulator, and Serial_Port.
The interface of the module consists of two parts:
 port list—Refers to a part, which is specified within brackets immediately after the module name.

128
 HDL Simulation and Synthesis

 port declaration—Specifies the direction of the data flow and the width of the port. The direction can
be input to the system, output from the system, or both input and output to the system. The width is
to indicate whether it is a single wire or a bus.
For example,
module CPU(clock, reset, address, data);
input clock;
input reset;
output [31:0] address;
inout [15:0] data;
…
endmodule
A module can be specified in the following three ways:
 Structural approach—In this approach, the system is specified using logic gates. Any digital circuit
can be represented using logic gates, which are the primitives in any digital circuit. However, too
many gates can make the circuit complex and complicated. To reduce the complexity, you can create a
library of different modules, such as adders and multiplexers, and use them in your module so that
you can build the system. An advantage of using this approach is that you can synthesize the circuit
easily.
 Dataflow approach—As a system takes some inputs, processes the input, and produces some output,
a system can be represented by using a set of assignment statements using expressions and operators
for the transformation of the input to the output. This is similar to writing a series of assignment
statements in a programming language by using various operators and expressions.
 Behavioral approach—In this approach, the behavior of a system is described without going into the
details of how it has been using a series of programming statements to describe the behavior of the
system through programming. This is called behavioral style. It is very easy to program, but difficult
to synthesize.

Syntax and Semantics of Verilog

Comments
Comments help a lot in understanding the code. If you take a leave and come back after ten days, you may
not be able to understand your own code in case there are no comments. Therefore, it is a good practice to
make the first line of your program a comment. Commenting in Verilog is exactly same as in C language.
Comments can be written in a single line as,
// This is a 4-bit adder
If a comment is of more than one line, then block commenting can be done as follows:
/* This is Verilog implementation of an error correction encoder
and decoder. It uses rate ½ convolution code */
It is always good to start writing the code with comments. A suggested commenting style for every file is
as follows:
// Filename
// Name of the project
// Purpose of this module
// Development environment
// Bugs if any
// Revision history

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Chapter 7

Data Types
In the Verilog language, data types have four values set: 0, 1, X, and Z. Logic zero is represented by 0,
1represents logic one value, X represents an unknown logic value, and Z represents high-impedance state.
The input and output values based on the four valued data for a BUF gate is as follows:

Data Objects
Data objects are declared in a model as a single element or an array of elements. The different types of data
objects that are supported by Verilog are signal, wire, supply nets, register, parameter, integer, and
memory.
Description of some of the data objects are as follows:
 Net—Represents the physical connection of signals in the circuit. Different types of nets are wor,
wand, and wire. These data objects can be declared as a scalar or vector type.
For example: wire n1; // n1 is a net of type wire
 Register—Holds the unsigned data. The value holds for a simulation delta cycle. The register can be
declared as a scalar or vector type.
For example: reg (2:0) r1; // r1 is a vector that holds 3-bit unsigned data.
 Parameter—Holds a constant value. These data objects are used to define the values or constants that
are local to a module or local to a sub-module.
For example: parameter P = 2’b11; // P is defined as constant value as 3
 Integer—Holds the data in signed representation form. These data objects are used to declare general-
purpose variables. Default size of an integer data object is 32-bit in size. Integer data object is of scalar
type.
For example: integer Count; // variable name count of type integer

NOT Gate
The program written in Verilog HDL, which is simulated using the Modelsim simulator tool, and the truth
table for the NOT gate is given as follows:

130
 HDL Simulation and Synthesis

//File Name : notgate.v

//Created on : 14-03-2010
//Module Name: notgate
//ProjectName: verilog_project

module notgate(inputa,out);

input inputa;
output out;

not(out,inputa);
endmodule
The waveform generated from the simulator for the basic gate is as shown in Figure 7.19:

Figure 7.19: Displaying the NOT Gate Simulation Results

OR Gate
Verilog code written using data flow model for two-input OR gate with two-valued function is given as
follows:
//File Name : or2.v
//Created on : 14-03-2010
//Module Name: or2
//ProjectName: verilog_project
module or2(inputa,inputb,out);
input inputa;
input inputb;
output out;
assign out=(inputa |inputb); //data flow
endmodule
Figure 7.20 shows the simulation results of an OR gate:

Figure 7.20: Displaying the OR Gate Simulation Results

Figure 7.21shows the four-valued truth table of an OR gate:

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Figure 7.21: Displaying the Four-Valued Truth Table of an OR Gate

AND Gate
The Verilog code fragment is written to simulate the functionality of two-valued AND gate as follows:
//File Name : and2.v
//Created on : 17-03-2010
//Module Name: and2
//ProjectName: verilog_project
module and2(inputa,out);
input [2:0] inputa;
output out;
and(out,inputa[0],inputa[1],inputa[2]);
endmodule
Figure 7.22 shows the simulation results of an AND gate:

Figure 7.22: Displaying the AND Gate Simulation Results

Figure 7.23 shows the four-valued truth table of an AND gate:

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Figure 7.23: Displaying the Four-Valued Truth Table of an AND Gate

NOR Gate
The data flow model for 2-input NOR gate is shown as follows:
//File Name : nor2.v
//Created on : 17-03-2010
//Module Name: nor2
//ProjectName: verilog_project
module nor2(inputa,out);
input [1:0] inputa ;
output out;
nor(out,inputa[0],inputa[1]);
endmodule
Figure 7.24 shows the simulated results of two-input NOR gate using the Modelsim simulator tool:

Figure 7.24: Displaying the Two-Input NOR Gate

NAND Gate
The data flow model for two-input NAND gate is shown as follows:
//File Name : nand2.v
//Created on : 17-03-2010
//Module Name: nand2
//ProjectName: verilog_project
module nand2(inputa,out);
input [1:0] inputa;
output out;
nand(out,inputa[0],inputa[1]);
endmodule

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Figure 7.25 shows the simulated results of two-input NAND gate using the Modelsim simulator tool:

Figure 7.25: Displaying the Two-Input NAND Gate Simulated Results

XOR Gate
The Verilog code to two-input XOR gate is shown as follows:
//File Name : xor2.v
//Created on : 17-03-2010
//Module Name: xor2
//ProjectName: verilog_project
module xor2(inputa,out);
input [1:0] inputa;
output out;
xor(out,inputa[0],inputa[1]);
endmodule
Figure 7.26 shows the simulated results of two-input XOR gate:

Figure 7.26: Displaying the Two-Input XOR Gate Simulation Results

XNOR Gate
The Verilog code to two-input XNOR gate is shown as follows:
//File Name : xnor2.v
//Created on : 17-03-2010
//Module Name: xnor2
//ProjectName: verilog_project
module xnor2(inputa,out);
input [1:0] inputa;
output out;

xnor(out,inputa[1],inputa[0]);
endmodule
Figure 7.27 shows the simulated results of two-input XNOR gate:

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Figure 7.27: Displaying the Two-Input XNOR Gate Simulation Results

D Flip-Flop
The following code is an example of sequential circuit, D flip-flop, in Verilog:
// FileName : dff_beh.v
// Created On : 17-03-2010
// Module Name: dff_beh
// ProjectName: dff_proj
// Tool Name : ModelSim SE 6

module dff_beh(clk,rst,din,dout,dout_bar);
input clk,rst;
input din;
output dout;
output dout_bar;
reg dout;
assign dout_bar = ~dout; //data flow

always@(posedge clk or negedge rst) // sequential executing

begin
if(rst==0)
dout<=0;
else
dout<=din;
end
endmodule
The behavior of synchronous D flip-flop is simulated. In the preceding code, the input nets are din, clk,
and rst; the clock variable is declared as clk and reset variable as rst; and the output nets are dout and
dout_bar.
Figure 7.28 shows the simulation results of D flip-flop:

Figure 7.28: Displaying the D Flip-Flop Simulation Results

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Counter
The 4-bit counter is designed using Verilog behavioral model. The counter starts counting from 0000 to
1111 and repeats the sequence. The counter resets itself when reset is set to high. Count is a 4-bit output
variable. Input variables are clock (clk) and reset (rst). Following is the Verilog code of a 4-bit counter:
// File Name : counter.v
// Created On : 17-03-2010
// Module Name: counter
// ProjectName: counter_project
// Tool Name : ModelSim SE 6

module counter(clk,rst,count);
input clk,rst;
output [3:0] count;
reg [3:0] count;

always@(posedge clk)
begin
if(rst==1'b0)
begin
count<=4'b0000; // sets counter to zero's
end
else
count<=count+1'b1; // starts counting
end
endmodule
The simulated results of a 4-bit counter are shown in Figure 7.29:

Figure 7.29: Displaying the 4-Bit Counter Simulation Results

Simulation
Simulation is a process of design verification that takes place at several points in the design flow to ensure
correctness of the design. During the simulation process, the functionality of the design is been verified at
every stage, that is, from the first step to the last step. It is an iterative process to generate the test vectors
to verify the circuit behavior in terms of functionality and timing constraints.
A Verilog or VHDL simulators compile the design for syntax errors and simulate the design with the input
test vector. The simulator generates the waveforms that consist of input and output signals and the values
that are possessed based on the input vectors used to verify the entire design. Simulation of the design can
be done at various levels, that is, at the functional level, Register Transfer level, Place and Route level

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using static timing analysis, and post synthesis stage. The detailed characterization of the design can be
done using functional and timing simulations.
As already learned, simulation is a process of verification of the design. The design to be verified is termed
as Device Under Test (DUT), which contains the entire hierarchy of the design. For example, if a
microprocessor is coded in Verilog or VHDL, the various sub-modules, such as Load Store Unit (LSU) and
execution units (Integer Unit, Floating Point Unit, and Bus Interface Unit), are included in the top-level
design. The DUT represents the top-level module of the design hierarchy. The top-level module drives the
inputs to DUT and nets that receive outputs from the DUT to verify the design.
This detailed simulation process helps in making the necessary changes before the fabrication. During the
design flow, the simulator interprets VHDL or Verilog code and verifies the circuit behavior. The process
of verification of design flow in the Xilinx tool is considered for an explanation purpose. Verification is an
automated process and various commercial simulators, such as Specman Elite, Icarus Verilog, and
Modelsim, are available in the market.

Synthesis
After the functional verification of the design is completed, the next step in the design flow is synthesis.
The goal of the synthesis step is to convert the netlist into target FPGA or ASIC technology.
During this step, Boolean circuit, which is designed based on the specification written in the behavioral or
structural flow style of VHDL or Verilog code, is transformed into a functionally equivalent gate-level
netlist and LUT-level netlist (FPGAs).
The synthesis report generated by the Xilinx ISE tool, for the given design, consists of the details of
number of logic elements (LUTs) required to design, the combinational path delay, and logic levels or the
depth of the circuit. The technology schematic view of the design can be obtained from the Xilinx tool.
The VHDL code for the 2X1 multiplexer using the behavioral code style is as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux4 is
Port ( s1,s0 : in STD_LOGIC;
a,b,c,d : in STD_LOGIC;
y : out STD_LOGIC);
end mux4;
architecture Behavioral of mux4 is
begin
y<=(a and(not s1)and(not s0))or(b and(not s1)and s0)or(c and s1 and(not s0))or(d
and s1 and s0);
end Behavioral;
The gate-level netlist, technology schematic view, and synthesis report for the 2x1 multiplexer is, as shown
in Figure 7.30 (a) –(e):

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Figure 7.30 (a): Displaying the Device Utilization Summary

Figure 7.30 (b): Displaying the Gate-Level Netlist of 2x1 Multiplexer

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 HDL Simulation and Synthesis

Figure 7.30(c): Displaying the LUT-Level Netlist of 2x1 Multiplexer

Figure 7.30(d): Displaying the LUT-Level Netlist of 2x1 Multiplexer

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Figure 7.30(e): Displaying each LUT Component of 2x1 Multiplexer

Behavioral Modeling
Behavioral modeling is one of the methods to describe hardware circuits using HDL. This modeling is
used to represent the circuits at higher level of abstraction. Verilog language supports this type of
modeling for ease of design. Structural and data flow model descriptions are suitable for the circuits with
few hundreds of gate count. As the gate count increases, the description of the circuit difficult to model
using these models.
Behavioral modeling has become popular due to its ease of programming, which is similar to algorithmic
language. The constructs used in Verilog are similar to C language constructs, such as assignments, if-else
statements, case, for, functions, and procedures. Verilog constructs, such as always, initial, for, case, and
begin-end blocks, support the abstract description of the circuit. Design description at behavioral
modeling is done using the sequence of assignment statements. The example of using behavioral model in
Verilog to generate the Fibonacci sequence is given as follows:
module fib(a,b,c) // module name fib
input a,b; // input variable declarations
output c; //output variable declarations
initial // initial construct to initialize the values
begin
c = 1'b1;
a = 1'b0;
b = 1'b1;
end
always (posedge clock) // always construct
begin
a <=b;
b <=c;
c<= a+b;
end
end module // endmodule

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Verilog code generates the Fibonacci sequence of numbers during the positive edge triggered clock. The
simulation results of the Verilog behavioral code can be generated using Verilog constructs, such as
always and initial. The stimulus for the Verilog code to generate the Fibonacci sequence is given as
follows:
module stimulus; // stimulus to test the design
initial
clock = 1'b0; // initialize the clock
begin
#5 clock = ~clock; // 5 unit delay
#100 stop; // after 100 time units simulation stops
end
initial
$monitor(“ monitor: a = %b, b = %b, c = %c”, a,b,c); // displays the value of a ,
b and c
end module

Timing Analysis
Timing analysis or verification is the process of verifying that the design meets the timing constraints.
Timing verification can be done using timing simulation. During timing simulation, DUT is verified at the
desired speed under worst-case conditions. This process is performed once the design process completes
the mapping, placement, and routing. During the timing verification phase, critical path delays, setup
time, and hold time violations can be determined ahead of time, that is, at the pre-silicon fabrication stage.

RTL Simulation
Registered Transfer Level (RTL) simulation is a verification process to verify the design coded in VHDL.
To determine the functionality of the circuit, the simulation process needs two inputs: one is the design to
be tested and another is the stimulus file to test the behavior of the circuit. As already learned, design to be
tested is referred to as DUT.
Outputs generated by the DUT are compared with the actual values.
RTL simulation, which is also called functional simulation, takes place at early stages of the design flow,
that is, at the pre-silicon stage or pre-synthesis stage.

VITAL Simulation
VITAL stands for VHDL Initiative Towards ASIC Libraries.
It specifies a standard method of writing ASIC and FPGA libraries.
VITAL is an IEEE standard used for modeling accurate timing for the gate-level design.
This gate-level design is generated after Place and Route stage for the verification of functional and timing
constraints of the design.
The Place and Route tool generates two files: VHDL netlist and Standard Delay format file with details
about the timing information.
VITAL simulation uses these two files as well as an additional file called VITAL library.
The VITAL library file describes the behavior of entities that are used to implement the design.
VITAL simulation uses three files: VHDL netlist, SDF file, and VITAL library for timing and functional
verifications.

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Summary
In this chapter, we have discussed the basic concepts of VHDL and Verilog with examples and their
simulation results for basic gates and various simulation models.
VHDL and Verilog are HDLs used for the description of VLSI circuits using behavioral model or
structural model. The behavioral model description of the circuit is the abstract level of description similar
to the algorithmic approach. The structural model description of the circuit is defined as the
interconnection of the hardware components or logic components. This type of model is also called gate-
level modeling.
Conventions used for operators, comments, data types, identifiers, and literals in VHDL and Verilog are
also discussed. The VHDL and Verilog code for basic gates and universal gates are given with simulation
results and synthesis details, such as device utilization for the given design. Modelsim simulator provides
tools to simulate the design and generate the waveforms for the given test vectors. Test vectors are the set
of input vectors used to verify the functionality of the design. The Xilinx synthesis tool is used to
synthesize the design to target device. The target device is Vertex-4 of FPGA.
Various types of simulation, such as behavioral simulation, functional simulation, RTL simulation, timing
simulation, and VITAL simulation, are discussed. Simulation is a process of verification of the design. This
verification takes place at various stages during the design flow to meet the design constraints in terms of
functional and timing constraints. Behavioral simulation, functional simulation, and RTL simulation are
functional verification simulation methods. Timing constraints are verified by timing verification strategy;
whereas, VITAL simulation is used to verify the design after Place and Route stage.

Questions
1. Write the syntax and semantic for process construct in VHDL.
2. Explain the features of VHDL and Verilog HDL with examples.
3. Explain how logic optimization takes place at the synthesis stage of design flow.
4. What is behavioral simulation, VITAL simulation, and functional simulation?
5. Define critical path delay, setup time, and hold time.
6. Write a procedure to generate a set of test vectors to verify the 4-bit ripple carry adder.
7. Discuss the slice utilization and LUT utilization ratio for a 2-bit up-counter.

Exercises
1. Write the VHDL code to generate the counter that repeats the Fibonacci sequence.
2. What are the primary and secondary units?
3. Compare and contrast the HDLs with high-level programming languages.
4. Explain the various approaches to design a code in Verilog.
5. Write the Verilog code for push and pop operations in stack.
6. Write the Verilog code to implement queue implementation.
7. Discuss the features of behavioral modeling method in Verilog.

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IC Design
If you need an information on: See page:
PLAs 144
PLDs 146
FPGA 148
ASIC 151
Selection of an Appropriate Integrated Circuit 151
Chapter 8

This chapter gives the detail description of Programmable Logic Devices (PLDs), Programmable Logic
Arrays (PLAs), and Field Programmable Gate Arrays (FPGAs). The architecture of PLAs supports the
realization of any complex digital design using the AND and OR planes. The description of FPGA
architecture and its importance to build Very Large Scale Integration (VLSI) circuits is also discussed and
compared with complex PLDs. In addition, the chapter gives an insight for the selection of these devices
and their importance in designing real time applications.

PLAs
Conventional approach to design any digital design is to simplify the given digital design and realize it
with minimum number of gates. Then, the optimized design is implemented with basic gates or universal
gates that are connected with wires. This method is simple, but lack of portability is its disadvantage.
Figure 8.1 shows the block diagram of PLA:

Figure 8.1: Displaying the Block Diagram of PLA

Depending on the application, circuit size varies. Typically, circuit means a combination of Boolean
expressions represented in the form of gates and interconnections. In other words, Boolean expressions are
directly proportional to the circuit size. These Boolean expressions can be optimized to reduce the circuit
complexity and cost of representing it using gates. The Boolean theorems and postulates are used to
optimize any Boolean expression. These optimized expressions are represented in the three forms: Sum of
Products (SOP), Product of Sums (POS), and Factored Forms (FF). All the predefined gates with a set of
inputs or outputs are placed on a Printed Circuit Board (PCB). Based on the minimal Boolean expression,
required gates and their interconnections are chosen that can be realized easily with minimum number of
gates on a PCB. The advantage of this type of realization is that the design is easy to implement. However,
the disadvantage is that the design is neither scalable nor cost effective due to the wastage of hardware
resources.
Now the question arises that is there any alternative to realize only the terms represented in the SOP, POS,
or FF form that leads to the effective utilization of hardware resources. This is an intuition behind the
invention of PLAs, which are devices used to realize any digital design.
Any digital circuit can be represented in either the canonical form or the standard form. The canonical
forms are of two types: sum of minterms and product of maxterms. Similarly, standard forms are of two
types: SOP and POS. To realize a design in the SOP or POS form, a set of AND gates and OR gates is
required. This concept has become the basis of introduction of PLAs. Figure 8.2 shows the PLA
architecture:

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 IC Design

Figure 8.2: Displaying the PLA Architecture

As shown in Figure 8.2, PLA consists of a sequence of AND gates and a sequence of OR gates. These
sequences are called programmable planes, namely AND plane and OR plane. The AND plane consists of
programmable interconnects along with the AND gates. Similarly, the OR plane consists of programmable
interconnects along with the OR gates. The AND plane consists of vertical and horizontal lines. Vertical
lines represent the inputs in the complemented and un-complemented forms. All the vertical lines are
connected across these horizontal lines. The interconnect points are called crossover points, which are
used to configure the function of each product term. Similarly, in case of OR plane, horizontal lines
represent the output lines. The vertical wires are used to connect the AND terms. Initially, crossover
points are not electrically connected. For a desired combination of product terms, these crossover points
are configured or connected electrically. With this method, the efficient utilization of resources is achieved.
In Figure 8.2, each horizontal line in the AND plane represents one minterm and each vertical line in the
OR plane represents each OR term. Therefore, the number of horizontal lines in the AND plane for a three-
input PLA is eight. The AND gate has one input and each OR gate has one output. Is it possible to have
one input AND gate? No. However, three inputs are hooked to the same wire to an AND gate for diagram
simplification. Each of AND gate with three input wires, which is what it is in reality (there is as many
input wires as variables). Again, a single wire into the OR gate is a combination of product terms. These
SOP terms may be maximum of eight, so there are eight wires. We use the same simplification to make it
easier to read such that the horizontal wires make up the OR plane.
Let us take an example to understand how PLA is used to implement a combinational circuit. Consider
three functions, F1, F2, and F3, which are represented in the SOP form. Realize the combinational circuit
with three functions given as,
F1 = ab' + bc
F2 = ab + ac'
F3 = bc + ac'
To generate the product terms, given functions are minimized using Boolean optimization methods. The
given combinational circuit is converted into minimal SOP terms. To represent these functions, six product
terms need to be generated using the AND plane. However, as we observe the functions, there are two

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common product terms, namely bc and ac'. The number of product terms in the AND array to be
implemented are ab', ab, bc, and ac'. Therefore, only four product terms are required to implement using
the AND plane. Four product terms, p0, p1, p2, and p3 hold the expression as follows:
p0= ab'
p1= ab
p2= bc
p3 = ac'
These four product terms are configured in the AND plane. The p0 term is represented as a black dot at
crossover point where vertical lines of x and y variables intersect with the horizontal line. Similarly, p1, p2,
and p3 are denoted as black dots on the AND plane. The terms that are generated using OR plane are F1,
F2, and F3, given as follows:
F1 = p0 + p2
F2 = p1 + p3
F3 = p3 + p2
Using PLA, only the required terms are generated. Simplification to the number of product terms is the
feature of PLA. In addition, the AND array is used which is fully utilized. As per the transistor
technology, NAND or NOR gate is used to implement these devices instead of AND or OR gate array.
One of the features of PLAs is that both AND and OR planes are programmable during manufacturing.
However, the difficulty in these devices is that finding common factors in large designs are impractical.

PLDs
PLDs are used to realize digital designs with AND and OR planes. Major difference when compared with
PLA devices is in the programming of AND and OR planes. In case of PLAs, both AND and OR planes are
programmable; whereas, in PLDs, either one of the planes is programmable or both the planes are fixed.
Programming technology is initiated in Read Only Memories (ROMs) to store the information. This
information is stored by programming the wires based on the address lines. These are one time
programmable and are fixed. In this case, fixed implies that bits cannot be changed once they are
programmed. In other words, these devices are not reconfigurable. Developments on these devices are
initiated to implement the combinational designs.
ROM consists of m-inputs and n-outputs. It is also called hardwired truth table, as truth table is stored in
it. Any combinational circuit can be implemented using ROMs. Based on the functionality, the output of
the circuit can change. The truth table is considered to store in the ROM devices and the required
minterms are programmed or configured to realize the design. For example, consider a well-known
combinational design, 1-bit Full Adder. The input variables of this circuit are x, y, and z, and output
variables are sum and carryout. Sum and carryout function in terms of sum of minterms are as follows:
sum(x,y,z) = f (1,2,4,7) = x'y'z + x'yz'+xy'z'+ xyz
carryout(x,y,z) = f (3,5, 6, 7) = x'yz + xy'z + xyz' + xyz
In ROM devices, minterms are configured on the AND plane. Outputs are determined by combining
minterms, such as 1,2,4,7 for sum and 3,5,6,7 for carryout, on the OR plane. Truth table inside a ROM
determines these minterms. You need to program the device such that whenever the minterm
combinations 1, 2, 4, 7 are read as input, output line generates 1. Similarly, generation of carry signal
output takes place. Basically, it consists of an AND array whose input will be x, y, z and output will be
f(0,1,2,7). To combine these minterms into required sum and carryout, OR array is required. These devices
are called as programmable devices due to its configurability feature. The minterms of the given input can
be combined as per users choice, that is, different inputs can be configured or given to these devices. After

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the device is configured to 1-bit Full Adder function, it cannot be used for different designs. The
realization of 1-bit Full Adder is shown in Figure 8.3:

Figure 8.3: Displaying the Realization of 1-bit Full Adder

Programming minterms to OR plane is introduced in programmable ROMs called PROMs. If the program
can be erased and reprogrammed, then these devices are called Erasable Programmable ROMs (EPROMs).
Electrical pulses are used to erase the configuration in EPROMs. These EPROMs erase the whole design on
devices. However, Electrically Erasable ROMs (EEPROMs) are used to erase part of a design and reuse it
for further usage. For all these types of ROMs, the circuit from the board is to be taken out and erasing
process is to be performed. This erasing process is performed by shining an ultra violet ray on the device.
However, in EEPROM, the device stays in the circuit and can selectively alter the program wherever
required. EEPROM are also called Flash memories.
In general, if there are n-inputs, then 2n minterms are required, that is, 2n AND arrays are required.
Similarly, for m-outputs, m–OR arrays are required. Cost of the device is not at all considered in present
day technologies. However, the number of minterms being used by a given function will always be less
than total minterms. This leads to wastage of hardware resources. In other words, underutilization of the
device takes place. These devices are best choice for memory devices.
Programmable Array Logic (PAL) is an advanced version of PLA. As in PLAs, the logic circuit to be
designed is represented in the SOP form. In PALs, only the AND plane is programmable. Mostly, PALs
are used to implement decoders. A further enhancement in PALs is the addition of registers at the output
of the AND-OR terms that enables you to design sequential circuits using PAL. These refined PALs are
called PLDs. Figure 8.4 gives an idea of PLD structure:

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Figure 8.4: Displaying the PAL Architecture

All the devices, such as PROMs, EPROMs, EEPROMs, PLAs, and PALs, are examples of PLDs.
Complex PLDs (CPLDs) combine several PLDs into a single module, provide programmable interconnects
to connect PLDs, and configure the design. They consist of number of logic blocks and global
programmable interconnects. Each logic block comprises of macro-cell, PAL or PLA, and its supported
output channels. Global programmable interconnects allow connections to logic blocks and input-output
blocks. Block diagram of generic CPLD is shown in Figure 8.5:

Figure 8.5: Displaying the Generic Architecture of CPLD

FPGA
Ross Freeman, one of the founders of Xilinx, invented FPGA in the year 1984. Xilinx continues to be one of
the leading vendors of FPGAs. Due to the reprogramming feature, FPGA has become a very popular
device. FPGAs are programmable devices; therefore, to realize any digital design, end users can program
FPGAs. These devices are very popular due to their reprogrammable nature and short turnaround time.
FPGAs are advanced versions of CPLDs, where PAL structure of the logic blocks is replaced by
Configurable Logic Blocks (CLBs).

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 IC Design

A generic FPGA architecture consists of programmable logic elements called CLBs, programmable
interconnect, and input and output programmable pads (Figure 8.6). All these three can be configured
through programming. Each configurable logic block consists of logic elements that can be used to realize
the logic. An FPGA contains two-dimensional CLBs and a two-dimensional array of switching matrices to
connect the CLBs. Through programmable routing, CLBs can be interconnected. An FPGA can have more
than 10,000 CLBs. Programmable interconnects are used to establish connection between logic elements.
Other important resources, such as three-state buffers, registers and multiplexers in I/O blocks, and JTAG
boundary scan circuitry, are also included in FPGAs. Figure 8.6 shows the architecture of FPGA:

Figure 8.6: Displaying the Generic FPGA Architecture

FPGAs can be programmed dynamically only once or several times depending on their technology used to
manufacture. Based on the implementation of logic elements and programming technology in FPGAs,
these devices are categorized into the following types:
 Antifuse FPGA
 Flash FPGA
 Static Random Access Memory (SRAM) FPGA

Antifuse FPGA
In this type of FPGA, the programming is done by burning a set of fuses. This type of programming is also
called hard programmable FPGAs, antifuse FPGAs, or one-time programmable devices. After the chip is
configured, it cannot be modified. These FPGAs are mostly preferable in production systems, where
reconfiguring the FPGA in the field is not required. For payload applications in space, these devices are
used extensively.

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Flash FPGA
Flash FPGAs can be reprogrammed thousands of times. These types of FPGAs use flash-erase EROM
technology; therefore, these devices are also called soft programmable devices. These are non-volatile, that
is, even when the power is switched off, the configuration within these devices remains intact. The main
advantage of FPGAs is that they can be reconfigured or reprogrammed in the field. However, these
devices are costlier when compared with antifuse FPGAs.

SRAM FPGA
In this type of FPGA, programmable switch is used to configure designs. The state of switch is controlled
by SRAM bit. SRAM-based technology is most widely used in FPGAs, as these devices support in-
programmability and re-programmability. In this type of FPGA, when power is switched off, the
configuration is erased. To retain the configuration even during power failures, additional logic is
required. Therefore, additional circuitry is added to load the configuration into the FPGA whenever
power is switched on. This reconfiguration is done very fast.
Most of the current day commercial FPGA products are based on either SRAM or antifuse technologies.
Major commercial vendors of FPGA devices are Xilinx and Altera. In Xilinx terminology, a set of building
blocks of a logic circuit is called slice; whereas, in Altera terminology, it is called adaptive logic module.
The main advantages of FPGA are as follows:
 Design and implementation are easier and faster
 The size of the chip is small
 Reliability is higher
 Due to re-programmable nature of FPGAs, the component count is reduced
 It provides remote hardware or field programming by end users
 Risk and cost of development time is reduced
 Non-Recurring Expenditure (NRE) cost is low
 Testing process is easier when compared to PLDs
FPGAs have the following disadvantages:
 Power consumption is high and slow
 The production cost is high as compared to Application Specific Integrated Circuits (ASICs)
 There will be an overhead (in terms of logic circuitry) as some portion of FPGA is not available for
user programming
FPGAs are extensively used for the design of both prototypes and production systems. Some typical
applications of FPGAs are as follows:
 In major research and development projects of telecommunications, networking, software radio, and
process control to develop fast prototypes
 In pre-production systems where the product has to be launched early to avoid competition
 In production systems where the production volumes are not very high and the ASIC development
cost is not justified

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ASIC
ASIC is an integrated circuit designed in such a way that it meets the exact requirements for a specific
application. ASIC is a fully customized device. If you need to design an electronic component as a
dedicated component for a specific task, then ASICs are the best choice; for example, mobile phones and
smart phones. Moreover, if you are developing a product that will have a mass market, such as an MP3
player or a set top box, then you can design an ASIC. The advantages of an ASIC are as follows:
 Very low production cost if the ASIC is for a mass market
 Best utilization of the resources on the chip as compared to FPGA
 Optimized for a specific application; and therefore, power consumption and size can be less
On the downside, ASIC has the following problems:
 Initial development cost is very high, that is, design, verification, and physical chip design will take a
lot of time and expertise
 The final ASIC fabrication will be done by a third party having the chip making facility

Selection of an Appropriate Integrated Circuit

When an application is realized, speed, recurring and manufacturing cost, and quantity plays a vital role
to consider the selection of various devices. CPLDs, FPGAs, and ASICs devices developed by commercial
vendors, such as Xilinx Corporations and AT&T electronics, are used to realize the designs. However,
Computer Aided Design tools automate the FPGA and ASIC design flows to make an efficient design.
Based on the quantity of product, type of application, speed requirements, and production time need to
be considered to select the appropriate device.
Whether an FPGA or ASIC is suitable for an application depends on the quantity. If the quantity is 20,000
to one million, an FPGA makes sense. If the quantity is 100,000 to about three million or sometimes five
million, structured ASIC will be cost effective. If the quantity is more than three or five million, then a
traditional ASIC will be cost effective.
Applications can be broadly categorized as embedded system applications, network applications, and
robotic applications.
Storage is one of the basic requirements in computing field. For the following memory devices, ASIC
devices are the best choice:
 FIFO buffer
 DRAM memory controllers
 Printer controller devices
 Graphic interface cards
 Telecommunications application devices
FPGAs are suitable for applications where speed of the device is not a major concern. For prototyping,
remote sensing application, and embedded system applications, these devices are used to configure the
required functionality.

Summary
PLDs are used to implement any digital design with the help of AND and OR planes. The combinational
circuits are represented in either canonical or standard forms. Standard form expressions, SOP or POS, are
realized using AND plane and OR plane. Based on the programmable features of AND and OR planes, the
devices may vary. The PLDs, such as ROM, PROM, EPROM, and EEPROM, are all fixed AND and OR
planes. Both AND and OR planes are programmable in PLA devices. These PLA devices are used in

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FPGAs. PAL devices consist of fixed AND plane and programmable OR plane. Combining these PLDs
forms various devices, such as CPLDs, FPGAs, and ASICs. These devices vary in programming feature
and the configuration technology. Different programming technologies for FPGAS are soft and hard.
Widely used devices are FPGAs and ASICs due to manufacturing cost and speed.

Questions
1. Draw the PLA structure for the function F1 = xy + yz+ x'z.
2. Distinguish between PROM and PLAs.
3. Write the application of CPLDs.
4. Explain the architecture of generic FPGA.
5. Write the advantages of ASICs over FPGAs.

Exercises
1. Implement the given function using PLDs
F = xyz + y'z' +x'y'
2. Draw the structure of PLA to implement the functions:
F1(x,y,z) = yz + x
F2 (x,y,z) = xy + x'y'z'
3. Design a procedure for the selection of appropriate integrated circuit for an embedded system
application.

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FPGA Design Process
If you need an information on: See page:
Architectures of Popular FPGAs 154
Choosing an FPGA 156
FPGA Design Process 159
FPGA Families of Different Vendors 163
FPGA Design Examples 164
Chapter 9

As Field Programmable Gate Array (FPGA) devices are becoming more and more versatile and flexible,
the use of these devices is also increasing. Choosing a specific FPGA for a given application is not an easy
task. In this chapter, you learn about the intricacies of selecting an FPGA, the FPGA design process, and
the precautions to be taken for designing a Printed Circuit Board (PCB) with FPGA. In addition, FPGA
design process is illustrated with few examples.

Architectures of Popular FPGAs

FPGAs have become prevalent in Very Large Scale Integration (VLSI) designs not only as prototyping
devices but also as substitutes for Application Specific Integrated Circuits (ASICs). Due to their
reconfigurable feature, FPGAs are found in extensive applications that include avionics and space
applications. In addition to reconfigurability, other benefits of FPGAs include instant turnaround due to
shorter design and production time, lower setup cost, and lower risk. Though the applications configured
on FPGAs are generally slower and consume more power as compared to ASICs, reduced development
cost and time have made FPGAs an excellent alternative to custom ASICs for medium to low volume
products. The Xilinx company has introduced FPGA in 1985. Thereafter, companies, such as Actel, Altera,
Quicklogic, and Algotronix, have introduced various types of FPGAs. The most common FPGA
architecture and its logical components are discussed in detail in the next subsection.

Basic FPGA Architecture

The most common FPGA architecture consists of three programmable components: logic blocks, input
output blocks (I/O blocks), and switch blocks (Figure 9.1). The given digital circuit can be programmed by
configuring the logic blocks and the routing resources, namely the switch blocks and I/O blocks. The
digital circuit is decomposed into smaller sub-circuits such that each element can be mapped onto a logic
block in the FPGA. The required connectivity is realized by programming the routing resources. The
horizontal and vertical lines called tracks represent the routing channel resources. The logic block is
capable of implementing combinational and sequential logic of different complexities. Switch block acts as
an interconnection block to connect vertical and horizontal channels.
The logic block is a basic functional unit in FPGA. The most common approach of implementing the basic
logic element is by using a 2k- bit Static Random Access Memory (SRAM) cell, which represents a k-input
one-output Look Up Table (LUT). This k-LUT is capable of implementing any Boolean function of k-
variables. Some of the major vendors for LUT-based FPGAs are Xilinx and Altera. Figure 9.1 shows the
most common FPGA architecture:

Figure 9.1: Displaying the Basic FPGA Architecture

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An LUT-based logic block consists of LUTs, flip-flops, multiplexers, and latches (Figure 9.2). These LUTs
are programmed to realize any n-variable Boolean function. As the k-input LUT inside a logic block can be
programmed to realize any of the 2m Boolean functions where m = 2k, the logic blocks are also called
Configurable Logic Blocks (CLBs). The CLBs in modern FPGAs have more than one LUT; for example,
CLBs in the Xilinx Virtex-4 family contain eight four-input LUTs. Most of the commercial FPGAs, such as
Xilinx and Altera, have four-input LUTs as logic blocks. Figure 9.2 shows an LUT-based logic block:

Figure 9.2: Displaying an LUT-Based Logic Block

For example, the two-variable Boolean function (a’+b) is realized with LUT, as shown in Figure 9.3:

Figure 9.3: Displaying a Two-Input LUT Realizing the Function (a’+ b)

In Figure 9.3, the truth table is listed for four input combinations, such as 00, 01, 10, and 11, where the
input variables are a and b. The corresponding output is considered based on the Boolean function (a’+ b).
A logic block can also be implemented using multiplexer–based logic function, where multiplexers are
basic logic circuits to realize the Boolean function. In other words, the multiplexer-based logic block is
realized using multiplexers. Multiplexers are generic structures that can be used to realize any logic
function. A multiplexer can be configured to implement different logic functions by connecting its select
and/or data lines to different signals. For example, a 2 x 1 multiplexer with data inputs as w and x and
select input as s1 implements the logic function (w.s1 + x.s1’ ). An example of multiplexer logic block with
three 2 x 1 multiplexers and a logic OR gate is shown in Figure 9.4:

Figure 9.4: Displaying the Multiplexer-Based Logic Block

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In Figure 9.4, the logic block is implemented by using three multiplexers, where the input variables are w,
x, y, z and output is f with S1, S2, S3, and S4 as select lines.

Choosing an FPGA
The first step in the process of FPGA selection is to identify your area of application, that is, whether it is
aerospace and defense applications or commercial applications.
For aerospace and defense applications, FPGAs need to work under harsh environmental conditions, such
as very high or low temperatures or very high humidity. Therefore, FPGAs that meet these requirements
are very few as compared to those that can be used for commercial applications.
The second step in narrowing down your search for the right FPGA is answering the following questions:
 Is the FPGA for general logic implementation?
 Is the FPGA for an embedded system implementation?
 Is the FPGA for implementing signal processing functions?
Depending on your answer, a vendor recommends a few families of FPGAs or a small set of components
within each family.
The next step is to identify the FPGA’s that meet your needs in each of the families.
For example, Xilinx gives a number of families, such as Vertex.
The various parameters that need to be taken into account are:
 Input voltage (5, 3.3, 2.5, 1.8)
 Number of gates
 Macro cells
 Clock
 Number of pins
 Package type: Plastic Leaded Chip Carrier (PLCC), Plastic Quad Flat Package (PQFP), Very Thin
Quad Flat Package (VTQFP), Thin Quad Flat Package (TQFP), Ball Grid Array (BGA), and Fine Pitch
Ball Grid Array (FBGA)
Let’s now learn about intellectual property cores, which are popularly known as IP cores.

IP Cores
In software development, you can use library functions. These library functions make development faster
as you do not have to write everything from scratch. Similarly, while designing FPGAs, IP cores are
available to implement commonly used functions in them.
IP core can be defined as a reusable unit of logic design. It is an intellectual property of the party who
developed it; and therefore, the name IP core. A large number of vendors offer IP cores for a price in the
following two forms:
a. Netlist, which can be ported to a different target FPGA. It cannot be reverse engineered; and
therefore, the IP is protected.
b. Hardware Description Languages (HDL) code, which is a synthesizable version of the IP core; and
therefore, it can be modified as per your requirements.
These IP cores are also called soft cores.

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Manufacturers of FPGAs
Manufacturers, such as Xilinx and Altera, provide IP cores, but they are very limited. Microblaze is a
software-based embedded processor from Xilinx. NIOS is a software-based embedded processor from
Altera. FPGA manufacturers also provide IP cores for more powerful embedded processor cores for AVR
and PowerPC.
A large number of 3rd party vendors provide IP cores. Each vendor may specialize in a specific area given
as follows:
 Processing—Processor cores such as Z80 and 8085Connectivity or Interfaces: RS232, I2C, and Ethernet
 Communication—Network protocol stacks, error detection and correction, and encryption
 Telecommunications—Modulations, demodulations, interleaving, digital up-conversion, digital
down-conversion, and direct digital synthesis
 Digital Signal Processing—Filters, decimation and interpolation, and FFT analysis
 Coding—Audio compression and video compression
Open source is made available mostly in VHDL or Verilog on the Internet. You can check at the website
www.opencores.org if any core that meets your requirement is available.
If you are a manager working on a project that uses FPGA with strict deadlines, then you need to consider
the option of buying the IP cores for implementing complex functionality in the FPGAs. This will save lot
of time; however, if the engineers start developing from scratch, then they will take lot of time for coding
and testing.

FPGA Configuration
FPGA is a reconfigurable device. However, as FPGA is based on SRAM technology, it is volatile, that is,
when power goes off, it has to be reprogrammed. On the other hand, Complex Programmable Logic
Devices (CPLDs) are non-volatile, as they are based on Electrically Erasable Programmable Read Only
Memory (EEPROM) or Flash cell technology.
Following two options can be used to configure an FPGA:
 Configure the FPGA directly using a cable during development
 Program a CPLD or Programmable Read Only Memory (PROM) by loading the configuration data
into the CPLD or PROM and then loading the configuration data onto the FPGA during production
models
When you want to program an FPGA using PROMs, the configuration data for the FPGA is stored in the
PROM. PROMs are of two types:
 One Time Programmable (OTP) ROM
 In System Programmable (ISP) ROM (platform Flash)
If you do not need ISP capability, you can use OTP ROM and use in the production model PCB.
Otherwise, you need to use ISP ROMs. Figure 9.5 shows the process of configuring an FPGA:

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Figure 9.5: Configuring the FPGA

When the design entry is done using VHDL or Verilog, EDIF netlist file is created. This design is then
fitted into the specific FPGA or CPLD architecture and a bit-stream file is generated. This file can be of
different forms depending on the device:
 For FPGAs, the file will have .bit extension
 For CPLDs, the file will have .jed extension
 For PROMs, the file will have .mcs, .exo, or .tek extension
The FPGA vendor supplies the necessary software, such as Xilinx Integrated Software Environment (ISE),
to generate these configuration files. All you need is the software and a cable to connect to the device. For
example, if you are configuring FPGA through a Joint Test Action Group (JTAG) cable, you need to
connect the JTAG cable to the FPGA JTAG port and download the .bit file onto the FPGA from a personal
computer.

Configuration Modes
A number of modes in which the devices can be configured are given as follows:
 JTAG—Refers to a mode, which can be used to program FPGA, CPLD, and PROM. It is done using a
JTAG cable. The JTAG mode is a serial programming mode in which data is loaded one bit per test
clock tick. This mode is also called Boundary Scan mode.
 Master-Serial—Refers to a mode, which is used to load the configuration data from a serial PROM to
an FPGA. This mode is also a serial mode in which data is loaded one bit per clock tick. The FPGA
itself provides the clock by using its internal oscillator that drives the configuration clock. Therefore,
in this mode, FPGA loads itself with the data in the PROM.
 Slave-Serial—Refers to a mode in which an external clock from a microprocessor or another FPGA is
used to load the configuration data into an FPGA. In this mode, the loading is done one bit per clock
tick.
 Slave-Parallel—Refers to a mode in which an external clock from another microprocessor or FPGA is
required. The data transfer is done byte wise rather than bit-by-bit; and therefore, transfer is faster.
This mode can be used if the configuration speed is important.
JTAG and Master-Serial are the most widely used modes.

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FPGA Design Process

The process of configuring a design onto an FPGA can be broken into several stages. A typical Computer
Aided Design (CAD) flow for FPGA would include software tools for the tasks, such as initial design
entry, logic synthesis, placement and routing, and programming the design into the FPGA. The complete
FPGA-based design flow is described in Figure 9.6. As mentioned earlier, CAD tools are essential for
configuring the circuits into FPGAs. Popular tools are ISE from Xilinx, Modelsim from Mentor Graphics
and Quartus software from Altera. The hardware design to be implemented into an FPGA is described
using either schematic diagrams or HDL. Different stages of the FPGA-based design flow are described in
the following subsections.

FPGA Design Flow

Figure 9.6 shows the complete FPGA-based design flow:

Figure 9.6: Displaying the FPGA Development Process

Designing an FPGA involves the following stages:
 Design entry: The system design can be entered using an HDL editor (when VHDL or Verilog is used
for the design) or a graphical editor that allows you to create Finite State Machines or block diagrams.
The graphical editor will automatically generate the corresponding HDL code.
 Behavioral simulation: This stage is similar to the compilation of a programming language code. A
behavioral simulator interprets the HDL code. The various signals and variables can be observed,
breakpoints can be set, and procedures and functions can be traced. This stage helps in the
understanding of design. In this stage, we will not take into consideration the target FPGA device.
The resource utilization and timing are also not considered.
 Synthesis: It is a process of converting the HDL to a netlist. Using basic building blocks, such as
adders, registers, and multiplexers, the netlist represents the actual circuit diagram.
 Post-synthesis simulation: It verifies whether the result at this stage differs from the behavioral
simulation result. If the result differs, then the reasons are probed and any issues are resolved.

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 Implementation: In this stage, the netlist is converted into a bit stream corresponding to a target
device. The complete design is described in terms of the primitives of the target architecture and all
the instances are assigned to physical locations. This is done iteratively as timing constraints need to
be met during the implementation process.
 Timing simulation: Ideally, test benches are written to check whether the necessary timing
constraints are met, particularly for critical paths. However, writing test benches is a very involved
task.
 Static timing analysis: This can be done easily by computing the actual timing with the constraint
imposed on the design.
Perform the following steps to download the VHDL source code onto an FPGA device:
1. Write the VHDL source code. The VHDL code to display the decimal digit using LED output is
shown in Figure 9.7:

Figure 9.7: Displaying the VHDL Source Code

2. After simulation, synthesis, and post synthesis, the VHDL code is transformed into a netlist, as shown
in Figure 9.8:

Figure 9.8: Generating a Netlist from the VHDL Code

3. After the synthesis stage in the FPGA design flow, the implementation stage performs actual
placement and routing of the logic blocks based on some heuristic algorithms to optimize the wire
length and absolute path delays to meet the timing constraints. The flow of placement and routing
stage generates bit stream and loads it into a board, as shown in Figure 9.9:

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Figure 9.9: Displaying the Implementation Stage after the Synthesis Stage

Designing FPGA-Based PCBs

To develop a system using an FPGA, you need to develop hardware—a PCB that contains the FPGA along
with all other components required to achieve the functionality. As FPGA devices have a large number of
pins, you need to be very careful in designing the PCB. The various process steps to design FPGA-based
PCB are shown in Figure 9.10:

Figure 9.10: Designing FPGA–Based PCB

Description of these steps is given as follows:
 System specifications—To start with, the overall specifications of the system need to be worked out.
These specifications are inputs, outputs, and the processing to be done on the board. You can embed a
lot of logic in an FPGA; however, unless the detailed specifications are worked out, you cannot
determine the additional required circuitry. A block diagram that gives the overall functionality is
also developed at this stage.

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 Preliminary design—At this stage, you need to identify various components to be used in a PCB. You
also need to select the specific FPGA to be used. As discussed earlier, you need to select an FPGA
based on the resources required on the device. You also need to study the factors, such as device
packaging and number of pins, as these factors affect the production cost of the PCB. While you are
carrying out the design, it is very important to keep in mind the design for test philosophy. Your
design should be such that it is not difficult to test the PCB during the production stage and
maintenance. In a PCB with a large number of components, you need to identity the important test
points. In the FPGA, you need to plan for writing built-in-test logic so that the FPGA can be tested
easily.
 Detailed Design—At this stage, you need to work out the detailed circuit diagram. For the FPGA,
you need to perform the following:
 Input or output identification.
 FPGA pin assignment.
 Clock generation and distribution. Note that clock is a source of cross talk and EMI. The Digital
Clock Management (DCM) circuitry in the FPGA should be made effective.
 Power supplies required for FPGA core, I/Os, and reference.
 Estimate the power dissipation. This is a specialized activity called thermal management. You
need to take expert advice on this aspect, as this will have an impact on the PCB design. If the
power dissipation is high, you may need to provide a cooling arrangement, such as fan.
 Static timing analysis to analyze the timing margins.
 Signal Integrity Analysis (SIA) is performed to find out the distortion caused when the signal
travels through the FPGA, crosstalk effects, and EM radiation, and how to overcome it. This
analysis provides the inputs for placement and routing tool.
 PCB design—PCB design with an FPGA onboard is a challenging task as FPGAs are devices with
large number of pins and packaging, which is difficult to handle. As a result, the number of layers is
going to be high (typically eight and above). The cost goes up and testing and debugging the PCB
becomes difficult as the number of layers increases. Therefore, experienced professionals need to take
up the PCB design. Particular care needs to be taken if the PCB has to accommodate both analog
circuitry and digital circuitry (as in the case of all the telecommunication systems). The analog and
digital grounds need to be separated.
 PCB assembly and test—PCB assembly and testing become easy if you follow the design for test
principle; else, life is tough. You need to test the PCB part-by-part rather than assembling all the
components in one shot.
 Production model—You can launch the production model after the prototype is working correctly.
The cost of production model will be much lower than the prototype, as you are likely to procure the
components in large quantities; and therefore, the cost per device will work out to be low. You need
to consider this while doing the design.

FPGA power dissipation depends on a number of factors, such as resources used, I/Os, and clock. Tools, such as Xilinx
XPower, are available to estimate the power dissipation of the FPGA.

After synthesizing and simulating, the last step is configuring the FPGA.
Xilinx gives in-system programmable Platform Flash configuration memories, such as PROM, to simplify
configuration process.

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In designing and developing systems using FPGA, the design and verification go hand in hand.

FPGA Families of Different Vendors

When you develop FPGA-based hardware, you need to identify the specific FPGA that you are going to
use in the hardware. For that, you should know about the leading vendors of the FPGAs.
The leading vendors of FPGAs with their website are as follows:
 Actel www.actel.com
 Altera www.altera.com
 Atmel www.atmel.com
 Lattice Semiconductors www.latticesemi.com
 Xilinx www.xilinx.com
If your organization is implementing FPGA-based system for the first time, then you need to do a lot of
window shopping to find out which vendor’s product suits you. Due to the immense competition, all the
vendors have comparable products; and therefore, you might have a tough time selecting a vendor. It is
not just the suitability of a specific FPGA for your application, but you also need to consider the following
factors while selecting a vendor:
 If the vendor has an office in your location, it would be very beneficial, as you will get the necessary
technical support. However, sometimes, the local presence may not be that important, as some
vendors provide excellent support through their websites.
 Some vendors may have local presence, but the support may not be good; therefore, reputation of the
vendor to provide technical support is a crucial factor. This can be ascertained through your
professional network.
 The training provided by the vendor is another important factor.
 The availability of the development boards from the vendor. For your specific requirement, it is likely
that the FPGA vendor will also have a development or evaluation board that can be used to develop
your prototype.
 A vendor who gives the reference designs of their evaluation boards can be preferred.
 Every vendor will have a large number of FPGAs from which you have to select the required FPGA
depending upon your requirements. Some vendors provide support and tools to select the right
FPGA that suits your requirement. Such vendors should be preferred.
 When you buy FPGAs in small quantities (say, two or three), they are going to be very costly.
Therefore, you need to assess your requirements in the long run (the production model of your
system) and then check which FPGA suits your budget. Prefer the vendor who supports your
prototyping or research work initially.
After the vendor is short-listed and you develop a good rapport with its representative, the rest of the
development process will commence.

Illustration: FPGA Families of Xilinx

In Xilinx Vertex 4 family of products, the logic sources are arranged in slices. Each slice consists of the
following components:
 LUT
 Multiplexers
 A Boolean logic block
 An adder or subtractor with a carry or borrow function

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Four such slices make up a CLB, which is the basic unit to create combinatorial logic or sequential circuits.
In this family, the following three groups of series are available:
 LX series—Refers to a series that is used for implementing logic and I/O functions.
 SX series—Refers to a series that is used for implementing digital signal processing functions. Slices
in the series are called digital signal processing slices.
 FX series—Refers to a series that have a PowerPC core and memory.
The latest series of Xilinx FPGAs are the Virtex 5 series. These FPGAs have capacities of 12 million gates
and 330,000 logic cells. The three families of the FPGAs are as follows:
 Virtex 5 LXT for high performance logic
 Virtex 5 SXT for digital signal processing
 Virtex 5 EXT for embedded processing
 Virtex-7 FPGAs for ASIC emulation

FPGA Design Examples

The VHDL code with simulation results giving details about the number of logic elements in terms of
LUTs using Xilinx ISE simulator tool is been given.
In addition, the implementation of data structures, such as stacks, queues, and shift register, using VHDL
is been discussed.

Stack Implementation using VHDL

In a stack, the data that enters last will come out first. Therefore, it is known as Last In First Out (LIFO)
data structure. In addition, you need to know when the stack is full or empty, as you cannot input data
when the stack is full or take out data when the stack is empty.
You can implement a stack using Dual Port Random Access Memory (DPRAM) as a component. The
DPRAM is a 4-bit wide, 16 depth dual port RAM with "port a" is write only and "port b" is read only. The
addresses for memory location for "port a" and "port b" are generated by up-down counter when both
write (wr) and read (rd) signals are high. Write address is the current value of counter. For the next write
operation, the counter will generate address by counting up. Similarly, when both read and write signals
are low, reading will take place at current value of counter and it generates the address for the next read
operation by counting down. When other than these combinations of values of read and write are given,
the current value of counter is latched; and therefore, all the operations will take on that memory address
only for these combinations of read and write. The block diagram of stack is shown in Figure 9.11:

Figure 9.11: Displaying the Block Diagram of Stack

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The input ports in the block diagram are as follows:

 clk : Clock
 rst : Active high reset
 cs : Chip select
 wr : Write enable for port a
 rd : Read enable for port b when rd is zero
 datain : Data input to the stack
The output ports in the block diagram are as follows:
 full : Active high signal; high when all the memory locations are written
 empty : Active high signal; high when all the memory locations are empty
 dataout : Data output when rd is zero from memory location address by read counter

VHDL Implementation
Following is the VHDL implementation of the stack:
-- File name: Stack.vhdl
--
-- Create Date: 17:10:26 07/05/2007
-- Module Name: Stack
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 8.2i,ModelSim SE 6.0

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------
--library declaration

library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--entity declaration

entity Stack is

generic (width : integer := 4; -- no. of bits input

addloc : integer := 4);-- depth of stack in 2's power(2**depth)

--input ports

port (wr : in std_logic; -- write enable

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rd : in std_logic; -- read enable

clk : in std_logic; -- clock
rst : in std_logic; -- reset
cs : in std_logic;

-- data input output ports

datain : inout std_logic_vector((width -1) downto 0);

empty : out std_logic; --high when stack is empty
full : out std_logic; -- high when stack is full

dataout : out std_logic_vector((width -1) downto 0)

);

end Stack;

--architecture declaration

architecture StackArch of Stack is

-- component instantiating(dual port ram)

--signal declaration

signal dataouttemp : std_logic_vector((width -1) downto 0);

signal top : std_logic_vector((addloc -1) downto 0); -- address
pointer
signal wrtrd : std_logic_vector(1 downto 0);
signal cnt : std_logic; -- control signal
signal cnt1 : std_logic; -- control signal
signal delay : std_logic; -- control signal
signal fulltemp : std_logic;
signal fulltemp1 : std_logic;
signal emptytemp : std_logic;
signal emptytemp1 : std_logic;
signal rddpram : std_logic;
signal wrdpram : std_logic;
-----------------------------------------------------------------------
--component declaration(DPRAM)

component dpram

-- Generic declaration

generic (width : integer := 4;

addloc : integer := 4);

--input ports
-- address inputs, write enable, read enable, chip select, async reset, clock

port(adda : in std_logic_vector((addloc -1) downto 0);

addb : in std_logic_vector((addloc -1) downto 0);
wra : in std_logic;
wrb : in std_logic;

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 FPGA Design Process

cs : in std_logic;
rst : in std_logic;
clk : in std_logic;

-- data input ports

ainout : inout std_logic_vector((width -1) downto 0);

-- data output ports

binout : inout std_logic_vector((width -1) downto 0)

);

end component;
--------------------------------------------------------------

begin

-- port mapping of dpram

dualpram:dpram generic map (width => width,

addloc => addloc)
ort map (adda => top,
addb => top,
wra => wrdpram,
wrb => rddpram,
cs => cs,
rst => rst,
clk => clk,
ainout => datain,
binout => dataouttemp
);

wrtrd <= wr & rd; --combining read write operations

-- dpram write enable

wrdpram <= '1'when (wr = '1' and fulltemp1 = '0') or wrtrd ="10" else '0';

-- dpram read enable

rddpram <= '0'when (rd = '0' and delay = '0') or wrtrd ="10" else '1';

fulltemp <='1'when (wrtrd ="11" and (conv_integer(top) = ((2**addloc)-1) and

cnt1 = '1' ))

else '0'; -- indicates that stack is full

emptytemp <='1'when ((wrtrd = "00") and (conv_integer(top) =0)) or (cnt ='0'

and wr = '0' )

else '0'; -- indicates that stack is empty

process(clk,rst) --process

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begin

if rst='1' then

emptytemp1 <= '1';

fulltemp1 <= '0';
cnt <= '0';
cnt1 <= '0';
top <=(others => '0');

elsif clk'event and clk='1' then

emptytemp1 <= emptytemp;

fulltemp1 <= fulltemp;

case wrtrd is

when "10" => -- read and write are taking place at same time
top <= top;

when "11" => -- write operation

cnt <= '1';
cnt1 <= '1';

if fulltemp='0' then
top <= top + '1'; -- write operation incrementing address pointer
cnt <= '1';

else
top <= top;

end if;

when "00" => -- read operation

if cnt = '1' and emptytemp='0' then

top <= top - '1'; -- read operation decrementing address

pointer
else
top <= top;

end if;

when others =>

end case;

end if;

end process;

process(clk,rst) --process

begin

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 FPGA Design Process

if rst ='1' then

delay <= '1';

elsif clk'event and clk ='1'then

if emptytemp ='1' and emptytemp1 ='1' then

delay <= '1';

else
delay <= '0';

end if;

end if;

end process;

empty <= emptytemp;

full <= fulltemp;

dataout <= (others =>'Z') when fulltemp1 ='1' or delay ='1' else dataouttemp;

end StackArch ;

Device Utilization Summary

Following is the device utilization summary of the stack implementation:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 86 5472 1%

Number of Slice Flip Flops 90 10944 0%

Number of 4 input LUTs 165 10944 1%

Number of bonded IOBs 15 240 6%

Number of GCLKs 1 32 3%

Figure 9.12 shows the simulation results of the stack:

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Chapter 9

Figure 9.12: Displaying the Stack Simulation Results

Queue Implementation using VHDL

Queue is a First In First Out (FIFO) data structure. Data that enters first will go out first from a queue.
When a queue is full, you cannot input data in it; similarly, you cannot take out data when the queue is
empty. In addition, you need to know whether the queue is full or almost full, and whether the queue is
empty or almost empty.
You can implement a queue using DPRAM as a component. As already learned, DPRAM is 4- bit wide, 16
depth dual port RAM with "port a" being write only and "port b" being read only. The address for memory
location for "port a" is generated by write counter as it is write only port. Similarly, read counter generates
the address for “port b”. Figure 9.13 shows the block diagram of a queue:

Figure 9.13: Displaying the Block Diagram of Queue

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 FPGA Design Process

The input ports in the block diagram are as follows:

clk : Clock
rst : Active high reset
cs : Chip select
wr : Write enable for port a
rd : Read enable for port b when rd is zero
inputdata : Data input
The output ports in the block diagram are as follows:
almostfull : Active high signal; high only when one memory location is left empty
during the write process
almostempty : Active high signal; high only when one memory location is left to be read
full : Active high signal; high when all the memory locations are written
empty : Active high signal; high when all the memory locations are empty
output(3 downto 0) : Data output when rd is zero from memory location address by read
counter

VHDL Implementation
Following is the VHDL implementation of the queue:
-- File name: Queue.vhdl
-- Create Date: 10:01:36 07/06/2007
-- Module Name: Queue
-- Project Name: VLSI LAb
-- Target Devices: xv4vfx12-10sf363
-- Tool versions: ISE 8.2i,Model Sim SE 6.0
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------
--LIBRARY DECLARATION

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

--entity declaration

entity Queue is

-- GENERIC DECLARATION
generic (width : integer := 4;
addloc : integer := 4
);

-- INPUT PORTS

port (clk : in std_logic; -- CLOCK

rst : in std_logic; -- RESET

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cs : in std_logic; -- CHIP SELECT

wr : in std_logic; -- WRITE ENABLE
rd : in std_logic; -- READ ENABLE

inputdata : inout std_logic_vector((width-1) downto 0);

-- OUTPUT PORTS

almostfull : out std_logic;

almostempty: out std_logic;
empty : out std_logic;
full : out std_logic;
output : out std_logic_vector((width -1)downto 0)
);

end Queue;

--architecture Declaration

architecture QueueArch of Queue is

-- COMPONENT INSTANTITING(DUAL PORT RAM)

component Dpram

-- GENERIC DECLARATION

generic(width : integer := 4;
addloc: integer := 4);

-- INPUT PORTS

-- ADDRESS INPUT

port(adda : in std_logic_vector((addloc-1) downto 0);

addb : in std_logic_vector((addloc-1) downto 0);
wra,wrb : in std_logic; -- WRITE ENABLE
cs : in std_logic; -- CHIP SELECT
rst : in std_logic; -- ASYNCRONOUS RESET
clk : in std_logic; -- CLOCK INPUT

-- DATA INPUTOUT PORTS

ainout : inout std_logic_vector((width -1) downto 0);

-- DATA OUTPUT PORTS

binout : inout std_logic_vector((width -1) downto 0)

);

end component;

-- SUBTYPE DECLARATION

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 FPGA Design Process

subtype feinteger is integer range 0 to (2**addloc);

-- SIGNAL DECLARATION

signal adddecoder1,adddecoder2 : std_logic_vector((addloc - 1) downto 0);

-- TO DECODE THE NEW ADDRESS FOR NEXT DATA AFTER WRITE OR READ CYCLE

signal outputdata :std_logic_vector((width -1)downto 0); -- TEMP OUTPUT SIGNAL

signal fecounter : feinteger; -- COUNTER FOR FULL AND EMPTY
signal fulltemp : std_logic; -- TEMP FULL
signal emptytemp : std_logic; -- TEMP EMPTY

-- SIGNAL FOR READ AND WRITE

signal wrtrd : std_logic_vector(1 downto 0);

signal rddpram : std_logic; -- READ ENABLE FOR DPRAM
signal wrdpram : std_logic; -- WRITE ENABLE FOR DPRAM

begin -- QueueArch

----- PORT MAPPING OF DPRAM -----

Dulpram:Dpram generic map(width => width,

addloc => addloc
)
port map(adda => adddecoder1,
addb => adddecoder2,
wra => wrdpram,
wrb => rddpram,
cs => cs,
rst => rst,
clk => clk,
ainout => inputdata,
binout => outputdata

);

-- COMBINING READ AND WRITE

wrtrd <= wr & rd;

wrdpram <='1' when (wr ='1' and fulltemp = '0') else '0'; -- WRITE

rddpram <='0' when (rd ='0' and emptytemp = '0') else '1'; -- READ

---------------Queue Full---------------------
fulltemp <= '1' when fecounter = ((2**addloc) -1) and wr = '1' else '0';
almostfull <= '1' when fecounter = ((2**addloc) -2) and wr = '1' else '0';
---------------------------Queue Empty ---------
emptytemp <='1' when fecounter =0 and rd ='0' else '0';
almostempty<='1' when fecounter =1 and rd ='0' else '0';

full <= fulltemp;

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empty <= emptytemp;

process(clk,rst)

begin -- PROCESS CLK

-- ACTIVITIES TRIGGERED BY ASYNCHRONOUS RESET (ACTIVE HIGH)

if rst = '1' then

adddecoder1 <= (others => '1');
adddecoder2 <= (others => '1');
fecounter <= 0;

-- ACTIVITIES TRIGGERED BY RISING EDGE OF CLOCK

elsif clk'event and clk = '1' then

case wrtrd is

when "11" =>

if fulltemp = '0' then

adddecoder1 <= adddecoder1 + '1';

fecounter <= fecounter + 1;

else

adddecoder1 <= adddecoder1;

fecounter <= fecounter;
end if;

when "00" =>

if emptytemp ='0' then

adddecoder2 <= adddecoder2 + '1';

fecounter <= fecounter -1;
else
adddecoder2 <= adddecoder2;
fecounter <= fecounter;
end if;

when "10" =>

adddecoder1 <= adddecoder1 + '1';

adddecoder2 <= adddecoder2 + '1';

when others =>

end case;

end if ;

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 FPGA Design Process

end process ;
output<= outputdata;
end QueuArch;

Device Utilization Summary

Following is the device utilization summary of the queue implementation:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 189 5472 3%

Number of Slice Flip Flops 108 10944 0%

Number of 4 input LUTs 371 10944 3%

Number of bonded IOBs 17 240 7%

Number of GCLKs 1 32 3%

The simulation result of queue implementation is shown in Figure 9.14:

Figure 9.14: Displaying the Queue Simulation Results

Shift Register implementation using VHDL

Shift register shifts the input data either to the left or to the right. Figure 9.15 shows the block diagram of
shift register:

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Chapter 9

Figure 9.15: Displaying the Block Diagram of Shift Register

When the shiftlr port is 01, it is right shift and when the shiftlr port is 10, it is left shift. For any other value
of shiftlr, the output data is same as the input data.
The input ports in the block diagram are as follows:
 shiftlr(1 downto 0)—01 for right shift operation; 10 for left shift operation; for any other input, the
output is unchanged data
 load—When high, data is loaded in shift register; when low, shifting will take place
 rst—Active high reset
 clk—Clock
The output port in the block diagram is as follows:
 shiftout(4 downto 0)—Shifts data out when load is zero and shiftlr is selected to either left shift or
right shift

VHDL Implementation
Following is the VHDL implementation of the shift register:
-- File name: ShiftRegister.vhdl
-- Create Date: 12:39:37 07/04/2007
-- Module Name: ShiftReg
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 8.2i,ModelSim SE 6.0

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
------------------------------------------------------------------
--libarary declaration

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

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 FPGA Design Process

---- any Xilinx primitives in this code.

--library UNISIM;
--use UNISIM.VComponents.all;

--entity declaration

entity ShiftReg is

-- bits to be shifted in one clock should be less than the data width

generic (shiftby : integer := 1;

datawidth : integer := 5 -- no. bits coming in
);

-- input port

port (datain : in std_logic_vector((datawidth -1) downto 0);

-- input data

clk : in std_logic;
rst : in std_logic; -- reset
load : in std_logic; -- load data enable

-- (01)shift right,(10)shift left else no shift

shiftlr : in std_logic_vector(1 downto 0);

-- shifted output data

shiftout : out std_logic_vector((datawidth -1) downto 0)

);

end ShiftReg ;

--architecture declaration

architecture ShiftRegArch of ShiftReg is

--signal declaration

signal shifttemp : std_logic_vector((datawidth - 1)downto 0);

begin

process (clk, rst) -- process

begin

-- activities triggered by asynchronous reset (active high)

if rst = '1' then

shifttemp <= (others => '0');

-- activities triggered by rising edge of clock

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Chapter 9

elsif clk'event and clk = '1' then

if load ='1' then

shifttemp <= datain;

elsif shiftby = 0 then

shifttemp <= shifttemp;

else

case shiftlr is

when "00" =>

shifttemp <= shifttemp;

when "01" => -- shift right

shifttemp <= shifttemp((shiftby -1) downto 0) & shifttemp((datawidth -1) downto

shiftby) ;

when "10" => -- shift left

shifttemp <= shifttemp(((datawidth-1)-shiftby) downto 0) & shifttemp((datawidth-1)
downto(datawidth-shiftby));

when others =>

shifttemp <= shifttemp;

end case;
end if;

end if;

end process;

shiftout <= shifttemp;

end ShiftRegArch;

Device Utilization Summary

Following is the device utilization summary of the shift register:
Device Utilization Summary (estimated values)
Logic Utilization Used Available Utilization

Number of Slices 8 5472 0%

Number of Slice Flip Flops 5 10944 0%

Number of 4 input LUTs 15 10944 0%

Number of bonded IOBs 15 240 6%

Number of GCLKs 1 32 3%

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 FPGA Design Process

Figure 9.16 shows the simulation results of the shift register:

Figure 9.16: Displaying the Shift Register Simulation Results

Summary
This chapter focuses on FPGA architecture and design processing steps for system prototyping. Due to
reprogrammable feature, the FPGA devices become popular as a rapid prototyping device. The basic
architecture of FPGA consists of programmable I/O blocks, programmable logic blocks, and interconnects.
Logic block is a basic unit to realize any Boolean function from basic logic gates to complex combinational
circuits. Most FPGAs use a multiplexer-based logic block or LUT-based logic block as a basic logic
element. The multiplexer control inputs are used as logic inputs and the multiplexer inputs are strapped to
logic levels to implement the desired function. The SRAM-cell represents the k-input one-output LUT that
implements any Boolean function upto k-variables. Various commercial vendors that produce these
FPGAs are listed in the chapter. The procedure to implement the hardware on a PCB is also explained. The
FPGA design process is illustrated with examples using VHDL.

Questions
1. Explain the need of FPGA and its various applications.
2. Explain the basic architecture of FPGA.
3. Explain the functions of LUT-based logic block and multiplexer-based logic blocks.
4. Explain the design flow for FPGAs.
5. List the methods to choose an FPGA device for an embedded application.
6. What is meant by LUT? Realize a given Boolean function f(x,y,z) = xy + z by using LUT-based logic
block.
7. List the commercial vendors of FPGA devices.

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Exercises
1. Write a Verilog code to implement a n-bit carry-lookahead adder.
2. Write a VHDL code to implement the 4-bit carry-save adder.
3. Write the steps involved to prototype the HDL-code onto an FPGA device.
4. Realize a NOR-gate using multiplexer as a logic block.

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 10
VHDL Implementation
Examples
If you need an inforamtion on: See page:
Adder 182
Multiplier 186
Multiplexer 192
Chapter 10

VHDL stands for VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed
Integrated Circuit. VHDL is a very popular Hardware Description Language (HDL) along with Verilog for
simulation, modeling, documentation, and synthesis of high-speed integrated circuits. As it is complicated
to design large systems by manually entering the circuit schematics or writing Boolean expressions, VHDL
can be used to describe systems using a language similar to a programming language. Systems can be
described in VHDL in the two forms: behavioral description and structural description. In the behavioral
description, the system is described based on how it works; whereas, in the structural description, the
system is described based on how it is implemented. In this chapter, you learn how to implement
commonly used digital circuits, such as adder, multiplier, and multiplexer, in VHDL. You also learn the
use of Xilinx ISE for the simulation and synthesize.

Adder
Addition is one of the most important operations, which is used in all computations. Adder is a circuit that
performs addition operation in computers that is widely used in all computations. A 4-bit Carry-
LookAhead (CLA) adder can be implemented using VHDL.
The behavioral description of VHDL code for CLA adder is given as follows:
-- Create Date: 09:31:03 03/21/2010
-- Design Name: adder
-- Module Name: cla1 - Behavioral
-- Project Name: cla
-- Target Devices: xc3s100e-4-tq144
-- Tool version: Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Parameter TMPDIR set to ./xst/projnav.tmp

-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.V Components.all;

----- Entity Declaration

entity cla1 is
port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
sum : out STD_LOGIC_VECTOR (3 downto 0);
carry : out STD_LOGIC;
c : in STD_LOGIC);
end cla1;

-----End of entity declaration

----- begin of architecture definition

architecture Behavioral of cla1 is

component full is

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 VHDL Implementation Examples

----port declaration

port ( a2,a1, a0 : in STD_LOGIC;

s, ca : out STD_LOGIC);
end component;
signal carry1 : std_logic_vector(3 downto 0);

begin

--- begin of description of logic of adder

U1: full port map(a(0),b(0),c,sum(0),carry1(0));

U2: full port map(a(1),b(1),carry1(0),sum(1),carry1(2));
U3: full port map(a(2),b(2),carry1(2),sum(2),carry1(3));
U4: full port map(a(3),b(3),carry1(3),sum(3),carry);

end Behavioral;

--- end of behavioral code

The input variables in the behavioral code are given as follows:
 a: 4-bit input in the binary form
 b: 4-bit input in the binary form
 c: 1-bit carry input; initially, it is reset as low
The output variables in the behavioral code are given as follows:
 sum: 4-bit output in the binary form
 carry: 1-bit carry output
Figure 10.1 shows the synthesis report of CLA adder using the Xilinx ISE tool:

Figure 10.1: Displaying the Synthesis Report of CLA Adder using the Xilinx ISE Tool

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Chapter 10

In Figure 10.1, the device summary information shows the number of slices, number of Look Up Tables
(LUTs), and number of bonded Input/Output Blocks (IOBs) used by the given design. For the CLA circuit,
number of logic elements (also called LUTs) used is two out of 1922. The timing constraints given by the
tool for the design is shown as follows:
Timing constraint: Default path analysis
Total number of paths / destination ports: 6 / 2
-------------------------------------------------------------------------
Delay: 7.047ns (Levels of Logic = 3)
Source: a0 (PAD)
Destination: ca (PAD)

Data Path: a0 to ca
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.218 1.052 a0_IBUF (a0_IBUF)
LUT3:I0->O 1 0.704 0.801 s1 (s_OBUF)
OBUF:I->O 3.272 s_OBUF (s)
----------------------------------------
Total 7.047ns (5.194ns logic, 1.853ns route)
(73.7% logic, 26.3% route)

===============================================================
CPU : 7.07 / 7.28 s | Elapsed : 7.00 / 8.00 s
Figure 10.2 shows the schematic view of the circuit with LUTs and the hardware components in each LUT:

Figure 10.2: Displaying the Schematic View of the 4-Bit CLA Adder

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 VHDL Implementation Examples

As you can see in Figure 10.2, the inputs of the 4-bit CLA design are a0, a1, and a2 and outputs are s and
ca. Figure 10.3 shows two 3-input LUTs of a design with the input and output variables:

Figure 10.3: Displaying the Schematic View of LUTs for the 4-Bit CLA Adder
In Figure 10.3, the CLA circuit is realized using two LUTs termed as LUT3, which means 3-input LUT. The
3-input LUT is used to realize any 3-variable function. The logic that is mapped to each LUT is shown as
gate-level circuit in Figure 10.4 and Figure 10.5. The logic expression for LUT1 is shown in Figure 10.4:

Figure 10.4: Displaying the Gate-Level View of LUT1 for the CLA Design
The logic expression for LUT2 is shown in Figure 10.5:

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Chapter 10

Figure 10.5 Displaying the Gate-Level View of LUT2

Let’s now learn about multipliers.

Multiplier
The 2-bit multiplier performs the multiplication of two 2-bit numbers and stores the product in a 4-bit
register. The input variables of the multiplier are named as x and y and the output of the multiplier is
termed as p. The two binary numbers are multiplied using addition of partial products. The partial
product bits are then added using a half adder. The VHDL code for 2x2 multiplier is given as follows:

MULTIPLIER:-2x2
----------------------------------------------------------------------------
-- Company:
-- Engineer:
-- Create Date: 10:15:18 03/27/2010
-- Design Name: multiplier
-- Module Name: p_bits - Behavioral
--Target Devices : xc4vfx12-10sf363
--Tool Versions: ISE 8.2i
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

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 VHDL Implementation Examples

library ieee;
use ieee.std_logic_1164.all;

--- Entity declaration is defined

entity p_bits is --- p_bits is the entity name

port( x: in std_logic_vector(1 downto 0); ---Input variable declarations
y: in std_logic_vector(1 downto 0); --- Input variable declarations
p: out std_logic_vector(3 downto 0)); --- Output Variable declarations
end p_bits;

---- Architectural definition for entity p_bits

architecture p_bits of p_bits is

component internal_bits is ----component declaration
port( x: in std_logic_vector(1 downto 0); ---Input port declaration
y: in std_logic_vector(1 downto 0); --- Input port declaration
a,b: out std_logic_vector(1 downto 0)); --- Output port declaration
end component;
---- End Component

----Component Half Adder declaration

component ha is
port(a,b:in std_logic; ---Input port a,b declared
su,car:out std_logic); ---Output port declaration
end component;
---- End of Component Declaration
----Component Full Adder declaration

component fa is
port(a1, b1 ,c1 :in std_logic; ---Input port a1,b1 declared
sum1,carry1 :out std_logic); ---Output port declaration
end component;
---- End of Component Declaration

signal a,b: std_logic_vector(1 downto 0);

signal c0:std_logic;

---- Description of the function

begin
u1:internal_bits port map(x,y,a,b);
p(0)<=a(0);
u2: ha port map(a(1),b(0),p(1),c0); --- Instantiation
u3: ha port map(b(1),c0,p(2),p(3)); --- Instantiation

end p_bits;

--- End of the component multiplier is finished

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Chapter 10

Figure 10.6 shows the block diagram of 2x2 multiplier:

Figure 10.6: Displaying the Block Diagram of 2x2 Multiplier

As already learned, the VHDL code is simulated and synthesized using the Xilinx ISE tool. The simulation
results and synthesized report with technology schematic view is given from Figure 10.7 to Figure 10.14.
Figure 10.7 shows the project summary, device utilization summary, and performance summary:

Figure 10.7: Displaying the Synthesis Report

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 VHDL Implementation Examples

The project summary gives information regarding the project file name, selected target device, module
name, and the tool version on which a program is simulated. The logic utilization in the device utilization
summary gives the number of logic blocks used to realize the multiplier circuit; in this case, it is four out
of 9316. Similarly, the logic distribution gives the details related to the distribution of the logic blocks; in
this case, it is 4-input LUTs.
Figure 10.8 shows the block diagram of synthesized circuit:

Figure 10.8: Displaying the Block Diagram of Synthesized Circuit

Figure 10.9 shows the gate-level view of LUT-1:

Figure 10.9: Displaying the Gate-Level View of LUT-1

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Chapter 10

Figure 10.10 shows the gate-level view of LUT-2:

Figure 10.10 Displaying the Gate-Level View of LUT-2

Figure 10.11 shows the gate-level view of LUT-3:

Figure 10.11: Displaying the Gate-Level View of LUT-3

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 VHDL Implementation Examples

Figure 10.12 shows the gate-level view of LUT-4:

Figure 10.12: Displaying the Gate-Level View of LUT-4

Simulation results are shown in Figure 10.13:

Figure 10.13: Displaying the Simulation Results for the Multiplier using ModelSim Simulator

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In Figure 10.13, the initialization waveforms are obtained where the variables x, y, and p_bits are
initialized to the value 0. The p_bits are changed to 1001 when x and y bits are changed to 11 and 11. These
waveforms are obtained using the Mentor Graphics tool. The waveforms are shown in Figure 10.14:

Figure 10.14: Displaying the Waveforms

Multiplexer
The 8 x 1 multiplexer acts as a digital switch. It connects data from one of the eight sources to its output
according to the decimal equivalent of select lines. For example, if the select lines are 010 (the decimal
equivalent of 2), then input(2) is assigned to the output. We will declare a generic variable selectlines
whose value is defined as 3 to select from 8 input lines. The total number of input lines can be, in general,
2 selectlines and the number of output lines is 1. Figure 10.15 shows the 8X1 multiplexer:

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Figure 10.15: Displaying the 8 x 1 Multiplexer

The input ports of the multiplexer are as follows:
input(7 downto 0) : Data input to multiplexer
sel (2 downto 0) : Choose lines to select which input is going to be assigned to
output
The output port of the multiplexer is as follows:
output : It is assigned according to the input line selected by the sel input

VHDL Implementation
The VHDL implementation of the multiplexer is as follows:
-- File name: Mux8.vhdl
--
-- Create Date: 14:19:47 07/05/2007
-- Module Name: Mux8
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 8.2i,ModelSim SE 6.0

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------
-- library declaration

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--entity declaration

entity Mux8 is

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--generic for no. of select lines

generic (selectlines : integer := 3);

-- inputs to mux

port (input : in std_logic_vector((2**selectlines)- 1 downto 0 );

sel : in std_logic_vector((selectlines -1) downto 0);

-- output port

output : out std_logic

);

end Mux8;

-- architecture Declaration

architecture Mux8Arch of Mux8 is

begin

process (input,sel) -- process

begin

output <= input(conv_integer(sel)); -- muxing.

end process;

end Mux8Arch;

Device Utilization Summary

Following is the device utilization summary of the 8x1 multiplexer:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 2 5472 0%

Number of 4 input LUTs 4 10944 0%

Number of bonded IOBs 12 240 5%

Simulation Results
Figure 10.16 shows the simulation results of the 8x1 multiplexer:

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Figure 10.16: Displaying the Simulation Results for 8x1 Multiplexer

16 X 1 Multiplexer
The 16 x 1 multiplexer acts as a digital switch. It connects data from one of the n sources to its output
according to decimal equivalent of select lines. For example, if the input to select lines is 0011 (whose
binary equivalent is 3), then input(3) is assigned to output.
If generic selectlines are assigned a value of 4, then there will be four select lines and the number of input
lines can be 16. You can change this value so that the input of multiplexer can be 2 selectlines.
Figure 10.17 shows the block diagram of 16X1 multiplexer:

Figure 10.17: Displaying the 16 x 1 Multiplexer

The input ports of the 16X1 multiplexer are as follows:
input(15 downto 0) : Data input to multiplexer
sel(3 downto 0) : Choose lines to select which input has to be assigned to
output

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The output port of the 16X1 multiplexer is as follows:

output : It is assigned according to the input line selected by sel

VHDL Implementation
The VHDL implementation of the 16X1 multiplexer is as follows:
-- File name: Mux16.vhdl
-- Create Date: 14:45:09 07/05/2007
-- Module Name: Mux16
-- Project Name: VLSI Lab
-- Target Devices: xc4vfx12-10sf363
-- Tool versions: ISE 8.2i,ModelSim SE 6.0

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------
-- library declaration

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--entity declaration

entity Mux16 is

--generic for no. of select lines

generic (selectlines : integer := 4);

-- inputs to mux

port (input : in std_logic_vector((2**selectlines)- 1 downto 0 );

sel : in std_logic_vector((selectlines -1) downto 0);

-- output port

output : out std_logic

);

end Mux16;

-- architecture Decalaration

architecture Mux16Arch of Mux16 is

begin

process (input,sel) -- process

begin

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output <= input(conv_integer(sel)); -- genrating mux.

end process;

end Mux16Arch;

Device Utilization Summary

Following is the device utilization summary of the 16x1 multiplexer:
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 4 5472 0%

Number of 4 input LUTs 8 10944 0%

Number of bonded IOBs 21 240 8%

Simulation Results
Figure 10.18 shows the simulation results of the 16 x 1 multiplexer:

Figure 10.18: Displaying the 16 x 1 Multiplexer Simulation Results

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Summary
In this chapter, you have studied how to develop applications using VHDL. Xilinx released a simulator
and synthesizer of Vertex-4/5 devices to address the design techniques for complex combinational
circuits. You have also demonstrated the arithmetic circuits, such as CLA adder, multiplier, and
multiplexer, using VHDL. In addition, the simulation and synthesis results are explained for some test
cases. The simulation waveforms from ModelSim tool are also discussed with test cases for designs, such
as multiplier.

Questions
1. Write the VHDL code for carry-save adder and compare the delay with CLA adder.
2. Explain decimal adders.
3. Write the VHDL code for BCD addition.
4. Write a VHDL code to compute the product of two 4-bit binary numbers using Booths multiplication
algorithm.
5. Write the VHDL code for generic nxm multiplier using repeated addition.
6. Write a VHDL code for a 4-bit number divided by a 2-bit combinational logic divider.

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Case Study:
Xilinx Development Board
If you need an information on: See page:
Xilinx ISE 10.1 200
Development Board Architecture 201
Interfacing with Peripherals 202
Chapter 11

In this chapter, you learn how to develop applications using a Xilinx FPGA-based development board. The
details of the architecture of the board and the tools required for development are also given. In addition,
a systematic procedure for the development is given through a case study.

Xilinx ISE 10.1

The Xilinx Integrated Software Environment (ISE) is a state of the art automation tool that consists of set of
programs to create, simulate, and implement digital design in a Field Programmable Gate Array (FPGA)
or Complex Programmable Logic Device (CPLD) target device. This tool takes the design entry in
Hardware Description Language (HDL), verifies it, and then synthesizes the design to FPGA target
devices, such as Virtex and Spatran. This tool consists of ISE design entry (using HDL editor, schematic
entry, and state machine editor), ISE simulation tool, and ISE backend flow.
ISE tool uses a graphical user interface that allows all the programs, such as design entry, HDL editor, and
functional simulation, to be executed from toolbars, menu, or icons. ISE tool controls all the aspects of
design flow, namely design entry, logic simulation, synthesis, timing simulation, place and route, and bit
stream generation, onto the target device through JTAG cable. A brief overview of various steps involved
in the design flow of a digital system is shown in Figure 11.1:

Figure 11.1: Displaying the Steps of Design Flow

Let’s now learn about the design flow in brief.

Design Entry in HDL/Schematic

The first step is to enter your design in an editor based on the specifications. This can be done by using the
source file menu. Source files can be created in three different formats: schematic, HDL (Verilog or
VHDL), and state machine design. After the code is entered, HDL compiler verifies the syntax errors.

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Simulation and Synthesis (Design Verification)

This step verifies the functionality of the design (functional simulation), behavior, and timing (timing
simulation) of the circuit after the place and route step. At the synthesis step, gate-level netlist is generated
for the given digital design.

Design Implementation
After generating the gate-level netlist, which is the technology-independent design at the synthesis step,
the design is converted into technology-dependent design (target to particular devices, such as Virtex or
Spatran FPGA). This step is performed in the following three sub-steps:
1. Translate: In this step, the design is converted into technology-dependent circuit with the available
logic elements. During the translation, the Native Generic Database (NGD) file serves as an input file
and generates the Native Circuit Description (NCD) file.
2. Mapping: The NCD file generated at the translation step is taken as an input to map the program and
allocate the Configurable Logic Blocks (CLBs) and input/output buffer resources to all the basic logic
elements in the design.
3. Placing and Routing the Design: After the design is mapped to logic blocks, the place and route
program runs to place the blocks and performs wiring either based on timing constraint or without
timing constraint depending on the users choice.
4. Timing Simulation: After the evaluation of place and route design, timing simulation step checks the
routing delays and timing constraint using the timing analyzer program.
5. Bit Stream Generation: In this step, configuration bit stream is created for downloading to a target
device for formatting into a programming file.

Development Board Architecture

The architecture of the board used for the development is shown in Figure 11.2:

Figure 11.2: Displaying the FPGA Development Board

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The board is built around Xilinx XC4VSX35 Virtex 4 FPGA and consists of the following components:
 Power supply module that supplies 1.2 volts/2.5 volts/3.3 volts to the board through an adapter
 Provision for clock input
 10/100 Mbps Ethernet interface
 RS 232 interface
 User switches and LEDs
 2 x 16 character LCD
 4 MB flash disk
 64 MB DDR SDRAM
 Joint Test Action Group (JTAG) port
 Configuration through platform Flash, PC4 JTAG Header, and System ACE
 Connectors, such as P240 expansion interface and 800 Mbps LVDS interface
Development board is a very sophisticated board that can be used to develop a variety of applications.
Generally, when you want to develop a system, it is always good to procure such a board and develop the
prototype. After you are satisfied with the prototype, you can consider the option of developing your own
hardware that needs only the necessary interfaces or peripherals. For instance, if you do not need an
Ethernet interface, you can eliminate it in your hardware design.
In addition to the hardware board, you need a number of tools to develop the firmware, perform the
simulation, and then test the firmware, after it is ported onto the hardware. Specifically, you need the
following tools:
 Xilinx ISE
 ModelSim
 ChipScope

Interfacing with Peripherals

In the case study, you will study the following:
 How to interconnect the board to a computer using RS232
 How to transfer data between the computer and the board using RS232
 How to display information on the LCD display
During the case study, you learn how to port the code onto the board and to test each module thoroughly.
In addition, you learn about various mechanisms for configuring the FPGA.
 Objective—To connect the computer to a FPGA device board through serial interface RS232,
designers should have a basic knowledge about digital design, FPGAs, and Xilinx ISE 10.1 tool.
Following are the characteristics of RS232 serial interface:
1. Uses a nine pin connector DB-9 (Figure 11.3)
2. Allows a bidirectional full-duplex communication (the computer can send and receive data at the
same time)
3. Communicates at a maximum speed of roughly 10 KB/s
Figure 11.3 shows the DB-9 male connector:

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Figure 11.3: Displaying the DB-9 Male Connector

Figure 11.4 shows the pin numbering of male connector:

Figure 11.4: Displaying the Pin Numbering of Male Connector

Figure 11.5 shows the pin numbering of female connector:

Figure 11.5: Displaying the Pin Numbering of Female Connector

Pin description of RS232 male connector is given in Table 11.1:
Table 11.1: Pin Description of RS232 Male Connector
Pin No. Name Dir Note/Description

1 DCD IN Data Carrier Detect. It is raised by DCE when modem is synchronized.

2 RD IN Receive Data (RD, Rx). Data is received from DCE.

3 TD OUT Transmit Data (TD, Tx). Data is sent from DTE.

4 DTR OUT Data Terminal Ready. It is raised by DTE when power is on. In the auto-
answer mode, it is raised only when RI arrives from DCE.

5 GND - Ground

6 DSR IN Data Set Ready. It is raised by DCE to indicate ready.

7 RTS OUT Request To Send. It is raised by DTE when it wishes to send. It also
expects CTS from DCE.
8 CTS IN Clear To Send. It is raised by DCE in response to RTS from DTE.

9 RI IN Ring Indicator. It is set when incoming ring detected - used for auto-
answer application. DTE raises DTR to answer.

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The abbreviations used in the preceding table are as follows:

1. RD: Receive Data
2. TD: Transmit Data
3. GND: Ground
4. DTE: Data Terminal Equipment
5. DCE: Data Cable Equipment
6. CTS: Clear To Send
Using the RS232 serial interface, data is transmitted one bit at a time along the wire. As computers usually
need at least several bits of data, the data is serialized before being sent. Data is commonly sent in the
chunks of 8 bits; therefore, the least significant bit (data bit 0) is sent first and the most significant bit (data
bit 7) is sent last. This interface uses an asynchronous protocol, which implies that no clock signal is
transmitted along with the data. The receiver has to have a way to time itself to the incoming data bits. In
the case of RS232, data transmission takes place as mentioned in the steps shown below:
1. Both sides of the cable agree in advance on the communication parameters (given in Figure 11.6). It is
done manually before the communication starts.
2. The transmitter sends bit 1 when the line is idle.
3. The transmitter sends a start bit (0) before each byte is transmitted, so that the receiver can
understand that data is coming.
4. After the start bit, data comes in with the agreed speed and format, so the receiver can interpret it.
5. The transmitter sends a stop bit (1) after each data byte.
For example, a 0x55 byte when transmitted appears in the following way:

Figure 11.6 shows the serial communication parameters:

Figure 11.6: Displaying the Serial Communication Parameters

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The speed is specified in baud, that is, how many bits per second can be sent. For example, 1000 bauds
would mean 1000 bits per second, or that each bit lasts one millisecond.
Common implementations of the RS232 interface do not allow just any speed to be used. Some standard
speed parameters used for RS232 interface are 1200, 9600, 38400, and 115200 bauds.
The signals on wires use a positive or negative voltage scheme as follows:
 1 is sent using -10V (or between -5V and -15V)
 0 is sent using +10V (or between 5V and 15V)
Perform the following steps to connect the RS232 interface to a computer:
1. Connect the FPGA Spartan-3E kit to a laptop or computer using the USB port, as shown in Figure
11.7:

Figure 11.7: Displaying the USB Connection

2. Connect the serial port (DCE terminal) available on the FPGA board to another USB port available on
the laptop or computer using a USB-to-Serial converter, as shown in Figure 11.8:

Figure 11.8: Displaying the USB-to-Serial Converter

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Figure 11.9 shows the RS232 interface:

Figure 11.9: Displaying the RS232 Interface

3. Switch on the board and configure the device using the Xilinx ISE 10.1 tool with the help of Hyper
Terminal path, as shown in Figure 11.10:

Figure 11.10: Displaying the Hyper Terminal Path

The Hyper Terminal window with the Connection Description dialog box appears, as shown in
Figure 11.11:

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Figure 11.11: Displaying the Hyper Terminal Window

4. Type an appropriate name in the Name textbox and click the OK button (Figure 11.11). The Connect
To dialog box appears (Figure 11.12).
5. Select the appropriate COM port from the Connect using drop-down list and click the OK button, as
shown in Figure 11.12:

Figure 11.12: Displaying the Selection of COM Connection

The COMS Properties dialog box appears where you can set the port settings (Figure 11.13).

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6. Set the baud rate to a desired value depending on the design parameters. As the baud rate in the
present design is configured for 9600 baud, the following settings are chosen, as shown in Figure
11.13:

Figure 11.13: Displaying the Hyper Terminal Settings

7. Click the OK button. The terminal becomes ready to run the program.
8. Run the program to display the data onto an LCD device and observe the changes on the LCD.

Summary
In this chapter, the Xilinx ISE version 10.1 and its architecture is been discussed. The design flow in the
Xilinx environment is performed in various steps, such as design entry, design verification, synthesis and
simulation, translate, map, and place and route. Finally, bit stream generation is programmed onto an
FPGA device. The block diagram of architecture with internal and peripheral components is also
discussed. In addition, you have learned the procedure to interface with the peripheral devices with
input/output devices, such as RS232 communication interface and USB, and display the data onto LCDs.

Questions
1. Explain the design verification process in Xilinx ISE.
2. What are the steps involved in the implementation of logic design in the Xilinx ISE tool?
3. Explain the procedure to interface with RS232.
4. Write the function of D9 cable.
5. What is baud rate? Give the permissible baud rates in the Xilinx 10.1 tool.

Exercises
1. Write a 2-bit synchronous counter in VHDL and verify the code using the Xilinx 10.1 tool.
2. Write the program to display the Hello word on the LCD through the keyboard interface.
3. Write a brief note on the components in Virtex Xilinx board.
4. Take any Spartan board and list all the components that are supported to interfacing with USB port.

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Case Study:
Implementation of a
Communication System
If you need an information on: See page:
Xtreme DSP Board Overview 210
Design Details 212
Implementation Details 213
Simulation 225
Testing Environment 247
Chapter 12

Many engineers, new to Very Large Scale Integration (VLSI) technology, show a surprising face when
asked whether they can implement a communication system using Amplitude Modulation (AM) on Field-
Programmable Gate Array (FPGA). After all, these signals are analog and FPGA handles only digital
signals. However, you can develop extremely complicated communication systems using FPGAs. In this
chapter, you learn how to implement a communication system using an FPGA development board
through a case study.

Xtreme DSP Board Overview

In the previous chapter, you have learned how to use an FPGA board to implement general logic or
develop embedded systems. However, this board is not sufficient for this case study, as you have to
develop a signal processing application. In addition to the standard hardware with the FPGA, you need
additional hardware that takes analog signal, converts it into digital format, and sends it to the FPGA.
Similarly, you also need additional hardware that takes the digital signal from the FPGA as input and
converts it into the analog signal. A special FPGA development board is used for this purpose, as shown
in Figure 12.1:

Figure 12.1: Displaying the FPGA Development Board from Nallatech

The Xtreme DSP Kit for Virtex-4

The FPGA development board used in this case study is from Nallatech (www.nallatech.com). It is a very
powerful development platform for creating a variety of applications, such as image processing, wireless
systems, software defined radio, and video imaging.
Xtreme Digital Signal Processor (DSP) development board consists of a motherboard and a daughter card.
The motherboard has a provision for interfacing to a host computer through either Universal Serial Bus
(USB) or Peripheral Component Interconnect (PCI). In addition, it provides Joint Test Action Group
(JTAG) configuration headers and status Light Emitting Diodes (LEDs). The daughter card has Virtex 4
FPGA for user programming (called user FPGA). This FPGA is Xilinx XC4VSX35-10FF668. It also has Zero
Bus Turnaround- Static Random Access Memory (ZBT-SRAM) and status LEDs. This board has the
provision to input two analog signals and output two analog signals as follows:
 Analog to Digital Converter (ADC):
 Sampling rate: 105 MSPS
 Resolution: 14 bits
 Device: Analog Devices AD6645

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 Digital to Analog Converter (DAC):

 Sampling rate: 160 MSPS
 Resolution: 14 bit
 Device: Analog Devices AD9772
Xtreme DSP development board works with software called Field Upgradeable System Environment
(FUSE) that has to be installed in your host system.
To use FPGA for signal processing, you need to choose a development board that caters to your input and
output signal requirements. Particular attention is necessary for the following:
 Sampling rate—The analog signal input occupies a certain bandwidth. For instance, voice signal has
a bandwidth of 4 Kilohertz (KHz); whereas, video signal has a bandwidth of 5 Megahertz (MHz).
Therefore, depending on the bandwidth of the signal, you need to choose the sampling rate, which
should be at least twice the maximum frequency component. For example, voice signal occupies a
bandwidth of 4 KHz; and therefore, minimum 8 KHz sampling rate is required. Similarly, video
signal has a bandwidth of 5 MHz; and therefore, the minimum sampling rate required is 10 MHz. The
ADC chosen should be capable of sampling at the desired rate. Similarly, the DAC should be able to
reproduce the analog signal based on the digital data given to it. If you require to process high
frequency signals, such as Radio Frequency (RF) and Intermediate Frequency (IF), encountered in
radio applications, then you need to be more careful in your selection of ADC and DAC.
Suppose you want to sample a radio signal that is centered at 20 MHz. Assume that the signal
bandwidth is 1 MHz. This implies that the signal has frequency components in the range 19.5 MHz to
20.5 MHz. Therefore, the highest frequency component in the signal is 20.5 MHz. If you apply the
above theorem, the minimum sampling rate required is 41 MHz. However, this is not required, if you
apply another theorem known as IF sampling theorem or bandpass sampling theorem or sub-
sampling theorem. Using this theorem, you can sample at 2 MHz. However, you need to check
whether the ADC is designed for bandpass sampling and from the ADC data sheet, you need to check
its performance for 20 MHz input signal. Generally, the sampling of the bandpass signals is done at
least 5 times the bandwidth for a good performance.
 Resolution of the samples—The ADC and DAC will have a resolution that indicates the granularity
of digitized sample. For example, a sample can be converted into 8-bit data or 16-bit data. Obviously,
16-bit data is a better option because it represents the sample more accurately as compared to 8-bit
data. In other words, the quantization noise will be less for higher resolution. You need to choose the
resolution of ADC and DAC depending on your application requirement as well as the cost of ADC
and DAC.
In the case of voice processing, an 8-bit resolution will be sufficient. The cost of the ADC or DAC will
be higher if you use 16-bit or 24-bit resolution for high quality music. In several communication
applications involving radio frequencies, at least 14-bit of resolution is desirable.
 Analog input/output signal levels—The peak-to-peak voltage levels of analog input to ADC and the
analog output from DAC will be specified. You need to check whether these ranges are sufficient for
your actual input.
 Anti-aliasing filter—Before converting analog signals into digital format, the signal has to be filtered
to ensure that frequency components above half the sampling frequency are not present. As this filter
removes the aliasing effect, it is called an anti-aliasing filter, which is necessary before the ADC.
Generally, this is a Low Pass Filter (LPF). You need to ensure that the FPGA development board that
you are using has the necessary anti-aliasing filters. For example, if your input is a voice signal, the
anti-aliasing filter should be an LPF with a cut-off frequency of 4 KHz, assuming a sampling rate of 8
KHz.

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 Reconstruction filter—Immediately after DAC, a reconstruction filter is required to get high quality
analog signal from the DAC. This is called reconstruction filter.
Therefore, while selecting an FPGA-based development board for communication applications, you need
to select ADC and DAC based on the bandwidth of the signal, sampling rate, resolution, and input/output
signal levels. In addition, the board needs to have the necessary anti-aliasing filter and the reconstruction
filter.

Even if you do not have access to a development board, you can implement the communication system described in
this chapter. Of course, your study is only limited to test the system through simulation.

Design Details
In this case study, you will develop a communication system that takes an input signal, modulates it using
AM in the FPGA, and then demodulates the signal in the FPGA to get back the original signal. You also
learn how to generate sine waves, implement modulation and demodulation algorithms, and filter the
signal. In fact, the work presented can be used straight to develop a communication system based on
FPGA. Figure 12.2 shows an amplitude modulator and demodulator:

Figure 12.2: Displaying the AM Modulator and Demodulator

In the modulator, the message signal (also called the input signal) is multiplied with a carrier to generate
the AM signal. At the demodulator, the envelope of the modulated signal is detected and then passed
through an LPF to get back the message signal.
We are considering the following two types of message signals:
 A single tone of 1 KHz frequency
 Voice signal, which can be obtained from the output of the Personal Computer (PC) sound card
The carrier is generally a high frequency signal. In this case study, we will take a carrier frequency of 455
KHz, as this frequency is a standard IF used in several high frequency communication systems.
We will generate 1 KHz frequency (a single tone) and 455 KHz carrier in the FPGA. Then, we will
implement the modulator as well as the demodulator in the FPGA. If we use an FPGA development board
that has an ADC and DAC, then we can also observe the modulated/demodulated signals in the
oscilloscope.
On the FPGA development board, we will implement the following:
 Generation of 1 KHz signal
 Generation of 455 KHz signal
 AM of 455 KHz carrier with 1 KHz signal
 AM of 455 KHz carrier with voice signal
 Amplitude demodulation of the above two signals

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Implementation Details
In this section, the step-by-step procedure for implementing the communication system is given. To start
with, you will learn how to perform the simulation and testing. Then, you will port the code on the FPGA
and then test on the actual hardware. Even if you do not have access to a development board, you can
work on the first portion of this project.

Creating a New Project using the Xilinx Project Navigator

To open the Xilinx Project Navigator, double-click the Xilinx ISE 8.2i shortcut from the Desktop or select
Start → Programs → Xilinx ISE 8.2i → Project Navigator. The main screen of the Xilinx ISE Project
Navigator appears, as shown in Figure 12.3:

Figure 12.3: Displaying the Xilinx ISE Main Screen

Perform the following steps to create a new project:

1. Select File → New Project. The New Project Wizard – Create New Project window appears, as shown
in Figure 12.4:

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Figure 12.4: Displaying the New Project Wizard – Create New Project Window
2. Type the name of the project in the Project Name field.
3. Enter a location in the Project Location field or browse to a location (directory path) by clicking the
button located beside the field, for the new project.
4. Select an option from the Top-Level Source Type list, which has the following options:
i. HDL → Choose this option for VHDL / Verilog programming
ii. Schematics → Choose this option to work on Schematics
In our case, we have selected HDL.
5. Click the Next button. The New Project Wizard - Device Properties window appears, as shown in
Figure 12.5:

Figure 12.5: Displaying the New Project Wizard – Device Properties Window
6. Fill the values in the table given as follows:
 Product Category: All
 Family: Vertex4
 Device: XC4VSX35

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 Package: FF668
 Speed Grade: -10
 Top-Level Module Type: HDL
 Synthesis Tool: XST (VHDL/Verilog)
 Simulator: Modelsim-SE VHDL
7. Select the Enable Enhanced Design Summary checkbox, if not selected.
8. Click the Next button to continue. The New Project Wizard – Project Summary window appears, as
shown in Figure 12.6:

Figure 12.6: Displaying the New Project Wizard – Project Summary Window
9. Click the Finish button to complete the creation of new project. The New Project Main Screen
appears, as shown in Figure 12.7:

Figure 12.7: Displaying the Project Window after Creating the New Project

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Perform the following steps to create VHDL/Verilog source:

1. Select the Sources tab from the New Project Main Screen (Figure 12.7).
2. Right-click the device as per your requirement. In our case, we have clicked XC4VSX35-10ff668. A
pop-up menu appears.
3. Select the New Source option from the pop-up menu. The New Source Wizard – Select Source Type
window appears (Figure 12.8).
4. Select the type of source from the list box. In our case, we have selected VHDL Module.
5. Type the name of the source code in the File name field. In our case, we have typed tone, as shown in
Figure 12.8:

Figure 12.8: Displaying the New Source Wizard – Select Source Type Window
6. Click the Next button to continue. The New Source Wizard – Define Module window appears (Figure
12.9). Declare the ports for Entity (which contains all the inputs and outputs) by filling in the port
information. We will output the tone as a 14-bit value; and therefore, we have selected the Bus check
box and entered 13 and 0 in the MSB and LSB columns respectively for the tone_wave port name, as
shown in Fig 12.9:

Figure 12.9: Displaying the New Source Wizard - Define Module Window
7. Click the Next button. The New Source Wizard – Summary window appears, as shown in Figure
12.10:

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Figure 12.10: Displaying the New Source Wizard – Summary Window

8. Click the Finish button. The VHDL program structure is displayed in the main GUI of Xilinx ISE, as
shown in Figure 12.11:

Figure 12.11: Displaying the VHDL Program Structure

Generation of 1 KHz Sine Wave (Tone) Component

To generate a sine wave, you can use the Direct Digital Synthesizer (DDS) core, which is readily available
in Integrated Simulation Environment (ISE). The DDS is used to generate any sine wave of the desired
frequency.
Local Oscillator is an important block in all the communication systems and generates a signal of the
required frequency. DDS is the digital equivalent of a Local Oscillator. It is also called Numerically
Controlled Oscillator (NCO). DDS is used to generate sine or cosine waves of desired frequency with high
accuracy. In many communication systems, you may also need to generate multiple sine waves with
different phases. The DDS is capable of generating sine waves with precise phase differences. You can use

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the DDS core on a variety of Xilinx processors, such as Virtex-4 FX, LX and SX families, Vertex-2 Pro,
Vertex-2, Vertex-E, Spartan-3E, Spartan-3, Spartan-2E, and Spartan 2.
In our example, we have chosen the sampling rate as 10 MHz. The number of output bits is 14. The
Spurious Free Dynamic Range (SFDR) would be equal to 6 times the number of bits or 84 dB.
Perform the following steps to generate a sine wave component:
1. Select VHDL Module, “tone – Behavioral (tone.vhd)” from the Sources tab of the Sources window and
right-click it to open a pop-up menu.
2. Select New Source from the pop-up menu. The New Source Wizard – Select Source Type window
appears, as shown in Figure 12.12:

Figure 12.12: Displaying the New Source Wizard – Select Source Type Window
3. Select IP (Coregen & Architecture Wizard) from the list box and enter the name of the component in
the File name field.
4. Click the Next button. The New Source Wizard – Select IP window appears, as shown in Figure 12.13:

Figure 12.13: Displaying the New Source Wizard – Select IP Window

5. Select Digital Signal Processing → Modulation Direct Digital Synthesizer v5.0 in the window.
6. Click the Next button. The New Source Wizard – Summary window appears, as shown in Figure
12.14:

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 Case Study: Implementation of a Communication System

Figure 12.14: Displaying the New Source Wizard – Summary Window

7. Click the Finish button. The Direct Digital Synthesizer dialog box appears, as shown in Figure 12.15:

Figure12.15: Displaying the Direct Digital Synthesizer Dialog Box

In our example, we have chosen the sampling rate for the tone as 10 MHz and number of output bits as 14.
Therefore, the SFDR would be 84 and frequency resolution would be 0.4.
8. Click the NEXT button. The Direct Digital Synthesizer dialog box changes showing the Output
Frequencies group, as shown in Figure 12.16:

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Fig 12.16: Displaying the Output Frequencies Group

9. Specify the required tone frequency in the Output Frequencies group. In our case, we have specified 1
KHz.
10. Press the Enter key on the keyboard.
11. Select the Fixed radio button as we are considering the single tone frequency.

In the case of multiple frequencies, you need to select the Programmable radio button.

12. Click the NEXT button to continue. The Direct Digital Synthesizer dialog box shows the Phase Offset
Angles group, as shown in Figure 12.17:

Figure12.17: Displaying the Phase Offset Angles Group

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 Case Study: Implementation of a Communication System

If there is any requirement of changing the phase of the wave, then you can make the necessary changes in
the group. As there is no need for any phase offset in our example, you can move on to the next window
by clicking the Next button. The various pin selection groups appear, as shown in Figure 12.18:

Figure 12.18: Displaying the Pin Selection Groups

From the dialog box, you need to choose the desired options as follows:
Clear Options  Select ACLR Pin (Asynchronous Clear)
Clear SCLR Pin (Synchronous Clear)
Clock Enable  Clear Clock Enable
Noise Shaping  Select Auto
Memory Type  Select Auto
Handshaking Options  Clear RDY Pin (Ready)
Clear RFD Pin (Ready for Data)
Pipelined  Select Pipelined
Accumulator Latency  Select One Cycle
Layout  Clear Layout
13. Click the NEXT button. The Direct Digital Synthesizer dialog box shows the Summary group, which
contains all the details that we have selected for the tone generation, as shown in Figure 12.19:

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Figure12.19: Displaying the Summary Group

14. Click the Generate button to generate the component.
While generating the DDS component, status of generation is displayed in the Transcript window of
the main window. You will see the message, Successfully generated sine_wave, in the Transcript
window, once the sine wave generation is completed.
15. Click the yellow color bulb icon at the upper right corner of the window to open the Language
Templates.
16. Select the COREGEN folder from Language Templates. The two folders, VHDL Component
Instantiation and Verilog Component Instantiation, appear under the COREGEN folder.
17. Select the sine_wave component from the VHDL Component Instantiation folder, as shown in
Figure 12.20:

Figure 12.20: Displaying the Xilinx Language Templates

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 Case Study: Implementation of a Communication System

From this window, you can take the component and its instance; and instantiate it in the VHDL source
code (copying the component and its instance from the Language Templates and pasting them in the
VHDL module, tone.vhd). You can then change the instantiation variables, as per your requirement. After
the instantiation, the VHDL source code appears, as shown in Figure 12.21:

Figure 12.21: Displaying the VHDL Source Code

18. Edit the line number 43 in the tone.vhd module according to the DDS Clock Rate set in the DDS
Performance operations (Figure 12.15).

You need to ensure that the DDS clock rate and instantiated clock in the source code are the same.

19. Write a process block for clock division, as shown in Listing 12.1:
Listing 12.1: ToneGeneration.vhd
---------------Tone Generation------------

--Library Declaration

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--Entity Declaration

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entity tone is

--input port

port ( clk : in STD_LOGIC;

rst : in STD_LOGIC;

--outport

tone_out : out STD_LOGIC_VECTOR (13 downto 0)

);

end tone;

--Architecture Declaration

architecture Behavioral of tone is

--signals Declaration

signal msg_out :std_logic_vector(13 downto 0);

signal clk_10M :std_logic;
signal cnt :integer;

------------Component Declarations-----------

component sine

port (

--input

CLK : IN std_logic;
ACLR: IN std_logic;

--output

SINE: OUT std_logic_VECTOR(13 downto 0)

);
end component;

begin

----------Component Instantiations------------
u1: sine

port map (
CLK => clk_10M,
ACLR => rst,
SINE => msg_out

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 Case Study: Implementation of a Communication System

);

--------------Clock Division Block------------

----Dividing 100MHz clock to 10MHz -----------

process(clk,rst)

begin
if(rst='1') then

clk_10M <= '0';

cnt <= 0;

elsif(clk'event and clk='1') then

if(cnt=4) then

clk_10M<= not clk_10M;

cnt <=0;

else

cnt <= cnt +1;

end if;

end if;

end process;

tone_out <= msg_out; ---Output Assignment

end Behavioral;

-------End of Tone Generation--------------

Now, our source code is ready for simulation.

Simulation
Before simulating the source code, you need to add Xilinx libraries in case you are using IP core
components from the COREGEN folder; otherwise, errors will occur while simulating with ModelSim.
The following libraries need to be added to the ModelSim:
 Unisim
 Simprim
 Coregenlib
To add these libraries, you need to change the properties of Simulation Library Compiler Properties,
which can be found using the following steps:
1. Select the device name XC4VSX35-10ff668 in the Sources tab of the Sources window.
2. Expand Design Utilities in the Processes pane.
3. Right-click Compile HDL simulation libraries from the Design Utilities. A pop-up menu appears.

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4. Select Properties from the pop-up menu. The Simulation Library Compiler Properties window
appears, as shown in Figure 12.22:

Figure 12.22: Displaying the Simulation Compiler Library Properties

5. In this window, you need to fill the properties as follows:
 Language: All
 Compiled Library Directory: C/Xilinx/xilinx (give the Xilinx path)
 Simulator Path: C/Modeltech_6.0/win32 (give the ModelSim path so that you can call ModelSim
directly from the Xilinx main window)
 Overwrite Compiled Libraries: Overwrite
Select all the check boxes except the Update modelsim.ini File for Xilinx Smart Model Use check box.
1. Click the Apply button.
2. Click the OK button.
6. Right-click Compile Simulation Libraries from the Xilinx main window and run it.
After completing the run process, all the required libraries will be added.

Simulation in ModelSim
Perform the following steps to design and simulate the source code tone.vhd in ModelSim, which can be
opened from the Xilinx ISE8.2i window:
1. Click the source code name (tone.vhd) in the Sources window to find the ModelSim simulator in the
Process window.
2. Double-click Simulate Behavioral Model. The ModelSim simulator opens to simulate the source
code, as shown in Figure 12.23:

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 Case Study: Implementation of a Communication System

Figure 12.23: Displaying the ModelSim Main Window

The ModelSim icon or main window appears on the Desktop after the successful installation of
ModelSim simulator (Fig 12.23). By clicking the ModelSim icon, the ModelSim Work window
appears, as shown in Fig 12.24:

Figure 12.24: Displaying the ModelSim Work Window

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After the successful loading, compilation, and simulation of design, the Waveform window appears, as
shown in Fig 12.25:

Figure 12.25: Displaying the Waveform Window

You need to force the clock and reset input values from the Waveform window.
3. Right-click clk (clock) in the window. A pop-up menu appears.
4. Select Clock from the pop-up menu. The Define Clock dialog box appears, as shown in Figure 12.26:

Figure 12.26: Displaying the Define Clock Dialog Box

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 Case Study: Implementation of a Communication System

5. Specify clock period in the Period field and leave the remaining options unchanged.
6. Click the OK button.
7. Right-click rst (reset) in the window. A pop-up menu appears.
8. Select Force from the pop-up menu. The Force Selected Signal dialog box appears, as shown in
Figure 12.27:

Figure 12.27: Displaying the Force Selected Signal Dialog Box

9. Click the Run button, as shown in Figure 12.28:

Figure 12.28: Displaying the Run Button

10. Repeat the step 6 to force the reset value as initialized in the source code. In our case, we have first
initialized reset to 1, and then 0. Keep running the code until divided clock (clk_10M) appears because
our source code runs with the divided clock.
The Waveform window reappears, as shown in Figure 12.29:

Figure 12.29: Displaying the Waveform Window after Running the Code
We need to change the format of the output signal, as we require the output in the analog form.
11. Right-click the output wave. A pop-up menu is displayed.
12. Select Format from the pop-up menu. A sub pop-up menu appears.
13. Select Analog from the sub pop-up menu. The Wave Analog dialog box appears, as shown in Figure
12.30:

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Chapter 12

Figure 12.30: Displaying the Wave Analog Dialog Box

14. Enter the pixels value (Figure 12.30).
15. Click the Apply button.
16. Click the OK button.
The 1 KHz analog tone signal appears, as shown in Figure 12.31:

Figure 12.31: Displaying the 1 KHz Tone Output Simulation Results

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 Case Study: Implementation of a Communication System

AM Modulator Implementation
Modulation is a process in which the characteristics of the carrier signal wave are varied according to the
characteristics of the message. Any of the following characteristics of the carrier can be varied:
 Amplitude
 Frequency
 Phase
If the amplitude is varied, it is called AM. If the frequency is varied, it is called Frequency Modulation. If
the phase is varied, it is called Phase Modulation. In good (or bad?) old days, the modulators and
demodulators used to be implemented in discrete circuitry. Subsequently, DSPs became the norm;
however, nowadays, FPGAs are used. The FPGA optimized for signal processing applications is the best
for these types of applications.
AM is defined as a process in which amplitude of carrier wave c(t) is varied about a mean value linearly
with the baseband signal m(t). Mathematically, AM wave is represented as follows:
AM modulated wave = Ac[1 + ka m(t)] cos(2fc )
= [1 + ka m(t)] c(t)
In this equation, ka is called the Modulation Index. For simplicity, we will take ka value as 1.
Perform the following steps to generate AM signals:
Step 1: Generate a 1 KHz tone signal m(t) from Xilinx ISE IP Coregen as explained in the Generation of 1
KHz Sine Wave (Tone) Component section. The tone is generated, as shown in Figure 12.32:

Figure 12.32: Displaying the Tone Signal

Step 2: Generate 455 KHz carrier signal following the same procedure as for 1 KHz tone. Note that the
sampling rate must be greater than or equal to twice the carrier frequency. In our case, we take the
sampling rate (DDS clock rate) as 10 MHz. The carrier signal is shown in Figure 12.33:

Figure 12.33: Displaying the Carrier Signal

Step 3:
i. Add a constant to the message through adder [1 + m(t)].
ii. Add a constant in terms of power of 2, that is, 214– 1 = 16383 (in decimal) = 3FFF (Hex), as we are
doing the processing in digital domain.
iii. Select an adder from the Xilinx IP core for Math functions. A pop-up menu appears. Click the Adder
Subtracter v7.0 option from the pop-up menu. The Adder Subtracter dialog box appears, as shown in
Figure 12.34:

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Figure 12.34: Displaying the Adder Subtracter Dialog Box

iv. Select the desired options from the dialog box as follows:
 Operation: Add
 Port A Input Outputs: 14 bits, Signed
 Port B Inputs Outputs: 16 bits, Signed, Constant Value 3FFF (Hexadecimal value of 214 - 1, as the
number of input bits is 14)
v. Click the Next button to go to the next page of the dialog box, as shown in Figure 12.35:

Figure 12.35: Displaying the Adder Subtracter Dialog Box

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vi. Select the desired options from the dialog box as follows:
Output Options : Registered
Latency : 1
Carry/Overflow Options: Clear Carry/Borrow Input
Layout : Create RPM
vii. Click the Generate button to generate the adder component.
Step 4:
i. Multiply the result in step 3 with the carrier wave. To do this, select the Multiplier component from
the New Source Wizard – Select IP window, as shown in Figure 12.36:

Figure 12.36: Displaying the New Source Wizard- Select IP Window

ii. Click the Next button to continue. The New Source Wizard –Summary window appears, as shown in
Figure 12.37:

Figure 12.37: Displaying the New Source Wizard –Summary Window

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iii. Click the Finish button. The Multiplier v8.0 dialog box appears, as shown in Figure 12.38:

Figure 12.38: Displaying the Multiplier v8.0 Dialog Box

iv. Select the desired options from the dialog box as follows:
 Port A: Data Type  Signed
Width  14 (carrier signal width)
 Port B: Data Type  Signed
Width  16 (Adder output width)
Multiplier Construction  Use XtremeDSP Slice
v. Click the Next button to go to the next page of the dialog box, as shown in Figure 12.39:

Figure 12.39: Displaying the Multiplier v8.0 Dialog Box

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 Case Study: Implementation of a Communication System

vi. Click the Finish button to generate the Multiplier component.

Step 5: Take all the components (tone, carrier, adder, and multiplier) from the Language Templates in the
Xilinx ISE main window. Go to VHDL Component Instantiation and take the components and their
instances.
Step 6: Put these components and instances in the VHDL source code, that is, copy the component and its
instance from the Language Templates and paste them in VHDL module (am_modulation.vhd).
After instantiating all the components in the source code, the code appears, as shown in Listing 12.2:
Listing 12.2: AM Modulation
----------------------------------------------------------------------
-- File name: am_modulation.vhd
--
-- Create Date: 15:24:53 09/12/2010
-- Design Name:
-- Module Name: am_mod - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity am_mod is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
am_out : out STD_LOGIC_VECTOR (13 downto 0));
end am_mod;

architecture Behavioral of am_mod is

--------------------------------------------------------------------
----------------- INTERNAL SIGNAL DECLARATIONS ---------------------
--------------------------------------------------------------------

signal msg_out ,carr_out :std_logic_vector(13 downto 0);

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signal adder_out :std_logic_vector(15 downto 0);

signal mul_out :std_logic_vector(29 downto 0);
--signal am_out1 :std_logic_vector(13 downto 0);

signal clk_10M :std_logic;

signal cnt :integer;

--------------------------------------------------------------------

--------------- COMPONENT DECLARATIONS -----------------------------

component msg
port (
CLK: IN std_logic;
ACLR: IN std_logic;
SINE: OUT std_logic_VECTOR(13 downto 0));
end component;

component carr
port (
CLK: IN std_logic;
ACLR: IN std_logic;
SINE: OUT std_logic_VECTOR(13 downto 0));
end component;
component adder
port (
A: IN std_logic_VECTOR(13 downto 0);
Q: OUT std_logic_VECTOR(15 downto 0);
CLK: IN std_logic);
end component;
component mul
port (
clk: IN std_logic;
a: IN std_logic_VECTOR(13 downto 0);
b: IN std_logic_VECTOR(15 downto 0);
q: OUT std_logic_VECTOR(29 downto 0));
end component;
---------------------------------------------------------------------

begin

-------------------COMPONENT PORT MAPPINGS --------------------------

u1 : msg
port map (
CLK => CLK_10M,
ACLR => rst,
SINE => msg_out);

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u2 : carr
port map (
CLK => CLK_10M,
ACLR => rst,
SINE => carr_out);

u3 : adder
port map (
A => msg_out,
Q => adder_out,
CLK => CLK);

u4 : mul
port map (
clk => clk,
a => carr_out,
b => adder_out,
q => mul_out);

----------------------------------------------------------------------

--------------- CLOCK DIVSION BLOCK ----------------------------------

process(clk,rst)
begin
if(rst='1') then
clk_10M <= '0';
cnt <= 0;
elsif(clk'event and clk='1') then
if(cnt=4) then
clk_10M <= not clk_10M;
cnt<= 0;
else
cnt <= cnt +1;
end if;
end if;
end process;

----------------------------------------------------------------------
am_out <= mul_out(29 downto 16);

end Behavioral;

----------------------END OF THE SOURCE CODE -------------------------

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Simulation Results of AM Modulation

After completion of the source code, simulate the code as per the procedure given in Tone Generation
Simulation. The simulation results are shown in Figure 12.40:

Figure 12.40: Displaying the AM Modulation Simulation Results

In Figure 12.40, you can observe the message signal, carrier signal, the added output, and the amplitude
modulated wave. The envelope of the amplitude modulated wave is exactly similar to the modulating
signal, which is of 1 KHz tone.

AM Demodulation
In the demodulation process, the carrier is removed from the modulated signal to get back the original
message. Demodulation involves two steps: envelope detection and low pass filtering, as shown in Figure
12.41:

Figure 12.41: Displaying the AM Demodulation

Envelope Detector
An envelope detector is realized in hardware using a diode, capacitor, and resistor (Figure 12.42). The
envelope detector takes the high frequency signal (in our case, the amplitude modulated signal) as input
and gives an output, which is the envelope of the original signal. The capacitor in the circuit stores the
charge on the rising edge and releases it slowly through the resistor, when the signal falls. The diode
ensures that the current does not flow backward to the input of the circuit. Fig 12.42 shows the envelope
detector:

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 Case Study: Implementation of a Communication System

Figure 12.42: Displaying the Envelope Detector

LPF removes the high frequency components that may be generated along with the envelope-detected
wave.
The procedure for AM Demodulation is as follows:
Step 1: Generate the AM modulated wave as explained in AM Modulation and instantiate the
am_modulation.vhd code in the VHDL source code.
Step 2: Develop the logic for envelope detector in VHDL. We need to detect the peaks in modulated signal
in terms of digital samples. Therefore, we have to compare every two samples in the modulated signal.
This implies that for every clock pulse, we have to compare the present sample and the previous sample,
and store the larger sample into a register. This eliminates all the negative samples. By keep on comparing
the samples, we will get back the message signal.
Step 3: Pass the output of the envelope detector through an LPF to remove all the unwanted signals (high
frequency components) that may occur while detecting the modulating signal.
Step 4: Generate the LPF from Xilinx IP Coregen as follows:
i. Select the FIR Compiler v1.0 IP core from the Xilinx ISE New Source Wizard-Select IP window, as
shown in Figure 12.43:

Figure 12.43: Displaying the New Source Wizard – Select IP Window

ii. Click the Next button and then the Finish button to get the FIR Compiler v1.0 dialog box, as shown in
Figure 12.44:

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Figure 12.44: Displaying the FIR Compiler v1.0 Dialog Box

iii. Select the desired options in the dialog box as follows:
Filter Specification:
Filter Architecture  Distributed Arithmetic
Number of Channels  1
Filter Type  Single Rate
Frequency Configuration:
Clock Frequency  10
Sampling Frequency 10
iv. Click the Next button to go to the next page of the dialog box, as shown in Figure 12.45:

Figure 12.45: Displaying the FIR Compiler v1.0 Dialog Box

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 Case Study: Implementation of a Communication System

v. Select the desired options from the dialog box as follows:

Input Data:
Input Data Type  Signed
Input Data Width  14
Coefficient Options:
Number of Coefficients (per set)  201 (depends on the filter you have designed in MATLAB)
Coefficient Width  16
Coefficient Structure  Symmetric
Load COE File: Load the filter coefficients in the .coe format, which has been designed from
MATLAB

When you design filters, initially you need to generate the filter coefficients using MATLAB. These filter coefficients have
to be loaded in the .coe format.

vi. Click the Next button to go to the next page of the dialog box, as shown in Figure 12.46:

Figure 12.46: Displaying the LPF Response

In Figure 12.46, you can observe the LPF response.
vii. Click the Next button to continue. The next page of the dialog box appears, as shown in Figure 12.47:

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Figure 12.47: Displaying the FIR Compiler v1.0 Dialog Box

viii. Click the Next button to go to the summary page of the dialog box, as shown in Figure 12.48:

Figure 12.48: Displaying the Summary Page

ix. Click the Finish button to generate the Filter component.
Step 5: Instantiate all the components (AM Demodulation and Filter) in the VHDL source code, as shown
in Listing 12.3:

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 Case Study: Implementation of a Communication System

Listing 12.3: AM Demodulation

------------------------------------------------------------------
File name: am_demod.vhd
--
-- Create Date: 17:08:22 09/12/2010
-- Design Name:
-- Module Name: am_demod - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity am_demod is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
dmod_out : out STD_LOGIC_VECTOR (13 downto 0));
end am_demod;

architecture Behavioral of am_demod is

------------------------------------------------------------------
-----------------INTERNAL SIGNAL DECLARATIONS---------------------
------------------------------------------------------------------
signal am_out1 :std_logic_vector(13 downto 0);
signal rfd,rdy :std_logic;
signal clk_10M :std_logic;
signal cnt :integer;
signal envelope :std_logic_vector(13 downto 0);
signal lpf_out :std_logic_vector(36 downto 0);
signal lpf_out1 :std_logic_vector(13 downto 0);

----------------STATE MACHINE SIGNALS----------------------------

type state_t is (s0,s1,s2);
signal state_v : state_t;
signal prev_val,present_val :integer;
signal out1 : integer;

------------------------------------------------------------------

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------------------------------------------------------------------
-------------- COMPONENT DECLARATIONS ---------------------------
------------------------------------------------------------------

component am_mod
port(
clk :in std_logic;
rst : in std_logic;
am_out :out std_logic_vector(13 downto 0));
end component;

component lpf_norm
port (
sclr: IN std_logic;
clk: IN std_logic;
nd: IN std_logic;
din: IN std_logic_VECTOR(13 downto 0);
rfd: OUT std_logic;
rdy: OUT std_logic;
dout: OUT std_logic_VECTOR(36 downto 0));
end component;

------------------------------------------------------------------

begin

---------------- COMPONENT PORT MAPPINGS -------------------------

u5: am_mod
port map(
clk => clk,
rst => rst,
am_out => am_out1);

u6 : lpf_norm
port map (
sclr => rst,
clk => clk_10M,
nd => '1',
din => envelope,
rfd => rfd,
rdy => rdy,
dout => lpf_out);

------------------------------------------------------------------
------------------------------------------------------------------
------------- Clock Division Block -------------------------------
------------------------------------------------------------------
process(clk,rst)
begin
if(rst='1') then
cnt <= 0;
clk_10M <= '0';

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 Case Study: Implementation of a Communication System

elsif(clk'event and clk='1') then

if(cnt=4) then
clk_10M <= not clk_10M;
cnt <=0;
else
cnt <= cnt +1;
end if;
end if;
end process;

------------------------------------------------------------------

------------------------------------------------------------------
-----------------State Machine Block -----------------------------
------------------------------------------------------------------
process(clk_10M,rst)
begin
if rst = '1' then
present_val <= 0;
else
present_val <= conv_integer(am_out1);
end if;
end process;

process(clk_10M,rst)
begin
if rst = '1' then
prev_val <= 0;
elsif (clk_10M'event and clk_10M = '1') then
prev_val <= present_val;
end if;
end process;

process(clk_10M,rst)
begin
if rst = '1' then
state_v <= s0;
out1 <= 0;

elsif (clk_10M'event and clk_10M = '1') then

case state_v is
when s0 =>
if prev_val < present_val then
state_v <= s1;
elsif prev_val > present_val then
state_v <= s2;
else
state_v <= s0;
end if;

out1 <= 0;

when s1 =>
if (prev_val <= present_val) then

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Chapter 12

state_v <= s1;

elsif prev_val > present_val then
state_v <= s2;
out1 <= prev_val;
end if;

when s2 =>
if prev_val < present_val then
state_v <= s1;
-- out2 <= prev_val;
elsif prev_val >= present_val then
state_v <= s2;
end if;
end case;
end if;
end process;

envelope <= conv_std_logic_vector(out1,14);

------------------------------------------------------------------

lpf_out1 <= lpf_out(33 downto 20);

dmod_out <= lpf_out1;

end Behavioral;

---------------------------End of the Source code-----------------

AM Demodulation Simulation Results

Simulation results of the AM Demodulation are shown in Figure 12.49:

Figure 12.49: Displaying the Demodulation Simulation Results

In Figure 12.49, you can observe the modulated signal, the output of the envelope detector, and the output
of the LPF, which is the message signal.

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 Case Study: Implementation of a Communication System

Device Utilization
You can find out the resource utilization of FPGA for the AM Modulation and Demodulation for a given
FPGA. Table 12.1 and Table 12.2 gives the device utilization summaries for the modulator and
demodulator when the design is synthesized using the target devices as XC4VSX35-12FF668:
Table 12.1: Device Utilization Summary for AM Modulator
Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 313 15360 2%

Number of Slice Flip Flops 447 30720 1%

Number of 4 input LUTs 388 30720 1%

Number of bonded IOBs 16 448 3%

Number of FIFO16/RAMB16s 2 192 1%

Number of GCLKs 3 32 9%

Number of DSP48s 1 192 0%

Table 12.2: Device Utilization Summary for AM Demodulator

Device Utilization Summary (Estimated Values)
Logic Utilization Used Available Utilization

Number of Slices 6019 15360 39%

Number of Slice Flip Flops 11169 30720 36%

Number of 4 input LUTs 9159 30720 29%

Number of bonded IOBs 16 448 3%

Number of FIFO16/RAMB16s 2 192 1%

Number of GCLKs 4 32 12%

Number of DSP48s 1 192 0%

Testing Environment
Based on user requirements, area constraints and pin assignments can be given during the physical design
implementation process to configure the digital design onto FPGA board. This section provides the
physical design implementation process for the given verified design. The procedure to assign input and
output pins to the DAC /ADC design and size of the chip is been described in this section in detail.

Testing the Code on FPGA Development Board

After checking the simulation results in ModelSim, you need to program the FPGA and test the AM
Modulator and Demodulator on the actual hardware. As discussed, we use the Xtreme DSP kit for Virtex-
4 from Nallatech. In the preceding section, we have studied how to generate the message signal (tone) in
the FPGA itself. Instead, you can give a single tone as input from one of the ADC inputs. This message

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signal is then modulated using the carrier generated in the FPGA. The modulated signal can be obtained
from one of the DAC outputs. After ensuring that you are getting the correct output (by observing the
waveform or spectrum), you can give this output as input to the second ADC. You can then demodulate
the signal in the FPGA and get back the message signal from the second DAC output. After testing the
communication system using a tone, you can give voice signal as input and check whether you are able to
get back the voice signal without any distortion using the setup, as shown in Figure 12.50:

Figure 12.50: Displaying the Test Setup for Testing the Communication System

Changes in the Code for Dumping into the Board

After checking the simulation results, required modifications in the code for dumping into the kit are as
follows:
 The DAC control signals should always be set. In particular, it is important not to leave the
DAC1_RESET and DAC2_RESET control lines low by default.
 The following are the code examples for setting fixed DAC control signals:

 DACs accept the ADCs inputs in the form of binary offset.

 It is a straightforward process to convert from two’s complement to offset binary format, which
involves taking a two’s complement input and inverting the top most bit.
This format is as follows:

These are the required changes in the main source code.

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When programming the FPGA, you need to check the data sheets to find out the format of the output of the ADC and
the input to the DAC.

The complete code for AM Modulation and Demodulation in real-time using the FPGA board are given in
Listing 12.3 and Listing 12.4, respectively:
Listing 12.3: AM Modulation in Real-Time
File name: am_mod.vhd
-- Create Date: 15:24:53 09/12/2010
-- Design Name:
-- Module Name: am_mod - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity am_mod is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
message :in std_logic_vector(13 downto 0);
----------- DAC SETUPS -----------------------
-- dac reset signals
DAC1_RESET : out std_logic;
DAC2_RESET : out std_logic;
-- dac setup
DAC1_MOD0 : out std_logic;
DAC1_MOD1 : out std_logic;
DAC2_MOD0 : out std_logic;
DAC2_MOD1 : out std_logic;
-- dac clock divider setup
DAC1_DIV0 : out std_logic;
DAC1_DIV1 : out std_logic;
DAC2_DIV0 : out std_logic;
DAC2_DIV1 : out std_logic;

------------------------------------------------

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am_out : out STD_LOGIC_VECTOR (13 downto 0));

end am_mod;

architecture Behavioral of am_mod is

------------------------------------------------------------------------
-----------------INTERNAL SIGNAL DECLARATIONS --------------------------
------------------------------------------------------------------------

signal msg_out ,carr_out :std_logic_vector(13 downto 0);

signal adder_out :std_logic_vector(15 downto 0);
signal mul_out :std_logic_vector(29 downto 0);
signal am_out1 :std_logic_vector(13 downto 0);

signal clk_10M :std_logic;

signal cnt :integer;

-----------------------------------------------------------------------

----------------- COMPONENT DECLARATIONS ------------------------------

---------------DISABLE THIS MSG COMPONENT WHILE USING IN REALTIME------

--component msg
-- port (
-- CLK: IN std_logic;
-- ACLR: IN std_logic;
-- SINE: OUT std_logic_VECTOR(13 downto 0));
--end component;

component carr
port (
CLK: IN std_logic;
ACLR: IN std_logic;
SINE: OUT std_logic_VECTOR(13 downto 0));
end component;
component adder
port (
A: IN std_logic_VECTOR(13 downto 0);
Q: OUT std_logic_VECTOR(15 downto 0);
CLK: IN std_logic);
end component;
component mul
port (
clk: IN std_logic;
a: IN std_logic_VECTOR(13 downto 0);
b: IN std_logic_VECTOR(15 downto 0);
q: OUT std_logic_VECTOR(29 downto 0));
end component;

--------------------------------------------------------------------

begin

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---------------------DAC RESET SETTINGS ----------------------------

DAC1_MOD0 <= '0';

DAC1_MOD1 <= '0';
DAC2_MOD0 <= '0';
DAC2_MOD1 <= '0';

-- disable resets for DACs

DAC1_RESET <= '0';
DAC2_RESET <= '0';

-- optimum settings for sampling rate

DAC1_DIV0 <= '1';
DAC1_DIV1 <= '0';
DAC2_DIV0 <= '1';
DAC2_DIV1 <= '0';

-----------------------COMPONENT PORT MAPPINGS ---------------------

--u1 : msg
-- port map (
-- CLK => CLK_10M,
-- ACLR => rst,
-- SINE => msg_out);

u2 : carr
port map (
CLK => CLK_10M,
ACLR => rst,
SINE => carr_out);

u3 : adder
port map (
A => msg_out,
Q => adder_out,
CLK => CLK);

u4 : mul
port map (
clk => clk,
a => carr_out,
b => adder_out,
q => mul_out);

---------------EXTERNAL INPUT BLOCK -------------------------------

process(clk,rst)
begin
if(rst='1') then
msg_out <= "00000000000000";
elsif(clk'event and clk='1') then
msg_out <= message;
end if;
end process;

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--------------------CLOCK DIVISION BLOCK -------------------------

process(clk,rst)
begin
if(rst='1') then
clk_10M <= '0';
cnt <= 0;
elsif(clk'event and clk='1') then
if(cnt=4) then
clk_10M <= not clk_10M;
cnt<= 0;
else
cnt <= cnt +1;
end if;
end if;
end process;
------------------------------------------------------------------

am_out <= mul_out(29 downto 16);

am_out <= not(not am_out1(13) & am_out1(12 downto 0)); --BINARY OFFSET

end Behavioral;
Listing 12.4: AM Demodulation in Real-Time
-----------------------------------------------------------------------
--File name: am_demod.vhd
-- Create Date: 17:08:22 08/08/2007
-- Design Name:
-- Module Name: am_demod - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity am_demod is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
message :in std_logic_vector(13 downto 0);
am_in :in std_logic_vector(13 downto 0);

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 Case Study: Implementation of a Communication System

--------------------- DAC SETUPS ------------------------------------

-- dac reset signals
DAC1_RESET : out std_logic;
DAC2_RESET : out std_logic;
-- dac setup
DAC1_MOD0 : out std_logic;
DAC1_MOD1 : out std_logic;
DAC2_MOD0 : out std_logic;
DAC2_MOD1 : out std_logic;
-- dac clock divider setup
DAC1_DIV0 : out std_logic;
DAC1_DIV1 : out std_logic;
DAC2_DIV0 : out std_logic;
DAC2_DIV1 : out std_logic;
-----------------------------------------------------------------------
am_out :out std_logic_vector(13 downto 0);
dmod_out : out STD_LOGIC_VECTOR (13 downto 0));
end am_demod;

architecture Behavioral of am_demod is

-----------------INTERNAL SIGNAL DECLARATIONS----------------------

-------------------------------------------------------------------
signal am_out1 :std_logic_vector(13 downto 0);
signal msg_out,am_in1 :std_logic_vector(13 downto 0);
signal rfd,rdy :std_logic;
signal clk_10M :std_logic;
signal cnt :integer;
signal envelope :std_logic_vector(13 downto 0);
signal lpf_out :std_logic_vector(36 downto 0);
signal lpf_out1 :std_logic_vector(13 downto 0);

--------SIGNALS FOR STATE MACHINES --------------------

type state_t is (s0,s1,s2);
signal state_v : state_t;
signal prev_val,present_val :integer;
signal out1 : integer;

-----------------COMPONENT DECLARATIONS ---------------------------

component am_mod
port(
clk :in std_logic;
rst : in std_logic;
message :in std_logic_vector(13 downto 0);
am_out :out std_logic_vector(13 downto 0));
end component;

component lpf_norm
port (
sclr: IN std_logic;
clk: IN std_logic;
nd: IN std_logic;

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din: IN std_logic_VECTOR(13 downto 0);

rfd: OUT std_logic;
rdy: OUT std_logic;
dout: OUT std_logic_VECTOR(36 downto 0));
end component;
-------------------------------------------------------------------

begin

-------------- DAC RESET DECLARATIONS ----------------------------

DAC1_MOD0 <= '0';
DAC1_MOD1 <= '0';
DAC2_MOD0 <= '0';
DAC2_MOD1 <= '0';

-- disable resets for DACs

DAC1_RESET <= '0';
DAC2_RESET <= '0';

-- optimum settings for sampling rate

DAC1_DIV0 <= '1';
DAC1_DIV1 <= '0';
DAC2_DIV0 <= '1';
DAC2_DIV1 <= '0';

-------------------COMPONENT PORT MAPPINGS ------------------------

u5: am_mod
port map(
clk => clk,
rst => rst,
message => msg_out,
am_out => am_out1);

u6 : lpf_norm
port map (
sclr => rst,
clk => clk_10M,
nd => '1',
din => envelope,
rfd => rfd,
rdy => rdy,
dout => lpf_out);

--------------------CLOCK DIVISION BLOCK-------------------

process(clk,rst)
begin
if(rst='1') then
cnt <= 0;
clk_10M <= '0';
elsif(clk'event and clk='1') then
if(cnt=4) then
clk_10M <= not clk_10M;
cnt <=0;
else
cnt <= cnt +1;

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end if;
end if;
end process;

----------- BLOCK FOR EXTERNAL INPUT -------------------

process(clk,rst)
begin
if(rst='1') then
msg_out <= "00000000000000";
am_in1 <= "00000000000000";
elsif(clk'event and clk='1') then
msg_out <= message;
am_in1 <= am_in;
end if;
end process;

-----------STATE MACHINE FOR ENVELOPE DETECTOR------------

process(clk_10M,rst)
begin
if rst = '1' then
present_val <= 0;
else
present_val <= conv_integer(am_out1);
end if;
end process;

process(clk_10M,rst)
begin
if rst = '1' then
prev_val <= 0;
elsif (clk_10M'event and clk_10M = '1') then
prev_val <= present_val;
end if;
end process;

process(clk_10M,rst)
begin
if rst = '1' then
state_v <= s0;
out1 <= 0;

elsif (clk_10M'event and clk_10M = '1') then

case state_v is
when s0 =>
if prev_val < present_val then
state_v <= s1;
elsif prev_val > present_val then
state_v <= s2;
else
state_v <= s0;
end if;

out1 <= 0;

when s1 =>

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Chapter 12

if (prev_val <= present_val) then

state_v <= s1;
elsif prev_val > present_val then
state_v <= s2;
out1 <= prev_val;
end if;

when s2 =>
if prev_val < present_val then
state_v <= s1;
elsif prev_val >= present_val then
state_v <= s2;
end if;
end case;
end if;
end process;

envelope <= conv_std_logic_vector(out1,14);

----------------------------------------------------------------------

lpf_out1 <= lpf_out(33 downto 20);

am_out <= not(not am_out1(13) & am_out1(12 downto 0));--Binary offset

dmod_out <= not(not lpf_out1(13) & lpf_out1(12 downto 0));--Binary offset

end Behavioral;

Generating Bit File

After modifying the source code as given in the preceding listings, you need to generate the bit file. The
procedure for generating the bit file is as follows:
Step1:
 Select User Constraints in the Processes dialog box of the Xlinix main window.
 Select Create Area Constraints in the User Constraints menu, as shown in Fig 12.51:

Figure 12.51: Displaying the Processes Dialog Box

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 Case Study: Implementation of a Communication System

 Right-click the Create Area Constraints option. A pop-up menu appears.

 Select the Run option from the pop-up menu and run the Create Area Constraints process.
Step 2:
 After running the Create Area Constraints process, the Xilinx PACE window opens where you can
assign pin locking for ADCs and DACs, as shown in Figure 12.52:

Figure 12.52: Displaying the Xilinx PACE Window

In Fig 12.52, you can assign suitable pins in the Design Object List – I/O Pins window. After assignment of
pins, the Xilinx PACE window appears, as shown in Figure 12.53:

Figure 12.53: Displaying the ADC and DAC Pin Assignments

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Step 3:
 Go to the Processes dialog box, select Generate Programming File, and run it.
It will generate the bit file, which you can locate in the project folder.
Step 4:
 Generate the clock bit file for Virtex-2 (XC2V80-4CS144) after completion of the bit file generation for
am_dmod.vhd.
 Create a new project and generate the required clock based on the source code, given in Listing 12.5:
Listing 12.5: Clock Generation
--Clock Generation
--Filename: clk_10m-vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity OSC_CLOCK is
Port ( OSC_IN : in std_logic;
rst : in std_logic;
DAC0_CLKp : out std_logic;
DAC0_CLKn : out std_logic;
DAC1_CLKp : out std_logic;
DAC1_CLKn : out std_logic;
ADC0_CLKp : out std_logic;
ADC0_CLKn : out std_logic;
ADC1_CLKp : out std_logic;
ADC1_CLKn : out std_logic;
clk_out : out std_logic
);
end OSC_CLOCK;

architecture Behavioral of OSC_CLOCK is

component IBUF
port ( I: in std_logic;
O: out std_logic
);
end component;

component OBUFDS
port ( O: out std_logic;
OB: out std_logic;
I: in std_logic
);
end component;

component OBUF
port ( I: in std_logic;
O: out std_logic
);
end component;

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 Case Study: Implementation of a Communication System

--signal OSC_OUT: std_logic;

--signal OSC_OUTl: std_logic;
signal cnt :integer;
signal clk :std_logic;
signal clk_10M ,clk_105M: std_logic;

begin
process(clk,rst)
begin
if(rst='1') then
cnt <= 0;
clk_10M<= '0';
elsif(clk'event and clk='1') then
if(cnt=4) then
clk_10M <= not clk_10M;
cnt <=0;
else
cnt <= cnt+1;
end if;
end if;
end process;

clk_105M<= clk;
H6: IBUF port map (I => osc_in, O => clk);

H1: OBUFDS port map (I => clk_105M, O => DAC0_CLKp, OB => DAC0_CLKn);
H2: OBUFDS port map (I => clk_105M, O => DAC1_CLKp, OB => DAC1_CLKn);
H3: OBUFDS port map (I => clk_105M, O => ADC0_CLKp, OB => ADC0_CLKn);
H4: OBUFDS port map (I => clk_10M, O => ADC1_CLKp, OB => ADC1_CLKn);
H5: OBUF port map (I => clk_105M, O => CLK_OUT);

end Behavioral;
--End of source code

In the preceding code, 105 MHz is the clock frequency at which the FPGA board operates. You need to generate the
necessary clock frequency based on your requirements.

Step 5: Generate the bit file for clock by using the same procedure as explained in the steps 1, 2, 3, and 4.
Step 6: Open the FUSE software by clicking the following icon:

A window called FUSE Probe opens, as shown in Figure 12.54:

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Figure 12.54: Displaying the FUSE Probe Window

Step 7: Open the cards by clicking the Open Card button, as shown in Figure 12.55:

Figure 12.55: Displaying the FUSE Probe Window

Step 8: Assign the bit files of clock (Virtex-2) and main code (Virtex-4) to the respective FPGAs.
The FPGA board is a communication system that carries out AM Modulation and Demodulation.

260
 Case Study: Implementation of a Communication System

Step 9: Give the inputs to the ADCs and observe the outputs of DACs on either an oscilloscope or a
spectrum analyzer.
You can connect the ADC output to an oscilloscope or a spectrum analyzer to observe the modulated
output. In addition, you can loop back, obtain the demodulated output, and observe the demodulated
signal at the DAC output.
Instead of giving the single tone as input, you can also input voice and observe the output. If the voice
output from the DAC is of the same quality as that of the voice input to the ADC, then you are sure that
your AM/demodulation implementation in the FPGA is working fine.

Challenges in Signal Processing using FPGA

Signal processing using FPGAs is a very exciting and challenging area. In the case study given in this
chapter, you can observe that you need to implement different algorithms. In addition, you need to
implement different types of filters, such as low pass, high pass, and band pass. The limits of FPGA
performance will be tested when you work in this area. In particular, the challenges are in the areas of:
 Designing filters
 Optimizing the design by choosing the correct algorithms
 Reducing the delays
 Reducing the gate count
 Low power design
 Isolating the problem while testing—whether it is in hardware or software
The most important point to be taken into consideration while implementing signal processing algorithms
in an FPGA are the finite word length effects.

Summary
You can implement a communication system on an FPGA board that has the necessary ADC and DAC
components. The ADC and DAC have to be chosen keeping in view the frequencies of the input and
output signals. You can interface an ADC and a DAC to the FPGA. Then you can digitize the signal and
carry out the entire signal processing within the FPGA. This technique is used in various applications,
such as audio processing, video processing, imaging, software radio, and wireless communication. To
implement filters, such as low pass, high pass and band pass, you can generate the filter coefficients using
MATLAB and then use them in the Xilinx ISE. While implementing digital signal processing algorithms in
an FPGA, care needs to be taken by giving due consideration to the finite word length effects.

Questions
1. You can implement digital signal processing algorithms in an FPGA.
(a) True (b) False
2. A signal has a bandwidth of 20 KHz. The minimum sampling frequency is
(a) 20 KHz (b) 40 KHz (c) 80 KHz (d) 40 MHz
3. An anti-aliasing filter is an optional component before analog to digital conversion.
(a) True (b) False
4. The DDS is used to generate a signal of desired frequency
(a) True (b) False
5. Finite word length effects are not significant in an FPGA implementation.
(a) True (b) False

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6. In AM, the carrier signal is added to the message signal.

(a) True (b) False
7. To generate a carrier frequency of 455 KHz, the sampling frequency that can be used is
(a) 455 KHz (b) 10 MHz (c) 10 KHz (d) 1 KHz
8. You have implemented an AM communication system with 455 KHz carrier frequency. If you change
the carrier frequency to 1 MHz, you need to change the
(a) Code only (b) FPGA only (c) Code and FPGA
(d) The complete development board
9. To get analog output, the FPGA has to be interfaced with
(a) ADC (b) JTAG port (c) External clock (d) DAC
10. To give analog input to an FPGA, the FPGA has to be interfaced with
(a) ADC (b) DAC (c) External clock (d) JTAG port

Exercises
1. Study the data sheets for ADC and DAC components used in the development board described in this
chapter.
2. Instead of using a carrier frequency of 455 KHz, can you use a carrier frequency within the high
frequency band? What factors are to be considered to check whether the development board can
support this change in the carrier frequency?

262
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Case Study:
System-On-Chip
Development
If you need an information on: See page:
System-On-Chip Requirements 264
Design 265
Implementation 266
Chapter 13

System-On-Chip Requirements
In the present day scenario, there have been great advancements in process technologies that lead to
high-speed devices, such as Application Specific Integrated Circuit (ASIC) chips, Random Access
Memory (RAM) chips, microprocessors, and multicore processors. The most challenging task for
electronic system designers is to meet the time-to-market deadline and chip size. Modern integrated
systems are designed with combination of many functional blocks comprising processor cores, dedicated
communication interfaces, on-chip memories, and buses to meet the market demands. These
advancements have made possible the development of System-On-Chip (SOC) devices.
SOC is an integrated circuit that includes a processor, a bus, and other elements on a single monolithic
substrate. These complete systems integrated onto a single chip are called SOC. It enables you to
combine a number of gates to build complex functions to meet market demands. In other words, this
enables semiconductor manufacturers to meet specific system requirements cost-effectively while
delivering competitive time-to-market advantage. Added advantage of integration onto one-chip is
reduction of power consumption and area.
Complex functionalities previously required using heterogeneous devices are placed on a Printed Circuit
Board (PCB). Digital systems designed with PCB result in area and power consuming digital systems.
These PCBs having several chips in one package are replaced into one single integrated chip with all the
components built in as SOCs. Present day digital products, such as those used in hand-held devices, are
replaced by SOC design.
Following are the examples of SOCs:
 Smart phones with features of camera
 Video Graphics Array (VGA) displays
 Bluetooth
 Multi format music players
Various components in a typical SOC components are given as follows:
 Volatile memory systems and non-volatile memory systems
 RAM, Electrically Erasable Programmable Read Only Memory (EEPROM), flash memories, and
on-chip memories
 Processing units
 Accelerated functional units and graphical processors units
 General purpose processor- multiprocessor
 Specific purpose processor – microcontroller
 Digital signal processors
 Mixed signal circuits and logic circuits
 Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC)
 Micro electronic and mechanical systems
 Oscillators and phase-locked loops
 Optical input-output sensors
 Radio frequency components
 Communication channels
 High speed bus and Direct Memory Access (DMA) controllers
Following are some of the advantages of SOC devices:

264
 Case Study: System-On-Chip Development

1. Lower manufacturing cost, package requirements, and board cost

2. Decreased size
3. Reduced power consumption
Constructing a chip from given specifications to fabrication is a major task in the Very Large Scale
Integration (VLSI) design era. However, a significant improvement in Computer Aided Design (CAD)
techniques and circuit designs is required to create SOC designs. Successful implementation of such
systems requires the development of new design tools to meet the requirements of the end-user.
However, there are certain challenges in the form of complex functionalities, timing closure
requirements, and verification of design. Some factors involved to meet these challenges and make a
successful SOC design from specifications to fabrications are as follows:
1. Specified design must be ensured to be correct in hierarchical structure
2. Functional correctness under various constraints, such as clock, power, voltage, and thermal
conditions
3. Reliability of the product during its lifetime
4. Reduced effort in manufacturing process
5. Economic package requirements
6. Power dissipation and consumption within the limit
7. Battery backup charges
8. Cost effective cooling mechanism
9. Support for more functionalities and reusability feature
10. Manufacturing cost must be minimum
11. Manufacturing time must be very less to compete with market demands
12. Increase in speed of the device

Design
As already learned, requirements for SOC give a clear idea to design an efficient SOC. The designs of
SOC in several application domains are often subject to requirements in terms of processing
performance and flexibility. Programmability feature also plays a vital role in these single-chip
architectures; thereby, offering the desired flexibility in the design, while maintaining the advantages of
customized VLSI solutions, such as optimized power dissipation and processing performance.
To create a flexible and low-cost design in a short cycle, design reusability principle enables robustness,
modularity, and configurability in design. Design reusability implies that hardware and software
component designs for specific or general purpose can be reused to accomplish the task with
modifications. This method of designing SOC is called Intellectual Property (IP) based SOC design.
As time-to-market pressures and product complexities climb, the need to reuse complex building blocks
or components (known as IP or virtual component) also increases. Advantage of reusability is to ensure
correctness and decrease in design time. Some components, such as processor architectures (RISC,
SPARC, and ARM) and functions for specific domain, such as signal processing (DCT and FFT),
telecommunication, and multimedia (VLC and Turbo codes) are used as reusable components to build
SOCs. Therefore, an important issue arises that how to use these hardware or software components and
to what extent.
Depending on the application, various application-specific architectures using different execution
models and combinations of software and hardware components may be required; for example,
flexibility in programmability, performance, and power computing. Even the choice of the

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programmable processor is heavily dependent on the application. The processor communicates with
dedicated hardware accelerators through a standard on-chip hardware/software bus, such as Amba,
Avalon, and IBM CoreConnect, using control logic and specific memory blocks. Coprocessors and
hardware accelerators usage depends on the application complexity and the computing constraint
requirements. To give more flexibility and adaptability to the SOC, the reconfigurable technology plays
an important role.
IP-based designs are divided into three categories based on their flexibility feature to the designer’s
point of view to make an efficient and easy way to reuse the components.
Classification of IP-based design approaches is as follows:
 Hard core/hard IP
 Soft core/soft IP
 Firm core/firm IP
Let’s learn about these approaches in detail.

Hard Core/Hard IP
Designers provide a design in a black box form, which is a layout of the component with details about
basic information, such as functionality, input, and output details. Designers can use it as a component
without changing the functionality, but input combinations can vary. These designs are encrypted and
optimized. The black boxes are verified, synthesized, and then given to the designer in the form of
layouts. The disadvantage of hard core/hard IP is that functionalities are very hard to modify. Example
of a hard core/hard IP is microprocessors.

Soft Core/Soft IP
A designer can choose soft core IP components where the components can be redesigned with minor
modifications based on specifications. Register transfer level design written in any Hardware
Description Language (HDL) is simulated and synthesized to ensure the correctness of functional
behavior. Designer is responsible to design with respect to timing, delay, and power constraints. This is
more flexible for designers. The advantages of soft core/soft IP are easy to modify functionalities and
easy to change processes.

Firm Core/Firm IP
A simulated netlist is given in the form of gate-level netlist to the designer. Gate-level netlist consists of
gates and the interconnections between the gates. There is flexibility to change the connections between
nodes and synthesize the design. The visibility of the design in this case is more as compared to the hard
core/hard IP to the designers. The disadvantage of firm IP is hard to modify the functionalities of
modules; however, its advantage is easy to change processes.
Typically, these cores act as a platform to generate a required application onto a single chip. Let’s now
discuss how these different types of cores are useful for SOC implementation.

Implementation
SOC implementation management requires a robust co-design environment to master the complexity
and different refinement steps of the system from a high-level specification.
Any embedded application can be built using common architecture blocks and customized specific
components. Processors, memories, and bus interfaces are some examples of common architectures;
whereas, IP tools and IP library components are examples of customized specific components. Common
architectures and supporting technology components to use these common architectures are called

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platforms. Cores are provided to the designers as a platform to build SOCs by stitching the components
together for a specific application with the help of platforms known as platform-based systems for
development applications.
Platforms are not just hardware components. They consists of IP blocks in the form of hardware
components (embedded computer processing unit and memory), supporting components (real world
interfaces and mixed signal blocks), and software components (device drivers, real-time operating
systems, and application codes) for developing applications onto SOCs,
IP blocks or cores can be taken in the hard form, soft form, or firm form and added onto the design to
generate SOC for the required application. These basic components can be packaged in terms of
hardware or software elements and delivered to the customer for application development. Components
used in this case are not silicon compilation but using the components that are provided by the
manufacturers include both hardware and software components. This method of designing is known as
platform-based architectures.
These design approaches can be performed in block-based or platform-based architectures.
Following are the various classes of platforms:
 Full application platforms—These platforms allow derivative product designers to create complete
component by using the IP cores in terms of hardware modules and develop software on top of the
platform provided. For example, a complex dual processor architecture with hierarchical bus
systems combined to generate a specific application. A software component is to be developed to
use these platforms effectively. Examples of full application platforms are multiple processors
SOCs, hardware blocks, mixed signal elements, and customized software.
 Processor centric platforms—Centered on specific processors (ARM), ST Microelectronics provide
software services, such as real time kernels to develop SOC on those platforms.
 Communication centric platforms—Basic objective of these platforms is to provide communication
fabric optimized for applications related to communications.
 Configurable Platforms—Designers can configure the device based on the applications. Field
Programmable Gate Arrays (FPGAs) are devices that consist of an array of configurable blocks with
programmable interconnects. With the help of these configurable blocks, designers can customize
the device in terms of both hardware and software. Altera and Xilinx are commercial vendors that
provide FPGAs devices. Altera FPGA devices consist of ARM core as IP library component;
whereas, Xilinx Virtex-II Pro consists of PowerPC.

Selection of Platform based on Application

The selection of platform and IP core in any of the three forms (hard, soft, or firm) corresponds to the
selection criteria for the target application. The key parameters to be considered are as follows:
 The IP core processor must be characterized by a heterogeneous architecture
 Programmable logic elements
 DSP blocks
 Memory elements, such as RAM blocks
 Input/output pins
 Interface to integrate hardware and software of the SOC
 Integrate some co-processors within its Arithmetic Logic Unit
 Application-Specific Instruction Set Processor (ASIP) model
 Hardware accelerators must be linked by an on-chip hardware/software bus

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 Integrated with on-chip hardware/software communication module

 Real Time Operating System (RTOS) option with the corresponding port to the targeted IP
processor core
 The hardware and software refinement tools must be robust and efficient to limit the time-to-market
constraint

Summary
SOC consists of two or more complex components integrated onto a single chip. With the advent of deep
sub-micron technology, there are tight constraints on power consumption of VLSI circuits. Examples of
SOC devices are mobile devices that are hand-held and battery-operated with smart features integrated
on a chip. Based on design reuse principle, SOCs are generated for a specific application. Advantages of
SOC are power optimization and cost effective designs. The different forms of IP designs are hard, soft,
and firm. These forms create a platform, which consists of common architecture blocks in any of three
forms and software components associated to interconnect these blocks. The SOCs are implemented on
block-based designs or platform-based designs.

Questions
1. Why SOCs are performance oriented designs?
2. Write the details of various forms of IP designs.
3. What are the advantages of hard core IP over soft core IP?
4. What is platform? What are different types of platforms?
5. Explain the implementation strategy of SOC designs.

Exercises
1. Draw the SOC architecture for smart-mobile devices.
2. Discuss the requirements for network-based applications.
3. Device the requirement for network-on-chips.
4. Derive a procedure to design SOC for video conference.

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 14
Future Trends
If you need an information on: See page:
Ubiquitous Computing and Pervasive Computing Technologies 270
VLSI Design Trends 271
Chapter 14

The developments in the last few decades in Very Large Scale Integration (VLSI) technology paved way
for many exciting applications as well as miniaturization of computing devices. This is just the beginning.
In future, we are going to witness revolutionary developments in VLSI design with the invention of new
devices and their models as well as nano-technology, which is becoming a commercial viability. The
Electronic System Level (ESL) tools will make the design of VLSI chips a child’s play. All these
developments will result in invisible computing, which is extremely powerful computing devices that are
very small and invisible.

Ubiquitous Computing and Pervasive Computing Technologies

Ubiquitous computing, as the name implies, means computers everywhere. Ubiquitous computing shares
a vision of tiny, economical, robust networked processing devices, embedded in a system and distributed
at all scales throughout everyday life. According to the founder of ubiquitous computing, Mark Weiser,
during 1988 while working at XEROX PALO Alto Research Center (PARC) as a chief technologist, had a
vision of new generation of computing devices that involves technology everywhere but invisible.
According to Dan Russell, director of User Sciences and Experience Group at IBM's Almaden Research
Center, by the next decade, computing will become so naturalized within the environment that people will
not even realize that they are using computers. According to the researchers, smart devices all around us
will maintain current information about their locations, the contexts in which they are being used, and
relevant data about the users to guide.
Pervasive computing and calm technologies, synonyms of ubiquitous computing, are connected
computing devices in the environment. Among the emerging technologies, pervasive computing
environment includes smart homes, smart computers or wearable computers, and smart buildings. Most
interesting and challenging task is making the ubiquitous computing a reality.
The goal of ubiquitous computing is that instead of using computers as distinct objects, computers would
be embedded everywhere in environment and built into the objects so that they can be used in day-to-day
life. These devices sense the changes in the environment, and adapt and act based on the changes. For
example, ubiquitous computing environment might interconnect with environmental controls through
effective sensors and possess high-speed networking facilities. The necessary measurements are suggested
on smart devices with the help of high-speed inter-networking facilities. Although it sounds like a crazy
idea, but this will come into reality in future with invisible computing capabilities. Several applications of
ubiquitous computing, such as smart cards, Radio Frequency IDentification (RFID), mobile devices, and
monitoring devices, have become part of day-to-day life activities for human beings.
To achieve success in this era of computing, the researchers need to address the problems, such as how to
create a system that is embedded in the environment, fully connected network to support these systems,
intuitive, portable and almost invisible computers, and constantly available. To succeed in this direction,
pervasive computing environment must address the following issues:
 Smart environment to adapt new technologies
 Interoperability to communicate across the devices
 Minimum effort to adapt new technologies
 Ensure reliability for secure data transfers
 Inference in the presence of ambiguity
 Study the limitations of location aware technologies
Research in ubiquitous computing presents challenges across computer science field. Wireless networking
needs to be developed to accommodate remote computers hiding or embedded in environment. Besides
wireless technology, networking issues, such as real-time capabilities for multimedia over standard
networks and efficient packet routing, need to be addressed. In addition, high-speed devices with

270
 Future Trends

minimum power requirements need to be addressed. Existing devices that support pervasive computing
are smart devices with flexible/invisible transistor size, specific-purpose devices (Application Specific
Integrated Circuits), reconfigurable architectures (Field Programmable Gate Arrays), smart sensors, and
computing devices with network- on-chip/systems-on-chip. Apart from these challenges, issues to be
addressed in the areas, such as distributed computing, semantic Web, artificial intelligence, Web ontology,
reinforcement learning, and human computer interaction, are to develop a modeling language to express
complex nature of ontologies.
The research has been carried out actively at various leading institutions as a part of ubiquitous
computing. Some of the institutions with details of the projects undergoing in the ubiquitous/pervasive
computing field are listed as follows:
 Xerox's PARC has been working on pervasive computing applications since 1980s.
 IBM's project Planet Blue, focused on finding ways to integrate existing technologies with a wireless
infrastructure.
 Carnegie Mellon University's Human Computer Interaction Institute (HCII) is working on a project
named Aura, whose stated goal is to provide each user with an invisible halo of computing and
information services that persists regardless of location.
 Massachusetts Institute of Technology (MIT) has a project called Oxygen. MIT named their project
after oxygen because they envision a future of ubiquitous computing devices as freely available and
easily accessible as oxygen.
Let’s now learn about the importance of VLSI technologies to meet the challenges in pervasive
technologies.

VLSI Design Trends

In the current and coming decades, VLSI design currently enables you to build million-transistor chips:
Giga-Scale Integration (GSI) design and Tera-Scale Integration (TSI) design. GSI signifies more than one
billion transistors per chip; whereas, TSI signifies more than one trillion devices per chip. This gives
insight that future developments of VLSI, also termed as Ultra Large Scale Integration (ULSI) devices,
require innovation in various fields to meet the challenges in design trends.
The trend toward single-chip solutions will continue to increase indefinitely for all types of systems. Time-
to-market pressure increases the demand for reliability of chips and power-aware designs, and most
efficient and sophisticated Electronic Design Automation (EDA) tools. Some of the major trends in VLSI
design are identified and detailed with insight into the importance of VLSI design. The four major goals to
meet the time-to-market are as follows:
1. Decrease in device feature size
2. Increase in the complexity of the circuit on same surface area of chip
3. Increase in speed of digital circuits
4. Sophisticated Computer Aided Design (CAD) tools
Let’s discuss the challenges to meet the requirements for each of the four goals:
 Decrease in device feature size:
 Some of the design challenges involved in shrinking the feature size leads to:
1. Increase in transistor leakage and interconnect delays
2. Increase in problems related to power dissipation
3. Increase in costs for fine resolution processing in photolithographic

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 Increase in the complexity of the circuit and device count on a chip:

 Challenges involved in embedding the complexity on same surface area are as follows:
1. Increase in the complexity of logic leads to the increase in power consumption
2. An efficient heuristics are required to perform optimization at various levels, such as area,
power consumption, delay, and power dissipation
3. Increase in power consumption demands more sophisticated cooling and expensive
packaging mechanisms to sustain the power dissipations
4. An efficient long life batteries are required that sustains particularly for chips used for mobile
applications
 Increase in speed of digital circuits and reliability of design:
 Challenges involved in designing high-speed VLSI circuits are as follows:
1. Transistors need to be built with high mobility substance
2. Gallium Arsenide substance is one of the solution to increase the frequency of clock
3. Reliability factor depends mainly on power consumption, power dissipation, transistor
leakage, quality of fabrication, and fault tolerance techniques
4. Large systems also lead to thermal problems even with low dissipation technology
5. Thermal simulation and modeling plays a major role in the design process
Powerful EDA/ESL tools:
In the present day scenario, integrated circuits are designed mainly with Hardware Description
Languages (HDLs), such as Verilog and VHDL, at Register Transfer Level (RTL).
During the process of design flow, verification process takes place at every stage to check the functional
specifications and meet the design constraints, such as area and power. Functional verification causes the
design flow to re-spin. As per the records, 75% of designs re-spin at functional verification stage itself. As
the complexity of the circuit increases, the verification gap increases, which in turn affects the productivity
of design. A refinement in design productivity process is done to meet the continuous improvement in
design productivity.
Two approaches to improve design productivity are as follows:
1. Improvement at design level, that is, RTL to Higher Abstraction Level (HAL)
2. Design reuse methodology
ESL design is a new approach used to design integrated circuits at HAL. The ST Microelectronics initiated
the ESL design tools to meet the challenges in design productivity. The challenges for successful ESL
design tools are as follows:
 To reduce the re-spins at functional verification stage
 An efficient debugging methods to meet the design constraints
The general design flow in ESL tools is as shown in Figure 14.1:

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 Future Trends

Figure 14.1: Displaying the Design Flow of ESL Tools

The three phases in the design flow of ESL tools are specification, exploring, and refining. The functional
specification takes place at the specification phase; and during the exploring phase, design requirements
are compared to meet the constraints, such as power consumption, delay of the circuit, and area of the
circuit that are mapped onto the target device. To meet the design constraints, the process of re-spin takes
place in the refining phase. After the constraints are satisfied, final product is released to further phases of
CAD flow, which are placement, routing, and fabrication unit.
Some of the ESL commercial tools are given as follows:
1. System C or Spec C are system level design languages/tools: System C is open source software and
can be compiled with a standard C++ compiler. It is a standard language for specifying
hardware/software systems at various levels of abstraction, namely system level, behavioral level,
and RTL.
Spec C is a standard language with American National Standards Institute (ANSI). This language is
compiled using a C compiler.
2. Transaction Level Modeling (TLM) synthesis tool: In the TLM synthesis tool, designer describes the
model using behavioral model, which is an abstract level description of design written in System C.
The code is then synthesized using function calls. Synthesizer creates an equivalent RTL
implementation with appropriate interfaces.
3. TLM ignores detailed description of code at early stage of design, which in turn reduces the errors in
coding and improves the simulation performance.

Summary
The topics presented in this chapter include the introduction of state-of-the-art computing technologies,
such as ubiquitous computing and its various challenges to come to a reality in present day era. The
challenges in pervasive computing need to be addressed by researchers are identified as a smart
environment to adapt new technologies in short-turnaround time. Interoperability feature is to be
incorporated across the devices and reliability for secure data transfers at the cost of location-ware
technologies.

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Chapter 14

An insight about the projects related to pervasive/ubiquitous undergoing successfully at Xerox Palo Alto
research center, IBM, Carnegie Melon University, and MIT are detailed. In this chapter, the trends in VLSI
design are identified and discussed. An increase in circuit complexity and device count on a die is vital to
meet the demands of time-to-market trend for VLSI designs. Another important trend is increase in
designer’s productivity that leads to demand for highly sophisticated CAD tools. ESL tools provide
solutions to meet the requirements of designer’s productivity and reusability. Design flow of ESL tools
consists of three phases: specification, exploring, and refining. System C and Spec C are languages,
provided for behavioral level or abstraction level description of the design, are compiled with C/C++
compilers. These tools synthesize the high-level designs into RTL code and aid for further steps.

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 A
VHDL and Verilog Examples
This appendix contains the source code with simulation results to give the VHSIC Hardware Description
Language (VHDL) and Verilog Hardware Description Languages (HDLs) code usage.
The VHDL source code, test bench for functional simulation, simulation results using waveforms, and
synthesis report generated by the Xilinx ISE tool are given. Some of the examples listed as follows are also
solved:
 4-bit comparator
 4-bit binary counter
 Decoder
 De-multiplexer
 D flip-flop
 Dual Port Random Access Memory (DPRAM)
 Queue
Verilog source code and test bench with sample output is listed for the following two examples:
 4-bit ripple adder
 4x4 sequential and array multiplier

Comparator
Block Diagram:-
Appendix A

DESCRIPTION:- A 4-bit two input comparator compares two inputs (inputa and inputb) and gives
output (comp) as high if both the inputs are equal; otherwise, the output remains low.
Input ports:
a. Inputa (3 downto 0) : 4-bit input data a
b. Inputb (3 downto 0) : 4-bit input data b
Output port:
a. comp : Single bit output to indicate whether inputa and inputb are equal or not. If they are equal, then
comp is asserted high.
----PROGRAM OF COMPARATOR----
-- Title : comparator
-- Project : jntu
-------------------------------------------------------------------------------
-- File : comparator.vhd
-- Author : <ICS@SOMESH>
-- Created : 2006/02/01
-- Last modified : 2006/02/01
-------------------------------------------------------------------------------
-- Description : comparator to compare to no.’s
-------------------------------------------------------------------------------
-- Modification history :
-- 2006/02/01 : created
-------------------------------------------------------------------------------

library ieee; -- library declaration

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity my_comp is -- entity declaration

generic (size : integer := 4);

port (inputa : in std_logic_vector((size -1) downto 0); -- input data of port A

inputb : in std_logic_vector((size -1) downto 0); -- input data of port B

comp : out std_logic -- output port

);

end my_comp;

architecture my_comp_a of my_comp is

begin -- my_comp
comp <= '1' when (inputa = inputb) else '0'; -- comparering both
the input
end my_comp_a;

----TEST BENCH FOR COMPARATOR----

-------------------------------------------------------------------------------
-- Title : comparator test bench
-- Project : jntu
-------------------------------------------------------------------------------

276
 VHDL and Verilog Examples

-- File : comparator_ts.vhd
-- Author : <ICS@SOMESH>
-- Created : 2006/02/07
-- Last modified : 2006/02/07
-------------------------------------------------------------------------------
-- Description :test bench for comprator
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY comparator_vhd IS
END comparator_vhd;

ARCHITECTURE behavior OF comparator_vhd IS

-- Component Declaration for the
Unit Under Test (UUT)
COMPONENT my_comp
PORT(
inputa : IN std_logic_vector(3 downto 0);
inputb : IN std_logic_vector(3 downto 0);
comp : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL inputa : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL inputb : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL comp : std_logic;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: my_comp PORT MAP(
inputa => inputa,
inputb => inputb,
comp => comp
);
tb : PROCESS
BEGIN
inputa <= inputa + 1; -- input to inputa
inputb <= inputb + 3; -- input to inputb
-- Wait 100 ns for global
reset to finish
wait for 100 ns;

if now >= 4000 ns then

report " simulation completed successfully";
wait; -- will wait forever
end if;
END PROCESS;
END;

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Appendix A

SIMULATION RESULT
a. functional simulation

b. post place and routed simulation with delays

Timing summary:
----------------------------
Maximum path delay from/to any NODE: 5.836ns

Device Utilization Summary

virtex4
Target Device : xc4vfx12
Target Package : sf363
Target Speed : -12

Mapper Version : virtex4

Logic Utilization Used Available Utilization Note(s)

Number of 4 input LUTs: 3 10,944 1%

Logic Distribution:

Number of occupied Slices: 2 5,472 1%

Number of Slices containing only related logic: 2 2 100%

Number of Slices containing unrelated logic: 0 2 0%

Total Number of 4 input LUTs: 3 10,944 1%

Number of bonded IOBs: 9 240 3%

278
 VHDL and Verilog Examples

Counter
Block Diagram:-

DESCRIPTION:- A 4-bit counter has two inputs, reset (rst) and clock (clk), and two outputs, output (3
downto 0), which gives one count value on each positive (+ve) edge of clock and counth, which will be
high only for one clock cycle if the required count value is counted. For example, if we are counting 12,
then counth will be high as soon as we count 12. The advantage is that we do not have to add extra
comparator circuit with the counter as an extra hardware. Though there is one comparator inside the block
itself, which is used to compare only zero, it takes less hardware as compared to other comparators that
are used to compare any number.
In the generic of the source code, we have to specify that up to which value we want to count and its
required bit width. For example, in the following source code, 4 bits are given to count 15 in the generic
inputs, outputwidth and countupto.
Input ports:
a. rst : It is an active high reset
b. clock : Maximum operating frequency is 758.409 MHz

Output ports:
a. output(3 downto 0) : One count value on each +ve edge of clock
b. counth : High for one clock cycle as soon as the required count number is reached
given in the generic input, countupto
----PROGRAM OF counter----
-------------------------------------------------------------------------------
-- TITLE : 4 BIT COUNTER
-- PROJECT : COUNTER
-------------------------------------------------------------------------------
-- FILE : 4BITCOUNTER.VHD
-- AUTHOR : <ADMINISTRATOR@SOMESH>
-- CREATED : 2006/01/31
-- LAST MODIFIED : 2006/01/31
-------------------------------------------------------------------------------

-- DESCRIPTION :
-- 4 BIT COUNTER WITH ASYNCRONOUS RESET
-------------------------------------------------------------------------------
-- MODIFICATION HISTORY :
-- 2006/01/31 : CREATED
------------------------------------------------------------------------------------
--------------------------------------------------------
LIBRARY IEEE; -- LIBRARY DECLARATION
USE IEEE.NUMERIC_STD.ALL;

279
Appendix A

USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION
ENTITY COUNTER IS
GENERIC (COUNTUPTO : INTEGER := 15; -- NO. UP TO WHICH COUNTER TO COUNT
OUTPUTWIDTH : INTEGER := 4 -- NO. OF BITS REQUIRED FOR IT
);

-- INPUT PORTS
PORT (CLK : IN STD_LOGIC; -- CLOCK INPUT
RST : IN STD_LOGIC; -- RESET INPUT

-- OUTPUT PORTS
OUTPUT : OUT STD_LOGIC_VECTOR((OUTPUTWIDTH -1) DOWNTO 0);
counth : out std_logic -- it will high for one clock cycle
AFTER
-- counting spacified no.of count value
);
END COUNTER;

ARCHITECTURE COUNTER_A OF COUNTER IS -- ARCHITECTURE DECLARATION

-- SIGNAL DECLARATION
SIGNAL COUNT : STD_LOGIC_VECTOR((OUTPUTWIDTH -1) DOWNTO 0);
SIGNAL COUNTPOINT : STD_LOGIC;
BEGIN --
4BIT_COUNTER_A
PROCESS (CLK, RST)
BEGIN -- PROCESS
--
ACTIVITIES TRIGGERED BY ASYNCHRONOUS RESET
IF RST = '1' THEN -- (ACTIVE HIGH)
COUNT <= STD_LOGIC_VECTOR(TO_UNSIGNED((COUNTUPTO -1),OUTPUTWIDTH));
--
ACTIVITIES TRIGGERED BY RISING EDGE OF CLOCK
ELSIF CLK'EVENT AND CLK = '1' THEN
IF CONV_INTEGER(COUNT) = 0 THEN -- COUNTER
COUNTPOINT <= '1';
COUNT <=STD_LOGIC_VECTOR(TO_UNSIGNED((COUNTUPTO - 1),OUTPUTWIDTH));
ELSE
COUNTPOINT <= '0';
COUNT <= COUNT - '1';

END IF;
END IF;
END PROCESS;
OUTPUT <= COUNT;
COUNTH <= COUNTPOINT;
END COUNTER_A;

------------------------------------------------------------------------------------
--------------------------------------------------------

280
 VHDL and Verilog Examples

----Test bench for counter----

------------------------------------------------------------------------------------
--------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY counter_ts_vhd IS
END counter_ts_vhd;

ARCHITECTURE behavior OF counter_ts_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT counter
PORT(clk : IN std_logic;
rst : IN std_logic;
output : OUT std_logic_vector(3 downto 0);
counth : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';

--Outputs
SIGNAL output : std_logic_vector(3 downto 0);
SIGNAL counth : std_logic;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: counter PORT MAP( clk => clk,
rst => rst,
output => output,
counth => counth
);
-- genrating clock
clk <= '1' after 10 ns when clk ='0' else '0' after 10 ns;
-- genrating reset
rst <= '1','0' after 20 ns,'1' after 300 ns,'0' after 400 ns ;

tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
IF NOW >= 40000 NS THEN

REPORT " SIMULATION COMPLETED SUCCESSFULLY";

WAIT; -- WILL WAIT FOREVER
END IF;
END PROCESS;
END;

------------------------------------------------------------------------------------
--------------------------------------------------------

281
Appendix A

SIMULATION RESULT
1. functional simulation

2. post place and routed simulation with delays

Timing summary
----------------------------
Minimum period: 1.319ns (Maximum Frequency: 758.409MHz)
Minimum input arrival time before clock: 2.445ns
Maximum output required time after clock: 3.955ns

Device Utilization Summary

virtex4
Target Device : xc4vfx12
Target Package : sf363
Target Speed : -12
Mapper Version : virtex4
Logic Utilization Used Available Utilization Note(s)

Number of Slice Flip-Flops: 4 10,944 1%

Number of 4 input LUTs: 5 10,944 1%

Logic Distribution:

Number of occupied Slices: 3 5,472 1%

282
 VHDL and Verilog Examples

Number of Slices containing only related logic: 3 3 100%

Number of Slices containing unrelated logic: 0 3 0%

Total Number of 4-Input LUTs: 5 10,944 1%

Number of bonded IOBs: 7 240 2%

Number of BUFG/BUFGCTRLs: 1 32 3%

Number used as BUFGs: 1

Number used as BUFGCTRLs: 0

DECODER
Block Diagram:-

DESCRIPTION:- A 3X8 decoder has four inputs: three selectl (2 downto 0) input lines for selecting the
output according to the inputs given to these input lines and enb to enable the decoder to function
according to the given input. It gives the desired output on eight output lines (output(7 downto 0)) one at
a time that go high according to the input line’s binary equivalent value.
It has one generic selectline input, which by default is defined.
Input ports:
a. selectl(2 downto 0) : Lines to select which output is to be high
b. enb : ENABLE should be high
Output port:
a. output(7 downto 0) : Output will be high according to the binary equivalent of selectl input lines

----PROGRAM OF 3X8 DECODER----

-------------------------------------------------------------------------------
-- Title : Decoder
-- Project : JNTU
-------------------------------------------------------------------------------
-- File : decoder3x8.vhd
-- Author : <ICS@SOMESH>
-- Created : 2006/02/01

283
Appendix A

-- Last modified : 2006/02/01

-------------------------------------------------------------------------------
-- Description : generic decoder, in this we have to specify only the no. of
-- input lines and it will take number output lines and all internal logic
required
-- for that specification automatically.
-------------------------------------------------------------------------------
-- Modification history :
-- 2006/02/01 : created
-------------------------------------------------------------------------------

library ieee;
-- library declaration
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity decoder3x8 is
-- entity declaration

generic (selectline : integer := 3

-- number of input lines
);

-- input ports
port (selectl : in std_logic_vector((selectline -1) downto 0);
-- input lines
enb : in std_logic;
-- enable it is active high

-- output ports
output : out std_logic_vector(((2**selectline)-1)downto 0)
);
end decoder3x8;

-- architecture declaration
architecture decoder3x8_a of decoder3x8 is

-- signal declaration
signal tempout : std_logic_vector(((2**selectline)-1)downto 0);

begin

-- process for decoder3x1_a

process (selectl,enb)
begin
if enb ='1' then
-- active high enable
tempout <= (others => '0');
else
for i in 0 to ((2**selectline)-1) loop
--(i) for loop
if i = (conv_integer(selectl)) then
tempout(conv_integer(selectl)) <= '1';
else
tempout(i) <= '0';
end if;

284
 VHDL and Verilog Examples

end loop;
-- (i) end of loop
end if;
end process;
output <= tempout;
end decoder3x8_a;

----Test bench OF 3x8 DECODER ----

-------------------------------------------------------------------------------
-- Title : Decoder test bench
-- Project : JNTU
-------------------------------------------------------------------------------
-- File : decoder3x8.vhd
-- Author : <ICS@SOMESH>
-- Created : 2006/02/04
-- Last modified : 2006/02/04
-------------------------------------------------------------------------------
-- Description :automated test bench for 3X8 decoder
--
-------------------------------------------------------------------------------
-- Modification history :
-- 2006/02/04 : created
-------------------------------------------------------------------------------

LIBRARY ieee;
-- library declaration
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY decoder_ts_vhd IS
-- entity declaration
END decoder_ts_vhd;

ARCHITECTURE behavior OF decoder_ts_vhd IS --

architecture declaration

-- Component Declaration

-- for the Unit Under Test (UUT)

COMPONENT decoder3x1
PORT(
selectl : IN std_logic_vector(2 downto 0);
enb : IN std_logic;
output : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;

--signal declaration

--Inputs
SIGNAL enb : std_logic := '0';
SIGNAL selectl : std_logic_vector(2 downto 0) := (others=>'1');

--Outputs

285
Appendix A

SIGNAL output : std_logic_vector(7 downto 0);

BEGIN

-- Instantiate the Unit

-- Under Test (UUT)

uut: decoder3x1 PORT MAP(selectl => selectl,
enb => enb,
output => output
);

enb <= '1','0' after 450 ns, '1' after 500 ns;
-- giving inputs to enable

testbench : PROCESS
BEGIN

selectl <= selectl + '1';

-- inputs to input lines
if now >= 4000 ns then
report " simulation completed successfully";
wait;
-- will wait forever
end if;
wait for 6 ns;
END PROCESS;

END;

SIMULATION RESULT:
1. functional simulation

286
 VHDL and Verilog Examples

2. post place and routed simulation with delays

3. showing delay

Timing summary:
----------------------------
Maximum path delay from/to any node: 7.260ns

287
Appendix A

Device Utilization Summary

Logic Utilization Us Availabl Utilization Note(s
ed e )

Number of 4 input LUTs: 8 10,944 1%

Logic Distribution:

Number of occupied Slices: 4 5,472 1%

Number of Slices containing only related logic: 4 4 100%

Number of Slices containing unrelated logic: 0 4 0%

Total Number of 4 input LUTs: 8 10,944 1%

Number of bonded IOBs: 12 240 5%

DEMULTIPLEXERS
Block Diagram:

DESCRIPTION:- A 4 x 16 demultiplexer (DEMUX) has one data input, four select lines, and 16 output
lines. When input values are given to select lines, the decimal equivalent of that input value output signal
is assigned the input data; for example, 0010 means 2; therefore, output(2) is assigned input data.
Input ports:
a. input : Data input port
b. sel(3 downto 0) : Select line to select which output to assign input data Output port:
a. output(15 downto 0) : Output is assigned input data according to the select line input

288
 VHDL and Verilog Examples

----PROGRAM OF DEMUX----
-------------------------------------------------------------------------------
-- Title : demux
-- Project : jntu
-------------------------------------------------------------------------------
-- File : demux.vhd
-- Author : <ICS@SOMESH>
-- Created : 2006/02/01
-- Last modified : 2006/02/01
-- Description :de multiplexer
-------------------------------------------------------------------------------
-- Modification history :
-- 2006/02/01 : created
-------------------------------------------------------------------------------
library ieee; -- library declaration
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity demux is -- entity

declaration

generic (selectlines : integer := 4); -- specify no.

of select lines

port (input : in std_logic; -- input

data
sel : in std_logic_vector((selectlines -1) downto 0); -- select line

output : out std_logic_vector(((2**selectlines) -1) downto 0) -- data

-- output
);
end demux;

architecture demux_a of demux is

begin --
demux_a
process (sel,input)
begin --
process
demux : for i in 0 to ((2**selectlines) -1) loop -- Genrating genric mux

if i = conv_integer(sel) then
output(i) <= input;
else
output(i) <= '0';
end if;
end loop demux;
end process;
end demux_a;
------------------------------------------------------------------------------------
---------------------------------------------

289
Appendix A

----PROGRAM OF DEMUX test bench----

LIBRARY ieee;
--library declaration
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
--entity declaration
ENTITY demux_ts_vhd IS
END demux_ts_vhd;

ARCHITECTURE behavior OF demux_ts_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT demux
PORT(input : IN std_logic;
sel : IN std_logic_vector(3 downto 0);
output : OUT std_logic_vector(15 downto 0) );

END COMPONENT;

--Inputs
SIGNAL input : std_logic := '0';
SIGNAL sel : std_logic_vector(3 downto 0) := (others=>'0');

--Outputs
SIGNAL output: std_logic_vector(15 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: demux
PORT MAP(input => input,
sel => sel,
output => output
);

INPUT <= '1';

tb : PROCESS
BEGIN
SEL <= SEL + 1;
-- Wait 10 ns for global reset to finish
wait for 10 ns;
if NOW >= 400 NS THEN
REPORT " SIMULATION IS SUCCESSFUL";
wait; -- will wait forever
END IF;
END PROCESS;

END;
------------------------------------------------------------------------------------
-----------------------

290
 VHDL and Verilog Examples

SIMULATION RESULT:
a. functional simulation

b. POST PLACE AND ROUTED SIMULATION WITH DELAYS

Timing summary:
----------------------------
Maximum combinational path delay: 5.994ns

291
Appendix A

Device Utilization Summary

virtex4
a. Target Device : xc4vfx12
b. Target Package : sf363
c. Target Speed : -12
d. Mapper Version : virtex4
Logic Utilization Us Availabl Utilizatio Note(s)
ed e n

Number of 4 input LUTs: 32 10,944 1%

Logic Distribution:

Number of occupied Slices: 16 5,472 1%

Number of Slices containing only related logic: 16 16 100%

Number of Slices containing unrelated logic: 0 16 0%

Total Number of 4 input LUTs: 32 10,944 1%

Number of bonded IOBs: 21 240 8%

D FLIP-FLOP
Block Diagram: -

D Flip-Flop with Synchronous Reset

D Flip-Flop with Asynchronous Reset

292
 VHDL and Verilog Examples

DESCRIPTION:- The positive edge triggered D flip-flop samples its input and changes its output q and
q_bar at rising edge of controlling clock. The function of D flip-flop is the ability to hold the last value
stored. In the preceding block diagram, two types of D flip-flops with enable are shown: one with
synchronous reset and another with asynchronous reset. The function of enable is that when it is high,
external input is selected and used; and when it is low, current output of flip-flop is used.
In the following function table, every input is going on with rising edge of a clock:

----PROGRAM OF D Flip-flop----
-------------------------------------------------------------------------------
-- Title : D flip flop
-- Project : dff
-------------------------------------------------------------------------------
-- File : dff.vhd
-- Author : <Administrator@SOMESH>
-- Created : 2006/01/28
-- Last modified : 2006/01/28
-------------------------------------------------------------------------------
-- Description :
-- D Flip flop with syncronous and asynronous reset with enable
-------------------------------------------------------------------------------
-- Modification history :
-- 2006/01/28 : created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity my_dff is

port (i_data,i_data1 : in std_logic;

clk,clk1 : in std_logic; -- clk input
rst,rst1 : in std_logic; -- reset
enb,enb1 : in std_logic;

q : out std_logic; --
output Q
q1 : out std_logic;
q_bar : out std_logic; -- output q_bar
q_bar1: out std_logic
);
end my_dff;

architecture my_dff_a of my_dff is

signal tempq, tempq1 :std_logic;

293
Appendix A

begin -- my_dff_a

sync : process (clk, rst) -- synchronous reset dff

begin -- process sync

-- activities triggered by rising edge of clock
if clk'event and clk = '1' then
-- activities triggered by synchronous reset (active high)
if rst = '1' then
tempq <= '0';
else
if enb ='1' then -- enable input(active high)
tempq <= i_data;
else
tempq <= '0';
end if;
end if;
end if;
end process sync;

q_bar <= not tempq;

q <= tempq;

async : process (clk1, rst1) -- asynchronous reset d flip flop

begin -- process async
-- activities triggered by asynchronous
reset (active high)
if rst1 = '1' then
tempq1 <= '0';
-- activities triggered by rising edge of
clock
elsif clk1'event and clk1 = '1' then
if enb1 = '1' then -- enable input(active high)
tempq1 <= i_data1;
end if;
end if;
end process async;

q_bar1 <= not tempq1;

q1 <= tempq1;
end my_dff_a;
------------------------------------------------------------------------------------
---------------------------------------------
test bench using xilinx test bench wave form
------------------------------------------------------------------------------------
---------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY dff_ts IS
END dff_ts;

ARCHITECTURE testbench_arch OF dff_ts IS

294
 VHDL and Verilog Examples

COMPONENT my_dff
PORT (
i_data : In std_logic;
i_data1 : In std_logic;
clk : In std_logic;
clk1 : In std_logic;
rst : In std_logic;
rst1 : In std_logic;
enb : In std_logic;
enb1 : In std_logic;
q : Out std_logic;
q1 : Out std_logic;
q_bar : Out std_logic;
q_bar1 : Out std_logic
);
END COMPONENT;

SIGNAL i_data : std_logic := '0';

SIGNAL i_data1 : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL clk1 : std_logic := '0';
SIGNAL rst : std_logic := '1';
SIGNAL rst1 : std_logic := '1';
SIGNAL enb : std_logic := '0';
SIGNAL enb1 : std_logic := '0';
SIGNAL q : std_logic := '0';
SIGNAL q1 : std_logic := '0';
SIGNAL q_bar : std_logic := '0';
SIGNAL q_bar1 : std_logic := '0';

SHARED VARIABLE TX_ERROR : INTEGER := 0;

SHARED VARIABLE TX_OUT : LINE;

constant PERIOD_clk : time := 100 ns;

constant DUTY_CYCLE_clk : real := 0.5;
constant OFFSET_clk : time := 0 ns;
constant PERIOD_clk1 : time := 200 ns;
constant DUTY_CYCLE_clk1 : real := 0.5;
constant OFFSET_clk1 : time := 0 ns;

BEGIN
UUT : my_dff
PORT MAP (
i_data => i_data,
i_data1 => i_data1,
clk => clk,
clk1 => clk1,
rst => rst,
rst1 => rst1,
enb => enb,
enb1 => enb1,
q => q,
q1 => q1,
q_bar => q_bar,
q_bar1 => q_bar1

295
Appendix A

);

PROCESS -- clock process for clk

BEGIN
WAIT for OFFSET_clk;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD_clk - (PERIOD_clk * DUTY_CYCLE_clk));
clk <= '1';
WAIT FOR (PERIOD_clk * DUTY_CYCLE_clk);
END LOOP CLOCK_LOOP;
END PROCESS;

PROCESS -- clock process for clk1

BEGIN
WAIT for OFFSET_clk1;
CLOCK_LOOP : LOOP
clk1 <= '0';
WAIT FOR (PERIOD_clk1 - (PERIOD_clk1 * DUTY_CYCLE_clk1));
clk1 <= '1';
WAIT FOR (PERIOD_clk1 * DUTY_CYCLE_clk1);
END LOOP CLOCK_LOOP;
END PROCESS;

PROCESS -- Process for clk

PROCEDURE CHECK_q(
next_q : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (q /= next_q) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns q="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, q);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_q);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_q_bar(
next_q_bar : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (q_bar /= next_q_bar) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));

296
 VHDL and Verilog Examples

STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns q_bar="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, q_bar);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_q_bar);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- ------------- Current Time: 46ns
WAIT FOR 46 ns;
rst <= '0';
-- -------------------------------------
-- ------------- Current Time: 346ns
WAIT FOR 300 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 746ns
WAIT FOR 400 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 846ns
WAIT FOR 100 ns;
enb <= '1';
-- -------------------------------------
-- ------------- Current Time: 1146ns
WAIT FOR 300 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 1746ns
WAIT FOR 600 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 1846ns
WAIT FOR 100 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 1946ns
WAIT FOR 100 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 2046ns
WAIT FOR 100 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 2246ns
WAIT FOR 200 ns;
i_data <= '0';
enb <= '0';
-- -------------------------------------
-- ------------- Current Time: 2546ns

297
Appendix A

WAIT FOR 300 ns;

i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 2846ns
WAIT FOR 300 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 3346ns
WAIT FOR 500 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 3646ns
WAIT FOR 300 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 3946ns
WAIT FOR 300 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 4046ns
WAIT FOR 100 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 4246ns
WAIT FOR 200 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 4446ns
WAIT FOR 200 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 4646ns
WAIT FOR 200 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 4846ns
WAIT FOR 200 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 5046ns
WAIT FOR 200 ns;
enb <= '1';
-- -------------------------------------
-- ------------- Current Time: 5146ns
WAIT FOR 100 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 5346ns
WAIT FOR 200 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 5646ns
WAIT FOR 300 ns;
i_data <= '1';
-- -------------------------------------

298
 VHDL and Verilog Examples

-- ------------- Current Time: 5946ns

WAIT FOR 300 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 6246ns
WAIT FOR 300 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 6746ns
WAIT FOR 500 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 7046ns
WAIT FOR 300 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 7246ns
WAIT FOR 200 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 7546ns
WAIT FOR 300 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 7746ns
WAIT FOR 200 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 7846ns
WAIT FOR 100 ns;
enb <= '0';
-- -------------------------------------
-- ------------- Current Time: 8246ns
WAIT FOR 400 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 8346ns
WAIT FOR 100 ns;
enb <= '1';
-- -------------------------------------
-- ------------- Current Time: 8446ns
WAIT FOR 100 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 8846ns
WAIT FOR 400 ns;
i_data <= '1';
-- -------------------------------------
-- ------------- Current Time: 9046ns
WAIT FOR 200 ns;
i_data <= '0';
-- -------------------------------------
-- ------------- Current Time: 9346ns
WAIT FOR 300 ns;
i_data <= '1';

299
Appendix A

-- -------------------------------------
-- ------------- Current Time: 9646ns
WAIT FOR 300 ns;
i_data <= '0';
-- -------------------------------------
WAIT FOR 554 ns;

IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT, string'("No errors or warnings"));
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems
detected."
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT,
string'(" errors found in simulation"));
ASSERT (FALSE) REPORT "Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;

PROCESS -- Process for clk1

PROCEDURE CHECK_q1(
next_q1 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (q1 /= next_q1) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns q1="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, q1);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_q1);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_q_bar1(
next_q_bar1 : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (q_bar1 /= next_q_bar1) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns q_bar1="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, q_bar1);

300
 VHDL and Verilog Examples

STD.TEXTIO.write(TX_LOC, string'(", Expected = "));

IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_q_bar1);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- ------------- Current Time: 85ns
WAIT FOR 85 ns;
rst1 <= '0';
-- -------------------------------------
-- ------------- Current Time: 485ns
WAIT FOR 400 ns;
enb1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 885ns
WAIT FOR 400 ns;
i_data1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 1885ns
WAIT FOR 1000 ns;
i_data1 <= '0';
enb1 <= '0';
-- -------------------------------------
-- ------------- Current Time: 2685ns
WAIT FOR 800 ns;
i_data1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 3085ns
WAIT FOR 400 ns;
i_data1 <= '0';
enb1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 3285ns
WAIT FOR 200 ns;
i_data1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 3485ns
WAIT FOR 200 ns;
i_data1 <= '0';
-- -------------------------------------
-- ------------- Current Time: 4285ns
WAIT FOR 800 ns;
i_data1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 4485ns
WAIT FOR 200 ns;
enb1 <= '0';
-- -------------------------------------
-- ------------- Current Time: 4685ns
WAIT FOR 200 ns;
i_data1 <= '0';

301
Appendix A

-- -------------------------------------
-- ------------- Current Time: 5285ns
WAIT FOR 600 ns;
i_data1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 5485ns
WAIT FOR 200 ns;
enb1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 5885ns
WAIT FOR 400 ns;
i_data1 <= '0';
-- -------------------------------------
-- ------------- Current Time: 6285ns
WAIT FOR 400 ns;
i_data1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 6485ns
WAIT FOR 200 ns;
i_data1 <= '0';
-- -------------------------------------
-- ------------- Current Time: 6685ns
WAIT FOR 200 ns;
enb1 <= '0';
-- -------------------------------------
-- ------------- Current Time: 6885ns
WAIT FOR 200 ns;
enb1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 7085ns
WAIT FOR 200 ns;
i_data1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 7285ns
WAIT FOR 200 ns;
i_data1 <= '0';
-- -------------------------------------
-- ------------- Current Time: 7685ns
WAIT FOR 400 ns;
i_data1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 7885ns
WAIT FOR 200 ns;
i_data1 <= '0';
-- -------------------------------------
-- ------------- Current Time: 8685ns
WAIT FOR 800 ns;
i_data1 <= '1';
-- -------------------------------------
-- ------------- Current Time: 9085ns
WAIT FOR 400 ns;
i_data1 <= '0';
-- -------------------------------------
-- ------------- Current Time: 9485ns
WAIT FOR 400 ns;

302
 VHDL and Verilog Examples

i_data1 <= '1';

-- -------------------------------------
WAIT FOR 715 ns;

IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT, string'("No errors or warnings"));
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems
detected."
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT,
string'(" errors found in simulation"));
ASSERT (FALSE) REPORT "Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;

END testbench_arch;

SIMULATION RESULT:
a. functional simulation

b. post place and routed simulation with delays

303
Appendix A

DPRAM
Block Diagram:-

DESCRIPTION:- In DPRAM, the generic inputs are declared such that it becomes 4-bit wide,16 depth
dual port RAM . It has two ports, ainout and binout, for both read and write operations through which we
can read and write simultaneously. Memory address is given by add_a for port ainout and add_b for port
binout. When both the address inputs target same memory location, following conditions for priority
arises, which are taken care in the RAM:
 When both the ports are trying to write simultaneously on the same memory location, priority is
given to the port a. This implies that data send by port b at this extent is ignored.
 When port a is writing and port b is reading, data read by port b is the new updated data. This
implies that the priority is given to writing and after this operation, reading will take place.
 When port b is writing and port a is reading, data read by port a is the new updated data. This
implies that the priority is given to reading and after this operation, writing will take place.
 When both ports are reading simultaneously on the same location, there will be no priority, which
implies that they can read at the same time.

304
 VHDL and Verilog Examples

Input ports:
a. add_a : Address input for port a
b. add_b : Address input for port b
c. wr_a : Read-write enable for port a; if it is active high, then writing will take place;
else, if it is active low, then reading will take place
d. wr_b : Read-write enable for port a; If it is active high, then writing will take place;
else, if it is active low, then reading will take place
e. cs : Chip select active high
f. rst : Reset active high
g. clk : Clock

Inout ports:
a. ainout : Data input output port for port a
b. binout : Data input output port for port a

----PROGRAM OF dpram----
-------------------------------------------------------------------------------
-- Title : dpram
-- Project : dual port ram
-------------------------------------------------------------------------------
-- File : dpram.vhd
-- Author : <ICS@somesh>
-- Created : 2006/01/21
-- Last modified : 2006/01/21
-------------------------------------------------------------------------------
-- Description :
-- it has two ports through which we can simultaneously read and write
-- priority is given to "port a" when simultaneously reading and writing
-- and when one is reading and other is writing then first write will take
-- places after that reading is done on updated data
-------------------------------------------------------------------------------
-- Modification history
-- 2006/01/21 : created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity dpram is

generic (width
: integer := 4;
addloc : integer := 4
);
port(add_a,add_b: in std_logic_vector((addloc-1) downto 0); --address input
wr_a,wr_b : in std_logic; -- write enable
cs : in std_logic; --
chip select
rst : in std_logic; --
asyncronous reset

305
Appendix A

clk : in std_logic; -- clock

input

-- data input output ports

ainout : inout std_logic_vector((width -1) downto 0);
binout : inout std_logic_vector((width -1) downto 0)
);
end dpram;
architecture dpram_a of dpram is

type dpramtype is array (0 to ((2**addloc) -1))of std_logic_vector((width-1)

downto 0);
signal dpram : dpramtype;
signal wr_a_b : std_logic_vector(1 downto 0);
signal intri_a,intri_b,outtri_a,outtri_b : std_logic_vector((width -1) downto
0); -- tristate

begin
wr_a_b <= wr_a & wr_b;

ainout <= outtri_a when wr_a ='0' and cs = '1' else (others => 'Z');
binout <= outtri_b when wr_b ='0' and cs = '1' else (others => 'Z');
intri_a <= ainout when wr_a ='1' and cs = '1' else (others =>
'Z');
intri_b <= binout when wr_b ='1' and cs = '1' else (others =>
'Z');

process(clk,rst)

begin
if rst='1' then -- asyncronous reset (active high)
dpram <=(others => (others => '0'));
outtri_a <= (others => '0');
outtri_b <= (others => '0');
elsif cs = '1' then
if clk'event and clk ='1' then
if add_a = add_b then
case wr_a_b is
when "11" =>
dpram(conv_integer(add_a))<= intri_a;
when "10" =>
outtri_b <= intri_a;
dpram(conv_integer(add_a))<= intri_a;

when "01" =>

outtri_a <= intri_b;
dpram(conv_integer(add_b))<= intri_b;

when others =>

outtri_a <= dpram(conv_integer(add_a));
outtri_b <= dpram(conv_integer(add_b));
end case;
else
case wr_a_b is
when "11" =>
dpram(conv_integer(add_a))<= intri_a;

306
 VHDL and Verilog Examples

dpram(conv_integer(add_b))<= intri_b;

when "10" =>

outtri_b <= dpram(conv_integer(add_b));
dpram(conv_integer(add_a))<= intri_a;

when "01" =>

outtri_a <= dpram(conv_integer(add_a));
dpram(conv_integer(add_b))<= intri_b;

when others =>

outtri_a <= dpram(conv_integer(add_a));
outtri_b <= dpram(conv_integer(add_b));
end case;
end if;
end if;
end if;
end process;
end dpram_a;
------------------------------------------------------------------------------------
-----------------------------------------------------------
testing is done using forceing inputs in modelsim
------------------------------------------------------------------------------------
-----------------------------------------------------------
steps for testing are:-
vsim -lib work -t 1ps dpram_ts_vhd
# .structure
# .signals
add wave sim:/dpram_ts_vhd/*
restart
force -freeze sim:/dpram_ts_vhd/wr_a 1 0

force -freeze sim:/dpram_ts_vhd/wr_b 1 0

force -freeze sim:/dpram_ts_vhd/cs 1 0

force -freeze sim:/dpram_ts_vhd/rst 1 0 -cancel 10

force -freeze sim:/dpram_ts_vhd/add_a 0000 0

force -freeze sim:/dpram_ts_vhd/add_b 1111 0

force -freeze sim:/dpram_ts_vhd/ainout 1010 0

force -freeze sim:/dpram_ts_vhd/binout 0101 0

force -freeze sim:/dpram_ts_vhd/rst 0 10

force -freeze sim:/dpram_ts_vhd/clk 1 0, 0 {50 } -r 100

run

force -freeze sim:/dpram_ts_vhd/add_a 0001 0

force -freeze sim:/dpram_ts_vhd/add_b 1110 0

307
Appendix A

run
force -freeze sim:/dpram_ts_vhd/add_a 0010 0

force -freeze sim:/dpram_ts_vhd/add_b 1101 0

run
force -freeze sim:/dpram_ts_vhd/add_a 1101 0

force -freeze sim:/dpram_ts_vhd/add_b 1000 0

run

force -freeze sim:/dpram_ts_vhd/add_a 1001 0

force -freeze sim:/dpram_ts_vhd/add_b 0011 0

run

force -freeze sim:/dpram_ts_vhd/wr_a 0 0

force -freeze sim:/dpram_ts_vhd/add_a 0010 0

noforce sim:/dpram_ts_vhd/ainout

run

run

force -freeze sim:/dpram_ts_vhd/add_a 1110 0

run

force -freeze sim:/dpram_ts_vhd/add_a 1111 0

run

force -freeze sim:/dpram_ts_vhd/wr_b 0 0

force -freeze sim:/dpram_ts_vhd/add_b 0010 0

noforce sim:/dpram_ts_vhd/binout

run

force -freeze sim:/dpram_ts_vhd/add_b 1011 0

force -freeze sim:/dpram_ts_vhd/add_a 1100 0

force -freeze sim:/dpram_ts_vhd/add_b 1011 0

run

run

308
 VHDL and Verilog Examples

force -freeze sim:/dpram_ts_vhd/wr_a 1 0

force -freeze sim:/dpram_ts_vhd/add_a 0100 0

force -freeze sim:/dpram_ts_vhd/add_b 0100 0

force -freeze sim:/dpram_ts_vhd/ainout 1110 0

run

force -freeze sim:/dpram_ts_vhd/add_a 1100 0

force -freeze sim:/dpram_ts_vhd/add_b 1100 0

run

force -freeze sim:/dpram_ts_vhd/add_a 1100 0

run

force -freeze sim:/dpram_ts_vhd/add_b 0010 0

run

SIMULATION RESULT:
a. functional simulation

Timing Summary:
---------------
a. Minimum period : 2.564ns (Maximum Frequency: 390.038MHz)
b. Minimum input arrival time before clock : 4.882ns
c. Maximum output required time after clock : 3.935ns
d. Maximum combinational path delay : 5.790ns

309
Appendix A

Device Utilization Summary

a. Target Device : xc4vfx12
b. Target Package : sf363
c. Target Speed : -12
d. Mapper Version : virtex4
Logic Utilization Used Available Utilization Note(s)
Number of Slice Flip-Flops: 72 10,944 1%
Number of 4 input LUTs: 326 10,944 2%
Logic Distribution:
Number of occupied Slices: 164 5,472 2%
Number of Slices containing only related logic: 164 164 100%
Number of Slices containing unrelated logic: 0 164 0%
Total Number of 4 input LUTs: 326 10,944 2%
Number of bonded IOBs: 21 240 8%
Number of BUFG/BUFGCTRLs: 1 32 3%
Number used as BUFGs: 1
Number used as BUFGCTRLs: 0

QUEUE
Block Diagram:-

310
 VHDL and Verilog Examples

DESCRIPTION: Queue using DPRAM as a component has generic inputs such that it becomes 4-bit
wide,16 depth DPRAM with port a is write only and port b is read only. The address for memory location
for port a is generated by the write counter, as it is write only port. Similarly, address for port b is
generated by the read counter.
The working of queue is such that data, which enters first, will go out first (FIFO operation). It will give
five output signals: one will give output data and others will behave as indicators when the queue is full,
going to full, empty, or going to empty. The corresponding indicator will be active high when any the
condition for that specified signal becomes true.

Input ports:
a. clk : Clock
b. Rst : Active high reset
c. cs : Chip select
d. wr : Write enable for port a
e. rd : Read enable for port b when rd is zero
f. Inputdata : Data input to the FIFO

Out ports:
a. Almost_full : Active high signal; high only when one memory location is left empty
during the write process
b. Almost_empty : Active high signal; high only when one memory location is left to be read
c. Full : Active high signal; high when all the memory locations are written
d. Empty : Active high signal; high when all the memory locations are empty
e. Output(3 downto 0) : Data output when rd is zero from memory location address by read counter

----PROGRAM OF QUEUE USING DPRAM AS COMPONENT----

-------------------------------------------------------------------------------
-- TITLE : QUEUE
-- PROJECT : JNTU
-------------------------------------------------------------------------------
-- FILE : QUEUE.VHD
-- AUTHOR : <ICS@SOMESH>
-- CREATED : 2006/02/12
-- LAST MODIFIED : 2006/02/12
-------------------------------------------------------------------------------
-- DESCRIPTION :
-- QUEUE USING DUAL PORT MEMORY
-------------------------------------------------------------------------------
-- MODIFICATION HISTORY :
-- 2006/02/12 : CREATED
-------------------------------------------------------------------------------

LIBRARY IEEE;
--LIBRARY DECLARATION
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY MY_QUEUE IS

311
Appendix A

-- GENERIC DECLARATION
GENERIC (WIDTH : INTEGER := 4;
ADDLOC : INTEGER := 4
);
-- INPUT PORTS
PORT (CLK : IN STD_LOGIC; -- CLOCK
RST : IN STD_LOGIC; -- RESET
CS : IN STD_LOGIC; -- CHIP SELECT
WR : IN STD_LOGIC; -- WRITE ENABLE
RD : IN STD_LOGIC; -- READ ENABLE
INPUTDATA : IN STD_LOGIC_VECTOR((WIDTH-1) DOWNTO 0); -- INPUT DATA

-- OUTPUT PORTS
ALMOST_FULL : OUT STD_LOGIC;
ALMOST_EMPTY: OUT STD_LOGIC;
MPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OUTPUT : OUT STD_LOGIC_VECTOR((WIDTH -1)DOWNTO 0)
);

END MY_QUEUE;

ARCHITECTURE MY_QUEUE_A OF MY_QUEUE IS

-- COMPONENT INSTANTITING(DUAL PORT RAM)

COMPONENT DPRAM
-- GENERIC DECLARATION
GENERIC (WIDTH : INTEGER := 4;
ADDLOC : INTEGER := 4);

-- INPUT PORTS
PORT(ADD_A : IN STD_LOGIC_VECTOR((ADDLOC-1) DOWNTO 0); -- ADDRESS INPUT
ADD_B : IN STD_LOGIC_VECTOR((ADDLOC-1) DOWNTO 0); -- ADDRESS INPUT
WR_A,WR_B : IN STD_LOGIC; -- WRITE ENABLE
CS : IN STD_LOGIC; -- CHIP SELECT
RST : IN STD_LOGIC; -- ASYNCRONOUS RESET
CLK : IN STD_LOGIC; -- CLOCK INPUT
AINOUT : IN STD_LOGIC_VECTOR((WIDTH -1) DOWNTO 0);-- DATA INPUT
--PORTS

-- DATA OUTPUT PORTS

BINOUT : OUT STD_LOGIC_VECTOR((WIDTH -1) DOWNTO 0)
);

END COMPONENT;

-- SUBTYPE DECLARATION
SUBTYPE F_E_INTEGER IS INTEGER RANGE 0 TO (2**ADDLOC);

-- SIGNAL DECLARATION
SIGNAL ADD_DECODER1,ADD_DECODER2 : STD_LOGIC_VECTOR((ADDLOC - 1) DOWNTO 0);-- TO
-- DECODE THE NEW ADDRESS
--FOR NEXT DATA AFTER WRITE
--OR READ CYCLE

312
 VHDL and Verilog Examples

SIGNAL OUTPUTDATA :STD_LOGIC_VECTOR((WIDTH -1)DOWNTO 0);-- TEMP OUTPUT SIGNAL

SIGNAL F_E_COUNTER : F_E_INTEGER; -- COUNTER FOR FULL ANS EMPTY
SIGNAL FULL_TEMP : STD_LOGIC; -- TEMP FULL
SIGNAL EMPTY_TEMP : STD_LOGIC; -- TEMP EMPTY
SIGNAL WR_RD : STD_LOGIC_VECTOR(1 DOWNTO 0); -- SIGNAL FOR READ AND WRITE
SIGNAL RD_DPRAM : STD_LOGIC; -- READ ENABLE FOR DPRAM
SIGNAL WR_DPRAM : STD_LOGIC; -- WRITE ENABLE FOR DPRAM

BEGIN -- MY_QUEUE_A

----- PORT MAPPING OF DPRAM -----

DUALPRAM:DPRAM GENERIC MAP (WIDTH => WIDTH,
ADDLOC => ADDLOC)]
PORT MAP (ADD_A => ADD_DECODER1,
ADD_B => ADD_DECODER2,
WR_A => WR_DPRAM,
WR_B => RD_DPRAM,
CS => CS,
RST => RST,
CLK => CLK,
AINOUT => INPUTDATA,
BINOUT => OUTPUTDATA
);

-- COMBINING READ AND WRITE

WR_RD <= WR & RD;

WR_DPRAM <= '1' WHEN (WR = '1' AND FULL_TEMP = '0') ELSE '0'; -- WRITE

RD_DPRAM <= '0' WHEN (RD = '0' AND EMPTY_TEMP = '0') ELSE '1'; -- READ

--------------------------------FIFO FULL----------------------------------
FULL_TEMP <= '1' WHEN F_E_COUNTER = ((2**ADDLOC) -1) AND WR = '1' ELSE '0';
ALMOST_FULL<= '1' WHEN F_E_COUNTER = ((2**ADDLOC) -2) AND WR = '1' ELSE '0';
--------------------------------FIFO EMPTY---------------------------------
EMPTY_TEMP <= '1' WHEN F_E_COUNTER = 0 AND RD = '0' ELSE '0';
ALMOST_EMPTY <= '1' WHEN F_E_COUNTER = 1 AND RD = '0' ELSE '0';
---------------------------------------------------------------------------
FULL <= FULL_TEMP;
EMPTY <= EMPTY_TEMP;

PROCESS (CLK, RST)

BEGIN -- PROCESS CLK

-- ACTIVITIES TRIGGERED BY ASYNCHRONOUS RESET (ACTIVE
HIGH)
IF RST = '1' THEN
ADD_DECODER1 <= (OTHERS => '1');
ADD_DECODER2 <= (OTHERS => '1');
F_E_COUNTER <= 0;
-- ACTIVITIES TRIGGERED BY RISING EDGE OF CLOCK
ELSIF CLK'EVENT AND CLK = '1' THEN
CASE WR_RD IS
WHEN "11" =>
IF FULL_TEMP = '0' THEN
ADD_DECODER1 <= ADD_DECODER1 + '1';

313
Appendix A

F_E_COUNTER <= F_E_COUNTER + 1;

ELSE
ADD_DECODER1 <= ADD_DECODER1;
F_E_COUNTER <= F_E_COUNTER;
END IF;
WHEN "00" =>
IF EMPTY_TEMP ='0' THEN
ADD_DECODER2 <= ADD_DECODER2 + '1';
F_E_COUNTER <= F_E_COUNTER - 1;
ELSE
ADD_DECODER2 <= ADD_DECODER2;
F_E_COUNTER <= F_E_COUNTER;
END IF;
WHEN "10" =>
ADD_DECODER1 <= ADD_DECODER1 + '1';
ADD_DECODER2 <= ADD_DECODER2 + '1';
WHEN OTHERS =>

END CASE;

END IF;
END PROCESS ;
OUTPUT <= OUTPUTDATA;
END MY_QUEUE_A;
--------------------------------------------------------------------------------
TEST BENCH

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY queue_ts IS
END queue_ts;

ARCHITECTURE testbench_arch OF queue_ts IS

FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT my_queue
PORT (
clk : In std_logic;
rst : In std_logic;
cs : In std_logic;
wr : In std_logic;
rd : In std_logic;
inputdata : In std_logic_vector (3 DownTo 0);
almost_full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic;
full : Out std_logic;
output : Out std_logic_vector (3 DownTo 0)
);
END COMPONENT;

314
 VHDL and Verilog Examples

SIGNAL clk : std_logic := '0';

SIGNAL rst : std_logic := '0';
SIGNAL cs : std_logic := '0';
SIGNAL wr : std_logic := '0';
SIGNAL rd : std_logic := '0';
SIGNAL inputdata : std_logic_vector (3 DownTo 0) := "0000";
SIGNAL almost_full : std_logic := '0';
SIGNAL almost_empty : std_logic := '0';
SIGNAL empty : std_logic := '0';
SIGNAL full : std_logic := '0';
SIGNAL output : std_logic_vector (3 DownTo 0) := "0000";

SHARED VARIABLE TX_ERROR : INTEGER := 0;

SHARED VARIABLE TX_OUT : LINE;

constant PERIOD : time := 20 ns;

constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 0 ns;

BEGIN
UUT : my_queue
PORT MAP (
clk => clk,
rst => rst,
cs => cs,
wr => wr,
rd => rd,
inputdata => inputdata,
almost_full => almost_full,
almost_empty => almost_empty,
empty => empty,
full => full,
output => output
);

PROCESS -- clock process for clk

BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;

PROCESS
PROCEDURE CHECK_almost_empty(
next_almost_empty : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN

315
Appendix A

IF (almost_empty /= next_almost_empty) THEN

STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns almost_empty="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, almost_empty);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_almost_empty);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_almost_full(
next_almost_full : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (almost_full /= next_almost_full) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns almost_full="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, almost_full);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_almost_full);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_empty(
next_empty : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (empty /= next_empty) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns empty="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, empty);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_empty);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);

316
 VHDL and Verilog Examples

ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;

TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_full(
next_full : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (full /= next_full) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns full="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, full);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_full);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_output(
next_output : std_logic_vector (3 DownTo 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (output /= next_output) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns output="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, output);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_output);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- ------------- Current Time: 6ns
WAIT FOR 6 ns;
rst <= '1';
cs <= '1';
wr <= '1';
-- -------------------------------------

317
Appendix A

-- ------------- Current Time: 86ns

WAIT FOR 80 ns;
rst <= '0';
-- -------------------------------------
-- ------------- Current Time: 166ns
WAIT FOR 80 ns;
rd <= '1';
inputdata <= "1000";
-- -------------------------------------
-- ------------- Current Time: 226ns
WAIT FOR 60 ns;
inputdata <= "1001";
-- -------------------------------------
-- ------------- Current Time: 406ns
WAIT FOR 180 ns;
rd <= '0';
-- -------------------------------------
-- ------------- Current Time: 446ns
WAIT FOR 40 ns;
inputdata <= "1101";
-- -------------------------------------
-- ------------- Current Time: 606ns
WAIT FOR 160 ns;
inputdata <= "0101";
-- -------------------------------------
-- ------------- Current Time: 626ns
WAIT FOR 20 ns;
inputdata <= "0111";
-- -------------------------------------
-- ------------- Current Time: 886ns
WAIT FOR 260 ns;
rd <= '1';
-- -------------------------------------
-- ------------- Current Time: 986ns
WAIT FOR 100 ns;
inputdata <= "0101";
-- -------------------------------------
-- ------------- Current Time: 1086ns
WAIT FOR 100 ns;
inputdata <= "1101";
-- -------------------------------------
-- ------------- Current Time: 1626ns
WAIT FOR 540 ns;
inputdata <= "0111";
-- -------------------------------------
-- ------------- Current Time: 1686ns
WAIT FOR 60 ns;
inputdata <= "0110";
-- -------------------------------------
-- ------------- Current Time: 1766ns
WAIT FOR 80 ns;
wr <= '0';
rd <= '0';
-- -------------------------------------
-- ------------- Current Time: 1966ns

318
 VHDL and Verilog Examples

WAIT FOR 200 ns;

inputdata <= "1110";
-- -------------------------------------
-- ------------- Current Time: 2546ns
WAIT FOR 580 ns;
wr <= '1';
-- -------------------------------------
-- ------------- Current Time: 2846ns
WAIT FOR 300 ns;
inputdata <= "0110";
-- -------------------------------------
-- ------------- Current Time: 3166ns
WAIT FOR 320 ns;
inputdata <= "0100";
-- -------------------------------------
-- ------------- Current Time: 3206ns
WAIT FOR 40 ns;
inputdata <= "0101";
-- -------------------------------------
-- ------------- Current Time: 3346ns
WAIT FOR 140 ns;
inputdata <= "1101";
-- -------------------------------------
-- ------------- Current Time: 3366ns
WAIT FOR 20 ns;
rd <= '1';
-- -------------------------------------
-- ------------- Current Time: 3846ns
WAIT FOR 480 ns;
wr <= '0';
inputdata <= "1111";
-- -------------------------------------
-- ------------- Current Time: 4266ns
WAIT FOR 420 ns;
inputdata <= "1110";
-- -------------------------------------
-- ------------- Current Time: 4546ns
WAIT FOR 280 ns;
inputdata <= "1100";
-- -------------------------------------
-- ------------- Current Time: 4686ns
WAIT FOR 140 ns;
inputdata <= "1000";
-- -------------------------------------
-- ------------- Current Time: 4866ns
WAIT FOR 180 ns;
inputdata <= "0000";
-- -------------------------------------
-- ------------- Current Time: 4986ns
WAIT FOR 120 ns;
rd <= '0';
-- -------------------------------------
-- ------------- Current Time: 5286ns
WAIT FOR 300 ns;
inputdata <= "0001";

319
Appendix A

-- -------------------------------------
-- ------------- Current Time: 5466ns
WAIT FOR 180 ns;
inputdata <= "1001";
-- -------------------------------------
-- ------------- Current Time: 5586ns
WAIT FOR 120 ns;
wr <= '1';
-- -------------------------------------
-- ------------- Current Time: 5866ns
WAIT FOR 280 ns;
inputdata <= "1101";
-- -------------------------------------
-- ------------- Current Time: 6166ns
WAIT FOR 300 ns;
inputdata <= "1111";
-- -------------------------------------
-- ------------- Current Time: 6286ns
WAIT FOR 120 ns;
inputdata <= "1110";
-- -------------------------------------
-- ------------- Current Time: 6406ns
WAIT FOR 120 ns;
rd <= '1';
-- -------------------------------------
-- ------------- Current Time: 6706ns
WAIT FOR 300 ns;
inputdata <= "0110";
-- -------------------------------------
-- ------------- Current Time: 6846ns
WAIT FOR 140 ns;
inputdata <= "0010";
-- -------------------------------------
-- ------------- Current Time: 7106ns
WAIT FOR 260 ns;
wr <= '0';
-- -------------------------------------
-- ------------- Current Time: 7446ns
WAIT FOR 340 ns;
inputdata <= "0000";
-- -------------------------------------
-- ------------- Current Time: 7566ns
WAIT FOR 120 ns;
inputdata <= "0100";
-- -------------------------------------
-- ------------- Current Time: 7586ns
WAIT FOR 20 ns;
rd <= '0';
-- -------------------------------------
-- ------------- Current Time: 7626ns
WAIT FOR 40 ns;
wr <= '1';
-- -------------------------------------
-- ------------- Current Time: 7726ns
WAIT FOR 100 ns;

320
 VHDL and Verilog Examples

inputdata <= "1100";

-- -------------------------------------
-- ------------- Current Time: 7826ns
WAIT FOR 100 ns;
wr <= '0';
-- -------------------------------------
-- ------------- Current Time: 7906ns
WAIT FOR 80 ns;
inputdata <= "1101";
-- -------------------------------------
-- ------------- Current Time: 8046ns
WAIT FOR 140 ns;
inputdata <= "1001";
-- -------------------------------------
-- ------------- Current Time: 8166ns
WAIT FOR 120 ns;
inputdata <= "1001";
-- -------------------------------------
-- ------------- Current Time: 8186ns
WAIT FOR 20 ns;
rd <= '1';
-- -------------------------------------
-- ------------- Current Time: 8346ns
WAIT FOR 160 ns;
inputdata <= "1011";
-- -------------------------------------
-- ------------- Current Time: 8426ns
WAIT FOR 80 ns;
inputdata <= "0011";
-- -------------------------------------
-- ------------- Current Time: 8586ns
WAIT FOR 160 ns;
rd <= '0';
-- -------------------------------------
-- ------------- Current Time: 8806ns
WAIT FOR 220 ns;
inputdata <= "0001";
-- -------------------------------------
-- ------------- Current Time: 8946ns
WAIT FOR 140 ns;
inputdata <= "1001";
-- -------------------------------------
-- ------------- Current Time: 8966ns
WAIT FOR 20 ns;
inputdata <= "1000";
-- -------------------------------------
-- ------------- Current Time: 9326ns
WAIT FOR 360 ns;
inputdata <= "1100";
-- -------------------------------------
WAIT FOR 694 ns;

IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT, string'("No errors or warnings"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);

321
Appendix A

ASSERT (FALSE) REPORT

"Simulation successful (not a failure). No problems detected."
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT,
string'(" errors found in simulation"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT "Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;

END testbench_arch;

SIMULATION RESULT :
a. functional simulation

b. Place and routed simulation

Verilog Examples
1. A 4-Bit Ripple Adder
// module top declaration

module rippleadder4(sum,cout,a,b,cin);

322
 VHDL and Verilog Examples

// input and output declarations

input [3:0]a,b;
input cin;
output [3:0]sum;
output cout;

// internal wire delcaration

wire temp1;
wire temp2;
wire temp3;

// module add instantiation

assign sum[0] = (a[0] ^ b[0] ^ cin);

assign temp1 = ((a[0] & b[0]) | (b[0] & cin) | (a[0] & cin));
assign sum[1] = (a[1] ^ b[1] ^ temp1);
assign temp2 = ((a[1] & b[1]) | (b[1] & temp1) | (a[1] & temp1));
assign sum[2] = (a[2] ^ b[2] ^ temp2);
assign temp3 = ((a[2] & b[2]) | (b[2] & temp2) | (a[2] & temp2));
assign sum[3] = (a[3] ^ b[3] ^ temp3);
assign cout = ((a[3] & b[3]) | (b[3] & temp3) | (a[3] & temp3));
endmodule

####TEST BENCH for 4-Bit Ripple Adder

// stimulus
`include "rippleadder4.v"
module stimulus;

reg [3:0] a,b;

wire cout;
wire [3:0]sum;
reg cin;

rippleadder4 radder1(sum,cout,a,b,cin);

initial
$monitor($time, "sum= %d cout = %b a = %b b = %b cin = %b", sum,cout, a,b, cin);

initial

begin

#1 a=4'd4; b = 4'd3; cin = 1'b0;

#8 a=4'd9; b=4'd01; cin=1'b0;

#10 a=1'b1;b=1'b0;cin=1'b0;

323
Appendix A

#12 a=1'b1;b=1'b1;cin=1'b0;

end

endmodule

//Program 4X4 Multiplier using Shift Operation

module mult4(a,b,y);
input [3:0]a,b;
output [7:0] y;

//wire [5:0] am,bm;

wire [7:0] pp1;

wire [7:0] pp2;
wire [7:0] pp3;
wire [7:0] pp4;

wire [7:0] pp12;

wire [7:0] pp34;

//generate the partial products using shift

assign pp1 = b[0] ? a: 7'b0;

assign pp2 = b[1] ? a << 1:7'b0;
assign pp3 = b[2] ? a<< 2: 7'b0;
assign pp4 = b[3] ? a<< 3: 7'b0;

//sum partial products

assign pp12 = pp1 + pp2;

assign pp34 = pp3 + pp4;
assign y[7:0] = pp12 + pp34;

endmodule

###TEST BENCH for 4x4 Multiplier using Shift Operation in Verilog

`include "mult4.v"
module stimulus;

reg [3:0] a,b;

wire [7:0]y;

324
 VHDL and Verilog Examples

initial
$monitor($time, "product= %d , a = %d b = %d ", y, a,b);

//instantiate the design

mult4 m1(a,b,y);

// stimulus

initial
begin

#1 a=4'd5; b=4'd3;
#1 a=4'd2; b=4'd4;

end

endmodule

### SAMPLE OUTPUTDATA

product= x , a = x b = x

product= 15 , a = 5 b = 3

product= 8 , a = 2 b = 4

####PROGRAM 4X4 array MULTIPLIER

module arraymul4(a,b,y);

//input and output declarations

input [3:0]a,b;
output [7:0] y;

//wire declarations

wire net1, net2,cnet121,

net3,net4,net5,net6,net7,net8,net9,net10,net11,net12,net13,net14,net15,
cnet12,cnet34,cnet345,net67, net34,cnet67,cnet89,net1011,cnet1011,cnet1314,net89,
cnet891,cnet131,net1314;

325
Appendix A

wire temp1,ctemp2,temp2,ctemp3,ctemp1;

assign net1 = (a[1] & b[0]);

assign net2 = (a[0] & b[1]);
assign cnet12 = (net1 & net2);

assign net3 = (a[2] & b[0]);

assign net4 = (a[1] & b[1]);
assign net5 = (a[0] & b[2]);
assign net6 = (a[3] & b[0]);
assign net7 = (a[2] & b[1]);
assign net8 = (a[1] & b[2]);
assign net9 = (a[0] & b[3]);
assign net10 = (a[3] & b[1]);
assign net11 = (a[2] & b[2]);
assign net12 = (a[1] & b[3]);
assign net13 = (a[3] & b[2]);
assign net14 = (a[2] & b[3]);
assign net15 = (a[3] & b[3]);

assign y[0] = (a[0] & b[0]);

assign y[1] = (net1 ^ net2 );

assign net34 = (net3 ^ net4 ^ cnet12);

assign cnet34 = (net3 & net4) | ((net3 | net4)& cnet12);
assign y[2] = (net5 ^ net34 ^ 1'b0);
assign cnet345 = (net5 & net34) ;
assign cnet67 = (net6 & net7) | ((net6 | net7)& cnet34);
assign net67 = (net6 ^ net7 ^ cnet34);
assign temp1 = (net8 ^ net9 ^ net67);
assign cnet89 = (net8 & net9) | ((net8 | net9)& net67);
assign y[3] = temp1 ^ cnet345 ;
assign ctemp1 = temp1 & cnet345;
assign net1011 = (net10 ^ net11 ^ cnet89);
assign cnet1011 = (net10 & net11) | ((net10 | net11)& cnet89);
assign temp2 = (net12 ^ net1011 ^ cnet67);
assign ctemp2 = (net12 & net1011) | ((net12 | net1011) & cnet67);
assign y[4] = temp2 ^ ctemp1;
assign ctemp3 = temp2 & ctemp1;
assign net1314 = (net13 ^ net14 ^ cnet1011);
assign cnet1314 = (net13 & net14) | ((net13 | net14) & cnet1011);
assign y[5] = net1314 ^ ctemp2 ^ ctemp3 ;
assign cnet131 =(net1314 & ctemp2) | ((net1314 | ctemp2) & ctemp3);
assign y[6] = (net15 ^ cnet1314 ^ cnet131);
assign y[7] = (net15 & cnet1314) | ((net15 | cnet1314) & cnet131);
endmodule

326
 B
Internet Resources

References (4)
Internet Resources

www.acm.org Association for Computing Machinery

www.actel.com Actel

www.altera.com Altera

www.atmel.com Atmel

www.demosondemand.com Website that gives products and tools demonstration

www.eda.org EDA Industry Working Groups website

www.fpga4fun.com Home for FPGA tutorials, projects and boards

www.fpgajournal.com FPGA and programmable logic journal

www.fpgaworld.com FPGA design demonstrations

www.geda.seul.org Website dedicated to GPL tools for EDA

www.ieee.org Institute of Electrical and Electronic Engineers

www.latticesemi.com Lattice Semiconductors

www.mathworks.com The Mathworks Inc. (MATLAB and SIMULINK)

www.mentor.com Mentor Graphics

www.microwind.net Microwind Inc., France (Micorwind Tools)

www.mosis.org MOS Implementation Service

www.opencores.org Open source cores

www.openfpga.org FPGA standardization forum

www.ovi.org Open Verilog International

Appendix B

Internet Resources

www.pentek.com Pentek Inc., a leading supplier of FPGA-based

hardware

www.soccentral.com Provides resources on SOC, FPGA, and ASIC

www.synplicity.com Synplicity

www.systemc.org Open SystemC Community website

www.techonline.com Website that gives resources and virtual lab access

on embedded systems, DSP, and FPGAs

www.telelogic.com Telelogic

http://trident.sf.net Open source C to HDL tool

www.vhdl.org EDA Industry Working Groups website

www.wileydreamtech.com Wiley Dreamtech India Pvt. Ltd

www.xilinx.com Xilinx

Reference Books
 Douglas A. Pucknell, Fundamentals of Digital Logic Design: with VLSI circuit applications, Prentice
Hall Inc., 1990.
 Douglas L. Perry, VHDL Programming by Example, 4th Edition, Tata McGraw Hill, 2002.
 Farzad Nekoogar and Faranak Nekoogar, From ASICs to SOCs: A Practical Approach, Pearson
Education, 2003.
JanM. Rabaey, Anantha Chandakasan and Borivoje Nilolic, Digital Integrated Circuits: A Design
Perspective, Pearson Education, 2003.
 John P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley & Sons, 2005.
 Kamran Eshraghian, Douglas A. Pucknell, Sholeh Eshraghian, Essentials of VLSI Circuits and
Systems, Prentice Hall, 2005.
 Peter Marwedel, Embedded System Design, Kluwer Academic Publishers, Netherlands, 2003.
 Prasad K.V.K.K. Embedded/Real Time Systems: Design, Concepts and Programming, Black Book,
Dreamtech Press, 2005.
 Sivarama P. Dandamudi, Guide to RISC Processors for Programmers and Engineers, Springer
Science+Business Media Inc., 2005.
 Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, Tata
McGraw Hill, 2006.
 Uwe Meyer-Baese, Digital Signal Processing with FPGAs, Springer Verlag, 2001.

328
 C
Acronyms and
Abbreviations

ADC Analog to Digital Converter

ALU Arithmetic Logic Unit

AMBA Advanced Microcontroller Bus Architecture

AOI AND-OR-INVERT

API Application Programming Interface

ASIC Application Specific Integrated Circuit

ASSP Application Specific Standard Part/Product

BiCMOS Bipolar Complementary Metal Oxide Semiconductor

BIOS Basic Input Output System

BIST Built In Self Test

BJT Bipolar Junction Transistor

CAD Computer Aided Design

CAM Content Addressable Memory

Appendix C

CDMA Code Division Multiple Access

CE Chip Enable

CLA Carry Look-ahead Adders

CLB Configurable/Complex Logic Block

CLK Clock

CMOS Complementary Metal Oxide Semiconductor

CPA Carry-Propagate Adder

CPL Complementary Pass-Transistor Logic

CPLD Complex Programmable Logic Device

CPU Central Processing Unit

CS Chip Select

CSA Carry-Save Adder

CSMA/CD Carrier Sense Multiple Access/Collision Detection

CSP Chip Scale Packaging

CUT Chip Under Test

DAC Digital to Analog Converter

DAQ Data Acquisition

DCM Digital Clock Manager

DFF D-type Flip Flop

DFS Digital Frequency Synthesizer

DLL Delay-Locked Loop

DMA Direct Memory Access

DPS Digital Phase Shifter

DR Design Rule

DRAM Dynamic Random Access Memory

330
 Acronyms and Abbreviations

DRC Design Rule Checker

DSP Digital Signal Processor/Processing

DUT Device Under Test

EAPROM Erasable Alterable Programmable Read Only Memory

EDA Electronic Design Automation

EDIF Electronic Design Interchange Format

EPLD Erasable Programmable Logic Device

EPROM Erasable Programmable Read Only Memory

E2PROM Electrically Erasable Programmable Read Only Memory

FET Field Effect Transistor

FFT Fast Fourier Transform

FI Fan In

FIFO First In First Out

FIR Finite Impulse Response

FO Fan Out

FPGA Field Programmable Gate Array

FSM Finite State Machine

GaAs Gallium Arsenide

GOS Gate-Oxide Short

GPP General Purpose Processor

GPRS General Packet Radio Service

GSM Global System for Mobile Communications

HDL Hardware Description Language

HDVL Hardware Design and Verification Language

HLL High Level Language

331
Appendix C

HSTL High Speed Transistor Logic

IC Integrated Circuit

IEEE Institute of Electrical and Electronic Engineers

IGFET Insulated Gate Field Effect Transistor

IIR Infinite Impulse Response

ILA Integrated Logic Analysis

IOB Input Output Buffer/Block

IP Internet Protocol/Intellectual Property

ISE Integrated Software Environment

ISP In System Programming

JTAG Joint Test Action Group

LC Logic Cell

LFSR Linear Feedback Shift Register

LSI Large Scale Integration

LUT Look-Up Table

MAC Multiply And Accumulate

MIPS Million Instructions Per Second

MOPS Million Operations Per Second

MOSFET Metal Oxide Semiconductor Field Effect Transistor

MOSIS Metal Oxide Semiconductor Implementation Service

MSB Most Significant Bit

MTBF Mean Time Between Failures

MTTF Mean Time To Failure

MUX Multiplexer

NRE Non-Recurring Engineering (cost)

332
 Acronyms and Abbreviations

NVRAM Non-Volatile Random Access Memory

OAI OR-AND-INVERT

PAR Place and Route

PCB Printed Circuit Board

PCI Peripheral Component Interconnect

PCMCIA Personal Computer Memory Card International Association

PDA Personal Digital Assistant

PDF Probability Distribution Function

PE Processor Element

PGA Pin Grid Array

PLA Programmable Logic Array

PLCC Plastic Leadless Chip Carrier

PLD Programmable Logic Device

PLL Phase Locked Loop

PROM Programmable Read Only Memory

QFP Quad Flat Pack

RAM Random Access Memory

ROM Read Only Memory

RTL Register Transfer Level

SDR Software Defined Radio

SDRAM Synchronous Dynamic Random Access Memory

SIMD Single Instruction Multiple Data

SiO2 Silicon Dioxide

SMT Surface Mount Technology

SNR Signal to Noise Ratio

333
Appendix C

SOC System-On-Chip

SOI Silicon-On-Insulator

SOIC Small Outline Integrated Circuit

SOP Sum of Products

SR Software Radio

SRAM Static Random Access Memory

SSN Simultaneous Switching Noise

SSTL Stub Series Terminated Logic

TCP Transmission Control Protocol

TDMA Time Division Multiple Access

TG Transmission Gate

TQFP Thin Quad Flat Pack

TSMC Taiwan Semiconductor Manufacturing Corporation

TSOP Thin Small Outline Package

UART Universal Asynchronous Receiver/Transmitter

UCF User Constraints File

ULM Universal Logic Module

ULSI Ultra Large Scale Integration

USB Universal Serial Bus

UV Ultraviolet

VHDL VHSIC Hardware Design Language

VHSIC Very High Speed Integrated Circuit

VLSI Very Large Scale Integration

XNOR Exclusive NOR

XOR Exclusive OR

334
 Glossary
ASIC two bits; whereas, the full adder is a circuit
that performs the addition of three binary bits.
Stands for Application Specific Integrated
Circuit. It is an integrated circuit used to Asynchronous
design digital logic based on full-custom
design. Refers to a logic that is not synchronized by a
clock.
ALU
ATM
Stands for Arithmetic Logic Unit. It is a digital
circuit that performs addition, subtraction, Stands for Asynchronous Transfer Mode. It is
multiplication, division, and other Boolean a dedicated-connection switching technology
functions. that organizes digital data into 53-byte cell
units and transmits them over a physical
ATPG medium using digital signal technology.
Stands for Automatic Test Pattern Generation. ADC
It is an electronic design automation test
generation tool to verify the given digital Stands for Analog-to-Digital Converter. It is a
design by determining the input test sequence circuit, which takes analog input and transmits
that, when applied to a digital circuit, enables the digital output.
automatic test equipment to distinguish
between the correct circuit behavior and the
faulty circuit behavior caused by defects. The Back annotation
generated patterns are used to test Refers to a process of assigning delays from a
semiconductor devices after their manufacture given source file for the cells in a netlist during
to determine the reasons of failure. netlist simulation.

Adder Bit error rate

Refers to a Boolean circuit that performs the Refers to the measurement of the number of
addition of binary bits. The Adder circuit is of errors detected at the receiver’s end in a given
two types: half adder and full adder. The half length of time.
adder is a circuit that performs the addition of
 Glossary

BIST Clock skew

Stands for Built-In Self-Test. It is a process of Refers to the phase shift in a single clock
structured test techniques for combinational distribution network resulting from the
and sequential logic, memories, multipliers, different delays in clock-driving elements
and other embedded logic blocks. and/or different distribution paths.

BIT CPLD
Stands for Binary Digit. It is the basic unit of Stands for Complex Programmable Logic
information represented in digital systems in Device. It is a programmable logic device that
two forms, logic 0 and logic 1. is used to implement the digital designs by
using a set of macro cells.
Bitstream
Refers to a Field Programmable Gate Array CAD
(FPGA) configuration file, which is a Stands for Computer-Aided Design. It is
contiguous sequence of bits, representing a software used to design products, such as
stream of data, transmitted continuously over electronic circuit boards in computers.
a communications path, serially (one at a time)
loaded onto FPGAs. CLB
Stands for Configurable Logic Block. It is a
Bottom up design logic element that is used in Xilinx FPGA
Refers to a design approach that begins with devices.
the lowest-level blocks and builds the design
upward to the top level. Dual port
Refers to the two independent data ports
Black box allowing access to the same memory.
Refers to the testing of an Integrated Circuit
(IC) block whose internal details are hidden DFT
from the designer. Stands for Design for Test. It is a set of design
techniques that makes the test generation and
Bipolar test verification methods.
Refers to a process technology that employs
two junction transistors, NPN and PNP. DAC
Stands for Digital -to-Analog Converter. It
BiCMOS converts the data into an analog format.
Stands for Bipolar Complementary Metal Oxide
Semiconductor. It is a mixed technology Embedded systems
process that consists of bipolar transistors and Refers to the microcomputer embedded in
CMOS logic. control system that is non-accessible to users.

Configuration Embedded software

Refers to the process of programming the Refers to software that runs the embedded
stream of data or loading the program onto an systems.
FPGA.
Emulation
Constraints Refers to a process in which a device being
Refers to the implementation parameters developed is prototyped prior to manufacture.
defined by an end user.

336
 Glossary

DUT Flip flop

Stands for Device Under Test. It is a circuit to Refers to the edge sensitive storage element.
be tested that is represented in behavioral or
gate-level representation before Fault
manufacturing. Refers to the defect in the line or circuit.

EDA Fault coverage

Stands for Electronic Design Automation. It is Refers to the number of faults detected over
a software tool to aid the design of electronic the total number of faults with the given test
systems and chips. vector.

EPROM Floor planner

Stands for Erasable Programmable Read Only Refers to the tool for graphical analysis and
Memory. It is a type of programmable ROM specification of the placement of functional
that can be erased at regular interval of times. blocks within the chip layout and allocation of
EPROM is one time erasable ROM. interconnect routing between them such that
an optimum layout is achieved.
EEPROM
Stands for Electronically Erasable FPGA
Programmable Read Only Memory. It is a type Refers to an IC with fixed arrays of logic
of programmable ROM that can be erased blocks and a fixed mesh of interconnect wires.
electrically by applying voltage to one of the These interconnection wires and logic blocks
pins of the circuit. Individual bits of the can be programmed by Random Access
program can be erased in EEPROM. Memory (RAM), Flash memory, or fusible
links.
FSM
Stands for Finite State Machine. It is a Gate
mathematical model present in one of the Refers to a smallest logic element with several
finite states used to design digital circuits. inputs and one output.

Gate array
Front-end design Refers to an ASIC where transistors are
Refers to a sequence of steps to design ICs, predefined and interconnection pattern is
which include design capture, verification, customized.
and synthesis.
Half byte
Fan-in Refers to a four-bit data.
Refers to a number of inputs that drives the
gate. For a two input AND gate, the fan-in is Harvard architecture
two. Refers to a processor architecture in which
separate buses are used to access program
Fan-out memory and data memory.
Refers to the maximum number of lines that
the output of the gate can drive. Hierarchical design
Refers to a design description in multiple
layers.

337
 Glossary

HVL Mapping
Stands for Hardware Verification Language. It Refers to the process of assigning portions of
is used to test and validate the design logic design to a physical design.
represented in behavioral, Register-Transfer
Level (RTL), and gate-level descriptions. Masking
Refers to the process in which an operation
IC can be performed on a single bit.
Refers to a semiconductor circuit with
electronic devices (transistors, resistors, and Memory map
capacitors) and interconnect wiring integrated Refers to the documentation that lists or shows
in or on the chip. the function of each location in memory.
Place and route: Refers to one of the important
ISE
steps in design process where all the logic is
Stands for Integrated Software Environment, placed onto logic blocks in FPGA and
which is an EDA tool by Xilinx Corporation. interconnection between the logic blocks is
done.
LUT
Stands for LookUp Table, which is a function NCD
generator with n-inputs and a single output. Stands for Native Circuit Description, which is
Two LUTs can be used to build any Boolean an output of the simulation and synthesis tool
function of up to two variables, that is, 16 in the form of netlists.
Boolean functions. Similarly, three LUTs can
be used to build 256 Boolean functions. Netlist
Refers to the textual representation of logic
JTAG
and interconnects.
Stands for Joint Test Action Group, which is a
serial protocol used to transfer the binary bits OCM
onto a board, such as FPGA. Stands for On-Chip Memory, which is an
interface that supports the attachment of
IP
additional memory to the instruction and data.
Stands for Intellectual Property. It is a block of
predesigned blocks, also called cores, macros, Optimization
or virtual components. Refers to the design change to improve the
performance of the optimized circuit based on
MOS
area of the chip, power consumption, and
Stands for Metal Oxide Semiconductor. It is a delay optimization.
transistor formed with a P or N source and
drain, and a metal gate over an insulator forms Placement
an N or P channel when a charge is put on the Refers to the process of assigning specific parts
metal gate of the design to particular locations on the
chip in FPGAs.
MUX
Stands for Multiplexer, which is a Pipeline processing
combinational circuit that selects one of the Refers to a technique to run multiple
inputs using select lines. instructions concurrently in a single cycle.

338
 Glossary

PLD SOC
Stands for Programmable Logic Device, which Stands for System-On-Chip, which is an IC
is a digital circuit that can be programmable. that consists of processor, memory, and
input/output devices; for example, FPGA and
PLL ASIC.
Stands for Phase Locked Loop, which is an
electronic circuit that controls an oscillator so Simulation
that it maintains a constant phase angle Refers to the functional verification of the
relative to a reference signal. circuit.

Register SRAM
Refers to a memory location that is part of a Refers to the Static Random Access Memory. It
memory or processor. is a type of memory where the bistable
latching is used to store the data. Refreshing is
RAM not required due to bistable logic.
Refers to the form of data storage where the
data can be accessed randomly from any Static timing
location. Refers to the detailed description of on-chip
logic and interconnection delay.
ROM
Refers to a memory, which is fabricated with Test vector
the desired data to be stored permanently in it. Refers to the set of vectors used to determine
faults in a circuit.
RTL
Stands for Register Transfer Language, which Test vectors
is a behavioral description of the design at Refers to the sequence of binary bits used to
abstract level. verify the functionality of the circuit.

Routing Test cases

Refers to the interconnection or the process of Refers to the set of input parameters to test the
creating the desired interconnection logic cells software.
to make them perform the required functions.
Timing
Schematic Relates to delays, performance, and speed.
Refers to the graphical representation of a
design implementation in terms of logic gates. TTL
Stands for Transistor-Transistor Logic that
Synthesis tool performs both logic gating and amplifying
Refers to a tool that translates an HDL into a with transistors.
netlist (design implementation in terms of
logic gates). UART
Stands for Universal Asynchronous
Skew Receiver/Transmitter. It is a device that
Refers to the difference in timing that shows transmits and receives asynchronous data.
the delays at different nodes.

339
 Glossary

USB VCD
Stands for Universal Serial Bus. It is a standard Stands for Value Change Dump. It is an ASCII
serial bus that supports higher data rates than file generated by simulation tools capturing
RS232. You can connect up to 127 devices to a the value changes on selected variables in a
USB host. simulation.

Von- Newman Architecture Xilinx

Refers to an architecture that has shared bus Refers to a popular fabless semiconductor
for data and instruction. manufacturing company of producing the
PLDs.
Verilog
Refers to an HDL to represent a digital design. XOR
Stands for Exclusive OR. It is a digital logic
VHDL gate that implements an exclusive-or, where
Stands for Very High Speed Integrated Circuit exclusive means that the output will be logic 1
HDL, which is used to represent a digital only when one or the other but not both of the
design. inputs is logic 1.

Yield
Refers to the percentage of defect-free (usable)
die on a silicon wafer.

340
 Index
CPLD, 148, 151, 152, 157, 158, 200, 330
A
ADC, 73, 210, 211, 212, 247, 248, 249, 257, 258,
D
259, 261, 262, 264, 329 DAC, 73, 211, 212, 247, 248, 249, 251, 253, 254,
Adder, 55, 56, 57, 62, 98, 146, 147, 181, 182, 257, 258, 259, 261, 262, 264, 330
183, 184, 185, 187, 231, 232, 234, 322, 323, DUT, 65, 66, 137, 141, 295, 296, 315, 331
330
ALU, 10, 14, 329 E
ASIC, 3, 6, 7, 9, 10, 13, 14, 64, 66, 70, 76, 78, 79,
EDA, 2, 6, 9, 13, 75, 76, 77, 79, 81, 83, 85, 87, 89,
83, 100, 102, 137, 141, 143, 150, 151, 152, 154,
91, 93, 95, 97, 99, 100, 102, 271, 272, 327, 328,
164, 264, 328, 329
331
Asynchronous, 27, 31, 60, 61, 96, 221, 292, 334
EEPROM, 79, 147, 148, 151, 157, 264

B Emulation, 97
EPROM, 79, 147, 148, 151, 157, 264, 331
BiCMOS, 37, 38, 46, 47, 48, 329
Bipolar, 38, 329 F
BIST, 329
Fan-out, 34, 69
BIT, 279, 280
Fault, 65, 66, 67, 74

C Fault coverage, 66, 74

Flip flop, 293
CAD, 4, 7, 64, 76, 100, 159, 265, 271, 273, 274,
Floor planner, 94, 95
329
FPGA, 1, 5, 7, 9, 10, 11, 12, 14, 64, 66, 69, 70, 76,
CLB, 148, 149, 155, 164, 201, 330
77, 78, 79, 83, 100, 102, 106, 107, 137, 141,
Clock skew, 72 142, 143, 144, 148, 149, 150, 151, 152, 153,
Configuration, 103, 157, 158, 202, 240 154, 155, 156, 157, 158, 159, 160, 161, 162,
163, 164, 165, 167, 169, 171, 173, 175, 177,
Constraints, 91, 256, 257, 334
Index

179, 180, 200, 201, 202, 205, 208, 210, 211,

212, 213, 231, 247, 248, 249, 259, 260, 261,
J
262, 267, 327, 328, 331 JTAG, 100, 149, 158, 200, 202, 210, 262, 332
FSM, 8, 331
L
G LUT, 10, 11, 14, 83, 107, 108, 110, 112, 114, 116,
Gate, 5, 7, 10, 12, 16, 17, 18, 24, 34, 35, 42, 44, 118, 120, 124, 127, 137, 139, 140, 142, 154,
47, 65, 69, 76, 102, 104, 106, 107, 108, 109, 155, 163, 164, 169, 175, 178, 179, 180, 184,
110, 111, 112, 113, 114, 115, 116, 117, 118, 185, 186, 189, 190, 191, 194, 197, 247, 278,
119, 120, 130, 131, 132, 133, 134, 135, 138, 282, 283, 288, 292, 310, 332
144, 154, 184, 185, 186, 189, 190, 191, 200,
210, 266, 267, 271, 331, 332, 334 M
H Mapping, 10, 11, 201
Masking, 40
Hierarchical design, 81
MOS, 4, 37, 38, 39, 41, 42, 43, 44, 45, 46, 47, 48,
HVL, 99 67, 312, 313, 327, 328, 329, 330, 332
MUX, 50, 51, 57, 58, 61, 62, 288, 289, 290, 332
I
IC, 2, 3, 6, 7, 9, 10, 13, 14, 38, 39, 40, 41, 46, 64, N
66, 70, 76, 78, 79, 83, 89, 100, 102, 106, 109,
NCD, 201
111, 113, 115, 117, 119, 122, 137, 141, 143,
145, 147, 149, 150, 151, 152, 154, 164, 171, Netlist, 81, 138, 139, 156, 160
172, 176, 182, 183, 186, 223, 224, 235, 243,
249, 250, 252, 253, 258, 264, 275, 276, 277, P
279, 280, 283, 285, 289, 294, 296, 297, 300,
301, 305, 311, 312, 313, 314, 315, 316, 317, Placement, 78
328, 329, 332, 334 PLD, 143, 144, 146, 147, 148, 150, 151, 152, 157,
IP, 13, 156, 157, 172, 186, 218, 225, 231, 233, 158, 200, 330, 331, 333
239, 265, 266, 267, 268, 276, 279, 283, 288, PLL, 73, 333
292, 293, 304, 310, 311, 312, 325, 332
ISE, 12, 77, 79, 83, 88, 89, 100, 106, 107, 109, R
111, 113, 115, 117, 119, 121, 125, 137, 158,
159, 164, 165, 171, 176, 182, 183, 186, 188, RAM, 57, 59, 62, 149, 150, 151, 154, 157, 164,
193, 196, 199, 200, 202, 206, 208, 213, 217, 166, 170, 172, 173, 179, 202, 210, 247, 264,
226, 231, 235, 239, 261, 275, 332 267, 275, 276, 279, 283, 289, 290, 293, 304,
305, 310, 311, 312, 313, 325, 330, 333, 334

342
 Index

Register, 12, 79, 96, 130, 136, 141, 175, 176, 179,
233, 266, 272, 332, 333
V
ROM, 57, 58, 59, 62, 79, 104, 146, 147, 148, 150, Verilog, 7, 8, 10, 11, 12, 14, 77, 79, 81, 82, 84,
151, 152, 157, 158, 162, 264, 331, 333 85, 86, 97, 99, 101, 102, 107, 127, 128, 129,
130, 131, 132, 134, 135, 136, 137, 140, 141,
Routing, 10, 11, 201
142, 157, 158, 159, 180, 182, 200, 214, 215,
RTL, 12, 79, 80, 91, 92, 97, 98, 99, 101, 141, 142, 216, 222, 272, 275, 277, 279, 281, 283, 285,
272, 273, 274, 333 287, 289, 291, 293, 295, 297, 299, 301, 303,
305, 307, 309, 311, 313, 315, 317, 319, 321,
S 322, 323, 324, 325, 328

Schematic, 19, 20, 22, 41, 81, 84, 91, 92, 184, VHDL, 7, 8, 10, 11, 12, 77, 79, 81, 82, 84, 85, 86,
185, 200, 214 87, 88, 93, 97, 99, 101, 102, 103, 104, 105, 106,
107, 109, 111, 113, 115, 117, 119, 121, 125,
Simulation, 12, 90, 92, 93, 94, 95, 97, 100, 101,
136, 137, 141, 142, 157, 158, 159, 160, 164,
103, 105, 107, 108, 109, 110, 111, 112, 113,
165, 170, 171, 175, 176, 179, 180, 181, 182,
114, 115, 116, 117, 118, 119, 120, 121, 123,
183, 185, 186, 187, 188, 189, 191, 193, 195,
124, 125, 127, 129, 131, 132, 133, 134, 135,
196, 197, 198, 200, 208, 214, 215, 216, 217,
136, 137, 139, 141, 142, 170, 175, 179, 191,
218, 222, 223, 235, 239, 242, 272, 275, 277,
194, 195, 197, 201, 209, 217, 225, 226, 230,
279, 281, 283, 285, 287, 289, 291, 293, 295,
238, 246, 300, 303, 321
297, 299, 301, 303, 305, 307, 309, 311, 313,
Skew, 71, 72 315, 317, 319, 321, 323, 325, 328, 334
SOC, 2, 3, 6, 264, 265, 266, 267, 268, 328, 334
SRAM, 149, 150, 154, 157, 179, 210, 334 X
Static timing, 77, 95, 160, 162 Xilinx, 9, 12, 14, 76, 77, 79, 83, 88, 89, 90, 91, 93,
Synthesis tool, 78 94, 96, 100, 103, 106, 107, 109, 111, 113, 117,
119, 122, 137, 142, 148, 150, 151, 154, 155,

T 156, 157, 158, 159, 162, 163, 164, 165, 177,

182, 183, 186, 188, 193, 198, 199, 200, 201,
Test vector, 142 202, 203, 205, 206, 207, 208, 210, 213, 217,
218, 222, 223, 225, 226, 231, 235, 239, 243,
Test vectors, 142
249, 252, 257, 261, 267, 275, 328
Timing, 35, 75, 91, 94, 95, 99, 101, 107, 141,
XOR, 17, 19, 36, 65, 68, 74, 117, 118, 124, 134,
142, 160, 184, 201, 278, 282, 287, 291, 309
334

U
UART, 61, 334
USB, 205, 208, 210, 334

343