Si5328

ITU-T G.8262 S Y N C H R O N O U S E TH ER NET J ITTER -ATTENUATI NG

C LO CK M U LTI PL I E R

Features
 Fully-compliant with ITU-T  Dual clock outputs with
G.8262, EEC options 1 and 2. selectable signal format
 Generates any frequency from (LVPECL, LVDS, CML, CMOS)
8 kHz to 808 MHz.  LOL, LOS, FOS alarm outputs
 Ultra-low jitter clock outputs with  I2C or SPI programmable
jitter generation as low as 0.3 ps  On-chip voltage regulator for
rms (12 kHz–20 MHz) 2.5 ±10% or 3.3 V ±10%
 Integrated loop filter with operation Ordering Information:
selectable loop bandwidth  Small size: 6 x 6 mm 36-lead
(0.1 Hz; 1 to 10 Hz) See page 63.
QFN
 Dual clock inputs with manual or  Pb-free, ROHS compliant
automatically controlled hitless
Pin Assignments
switching

Applications

CKOUT1–
CKOUT1+
CKOUT2+
CKOUT2–
CMODE

VDD
GND
 G.8262 Synchronous Ethernet,  Carrier Ethernet switches,

NC

NC
EEC options 1 and 2 routers RST 1
36 35 34 33 32 31 30 29 28
27 SDI

 GbE/10GbE/100GbE NC 2 26 A2_SS
INT_C1B 3 25 A1
Synchronous Ethernet C2B 4 24 A0
VDD 5
GND 23 SDA_SDO
Pad
Description
XA 6 22 SCL
XB 7 21 CS_CA
GND 8 20 NC

The Si5328 is a jitter-attenuating precision clock multiplier for NC 9

10 11 12 13 14 15 16 17 18
19 NC

Synchronous Ethernet applications requiring sub 1 ps jitter performance

VDD

RATE0
CKIN2+
CKIN2–
NC
RATE1
CKIN1+
CKIN1–
LOL
and ultra-low loop bandwidth. When combined with a low-wander, low-
jitter reference oscillator, the Si5328 meets all of the wander, MTIE,
TDEV, and other requirements listed in ITU-T G.8262/Y.1362. The Si5328
accepts two input clocks ranging from 8 kHz to 710 MHz and generates
two output clocks ranging from 8 kHz to 808 MHz. The two outputs are
divided down separately from a common source.
The Si5328 can also use the TCXO as a clock source for frequency
synthesis. The device provides virtually any frequency translation
combination across this operating range. The Si5328 input clock
frequency and clock multiplication ratio are programmable through an I2C
or SPI interface.
The Si5328 is based on Skyworks Solutions' third-generation DSPLL®
technology, which provides frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need for external VCXO
and loop filter components. The DSPLL loop bandwidth is digitally
programmable, providing jitter performance optimization at the application
level. Operating from a single 2.5 or 3.3 V supply, the Si5328 is ideal for
providing clock multiplication and jitter attenuation in high-performance,
Synchronous Ethernet timing applications.

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Si5328
Functional Block Diagram

TCXO or Refclock

Hitless Switching
CKIN1 ÷ N31 Mux
÷ N1_LS CKOUT1
CKIN2 ®
÷ N32 DSPLL ÷ N1_HS
÷ N2_LS CKOUT2

Refclock
÷ N2

Loss of Signal/
VDD (2.5 or 3.3 V)
Frequency Offset Signal Detect Control
Loss of Lock GND

I2C/SPI Port Clock Select

Device Interrupt
Rate Select

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 Si5328
TA B L E O F C O N T E N T S

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1. External XAXB Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Pin Descriptions: Si5328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
11. Si5328 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

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Si5328
1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature TA –40 25 85 C
Supply Voltage during VDD 3.3 V Nominal 2.97 3.3 3.63 V
Normal Operation
2.5 V Nominal 2.25 2.5 2.75 V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.

V
SIGNAL +
Single-Ended
Differential I/Os VICM , VOCM VISE , VOSE
Peak-to-Peak Voltage
SIGNAL –

(SIGNAL +) – (SIGNAL –)
VID,VOD Differential Peak-to-Peak Voltage
VICM, VOCM
t

SIGNAL +
VID = (SIGNAL+) – (SIGNAL–)
SIGNAL –

Figure 1. Differential Voltage Characteristics

80%
CKIN, CKOUT
20%
tF tR

Figure 2. Rise/Fall Time Characteristics

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 Si5328

Table 2. DC Characteristics
(VDD = 2.5 V ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Supply Current1 IDD LVPECL Format — 251 279 mA
808 MHz Out
Both CKOUTs Enabled
LVPECL Format — 217 243 mA
808 MHz Out
1 CKOUT Enabled
CMOS Format — 204 234 mA
25 MHz Out
Both CKOUTs Enabled
CMOS Format — 194 220 mA
25 MHz Out
1 CKOUT Enabled
Disable Mode — 165 — mA

CKINn Input Pins2

Input Common Mode VICM 2.5 V ± 10% 1 — 1.7 V

Voltage (Input Thresh-
old Voltage) 3.3 V ± 10% 1.1 — 1.95 V

Input Resistance CKNRIN Single-ended 20 40 60 k

Single-Ended Input VISE fCKIN < 212.5 MHz 0.2 — — VPP

Voltage Swing See Figure 1.
(See Absolute Specs)
fCKIN > 212.5 MHz 0.25 — — VPP
See Figure 1.
Differential Input VID fCKIN < 212.5 MHz 0.2 — — VPP
Voltage Swing See Figure 1.
(See Absolute Specs)
fCKIN > 212.5 MHz 0.25 — — VPP
See Figure 1.
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 312.5 MHz.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.

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Si5328
Table 2. DC Characteristics (Continued)
(VDD = 2.5 V ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Output Clocks (CKOUTn)

Common Mode CKOVCM LVPECL 100  load line- VDD –1.42 — VDD –1.25 V
to-line
Differential Output CKOVD LVPECL 100  load line- 1.1 — 1.9 VPP
Swing3 to-line
Single Ended Output CKOVSE LVPECL 100  load line- 0.5 — 0.93 VPP
Swing3 to-line
Differential Output CKOVD CML 100  load line-to- 350 425 500 mVPP
Voltage3 line
Common Mode Output CKOVCM CML 100  load line-to- — VDD–0.36 — V
Voltage3 line
Differential Output CKOVD LVDS 500 700 900 mVPP
Voltage3 100  load line-to-line
Low Swing LVDS 350 425 500 mVPP
100  load line-to-line
Common Mode Output CKOVCM LVDS 100 load line-to- 1.125 1.2 1.275 V
Voltage3 line
Differential Output CKORD CML, LVPECL, LVDS — 200 — 
Resistance
Output Voltage Low CKOVOLLH CMOS — — 0.4 V

Output Voltage High CKOVOHLH VDD = 2.25 V 0.8 x VDD — — V

CMOS
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 312.5 MHz.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.

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 Si5328
Table 2. DC Characteristics (Continued)
(VDD = 2.5 V ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Output Drive Current CKOIO ICMOS[1:0] =11 — 20 — mA
(CMOS driving into VDD = 2.5 V
CKOVOL for output low
or CKOVOH for output ICMOS[1:0] =10 — 15 — mA
high. CKOUT+ and VDD = 2.5 V
CKOUT– shorted ICMOS[1:0] =01 — 10 — mA
externally)
VDD = 2.5 V
ICMOS[1:0] =00 — 5 — mA
VDD = 2.5 V
ICMOS[1:0] = 11 — 32 — mA
VDD = 3.3 V
ICMOS[1:0] =10 — 24 — mA
VDD = 3.3 V
ICMOS[1:0] =01 — 16 — mA
VDD = 3.3 V
ICMOS[1:0] =00 — 8 — mA
VDD = 3.3 V
2-Level LVCMOS Input Pins

Input Voltage Low VIL VDD = 2.25 V — — 0.7 V

VDD = 2.97 V — — 0.8 V

Input Voltage High VIH VDD = 2.25 V 1.8 — — V

VDD = 3.63 V 2.5 — — V

Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 312.5 MHz.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.

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Si5328
Table 2. DC Characteristics (Continued)
(VDD = 2.5 V ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

3-Level Input Pins4

Input Voltage Low VILL — — 0.15 x VDD V

Input Voltage Mid VIMM 0.45 x — 0.55 x VDD V

VDD
Input Voltage High VIHH 0.85 x — — V
VDD
Input Low Current IILL See Note 4 –20 — — µA

Input Mid Current IIMM See Note 4 –2 — +2 µA

Input High Current IIHH See Note 4 — — 20 µA

LVCMOS Output Pins

Output Voltage Low VOL IO = 2 mA — — 0.4 V

VDD = 2.25 V
Output Voltage Low IO = 2 mA — — 0.4 V
VDD = 2.97 V
Output Voltage High VOH IO = –2 mA VDD –0.4 — — V
VDD = 2.25 V
Output Voltage High IO = –2 mA VDD –0.4 — — V
VDD = 2.97 V
Disabled Leakage IOZ RSTb = 0 –100 — 100 µA
Current
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 312.5 MHz.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.

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Table 3. AC Characteristics
(VDD = 2.5 ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Single-Ended Reference Clock Input Pin XA (XB with cap to GND)

Input Resistance XARIN RATE[1:0] = LM, ML, MH, — 12 — k

ac coupled
Input Voltage Swing XAVPP RATE[1:0] = LM, ML, MH, 0.5 — 1.2 VPP
ac coupled
Differential Reference Clock Input Pins (XA/XB)

Input Voltage Swing XA/XBVPP RATE[1:0] = LM, ML, MH 0.5 — 1.2 VPP,
each.
CKINn Input Pins

Input Frequency CKNF 0.008 — 710 MHz

Input Duty Cycle CKNDC Input frequency > 225 MHz 40 — 60 %

(Minimum Pulse
Width) Input frequency < 225 MHz 2 — — ns
refers to both high and low
widths
Input Capacitance CKNCIN — — 3 pF

Input Rise/Fall Time CKNTRF 20–80% — — 11 ns

See Figure 2
CKOUTn Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency CKOF N1  6 0.008 — 808 MHz
(Output not config-
ured for CMOS)
Maximum Output CKOF — — 212.5 MHz
Frequency in CMOS
Format
Output Rise/Fall CKOTRF CMOS Output — — 8 ns
(20–80%) @ VDD = 2.25
212.5 MHz output CLOAD = 5 pF
Output Rise/Fall CKOTRF CMOS Output — — 2 ns
(20–80%) @ VDD = 2.97
212.5 MHz output CLOAD = 5 pF
Notes:
1. Lock and settle times may change with different f3, loop BW, and VCO frequency values. Contact Skyworks Solutions
for further details.
2. See Section 9 of “AN775: Si5328 Synchronous Ethernet Compliance Test Report” for more details.

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Si5328
Table 3. AC Characteristics (Continued)
(VDD = 2.5 ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Output Rise/Fall CKOTRF LVPECL, LVDS or CML — 230 350 ps
(20–80%) @ Output
312.5 MHz output
Output Duty Cycle CKODC 100  Load 45 — 55 %
Uncertainty @ Line-to-Line
808 MHz Measured at 50% Point
(Not for CMOS)
LVCMOS Input Pins

Minimum Reset Pulse tRSTMN 1 µs

Width
Reset to Microproces- tREADY 10 ms
sor Access Ready
Input Capacitance Cin — — 3 pF

LVCMOS Output Pins

Rise/Fall Times tRF CLOAD = 20pf — 25 — ns

See Figure 2
LOSn Trigger Window LOSTRIG From last CKINn to  — — 4.5 x N3 TCKIN
Internal detection of LOSn
N3 ≠ 1
Time to Clear LOL tCLRLOL LOS to LOL — 10 — ms
after LOS Cleared Fold = Fnew
Stable Xa/XB reference
Device Skew

Output Clock Skew tSKEW  of CKOUTn to  of — — 100 ps

CKOUT_m, CKOUTn
and CKOUT_m at same
frequency and signal
format
PHASEOFFSET = 0
CKOUT_ALWAYS_ON = 1
SQ_ICAL = 1
Phase Change due to tTEMP Max phase changes from – — 300 500 ps
Temperature Variation 40 to +85 °C, stable XAXB
reference
Notes:
1. Lock and settle times may change with different f3, loop BW, and VCO frequency values. Contact Skyworks Solutions
for further details.
2. See Section 9 of “AN775: Si5328 Synchronous Ethernet Compliance Test Report” for more details.

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 Si5328
Table 3. AC Characteristics (Continued)
(VDD = 2.5 ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

PLL Performance
(fin = fout = 346 MHz; BW = 0.088 Hz; LVPECL)
Lock Time1 tLOCKMP Start of ICAL to LOL low, — 2 — s
LOCKT = 4, FASTLOCK
enabled
Start of ICAL to LOL low, — 12.5 — s
LOCKT = 1, FASTLOCK
enabled
Settle Time1 tSETTLE Start of ICAL to output — 1 — s
phase within 45 degrees of
final value, LOCKT = 4,
FASTLOCK enabled
Start of ICAL to output — 1 — s
phase within 45 degrees of
final value, LOCKT = 1,
FASTLOCK enabled
Output Clock Phase tP_STEP After clock switch — 200 — ps
Change f3  128 kHz
Closed Loop Jitter JPK — 0.05 0.2 dB
Peaking
Jitter/Wander JTOL Jitter Frequency Loop 5000/BW — — ns pk-pk
Tolerance2 Bandwidth
Phase Noise 1 kHz Offset — –120 — dBc/Hz
fout = 156.25 MHz
10 kHz Offset — –128 — dBc/Hz
CKOPN
100 kHz Offset — –130 — dBc/Hz

1 MHz Offset — –144 — dBc/Hz

Subharmonic Noise SPSUBH Phase Noise @ 100 kHz — –88 — dBc

Offset
Spurious Noise SPSPUR Max spur @ n x F3 — –93 — dBc
(n  1, n x F3 < 100 MHz)
Notes:
1. Lock and settle times may change with different f3, loop BW, and VCO frequency values. Contact Skyworks Solutions
for further details.
2. See Section 9 of “AN775: Si5328 Synchronous Ethernet Compliance Test Report” for more details.

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Si5328

Table 4. Microprocessor Control

(VDD = 2.5 ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

I2C Bus Lines (SDA, SCL)

Input Voltage Low VILI2C — — 0.25 x VDD V

Input Voltage High VIHI2C 0.7 x VDD — VDD V

Input Current III2C VIN = 0.1 x VDD –10 — 10 µA

to 0.9 x VDD
Hysteresis of Schmitt VHYSI2C 0.05 x VDD — — V
trigger inputs
Output Voltage Low VOLI2C IO = 3 mA — — 0.4 V

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 Si5328
Table 4. Microprocessor Control (Continued)
(VDD = 2.5 ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SPI Specifications

Duty Cycle, SCLK tDC SCLK = 10 MHz 40 — 60 %

Cycle Time, SCLK tc 100 — — ns

Rise Time, SCLK tr 20–80% — — 25 ns

Fall Time, SCLK tf 20–80% — — 25 ns

Low Time, SCLK tlsc 20–20% 30 — — ns

High Time, SCLK thsc 80–80% 30 — — ns

Delay Time, SCLK Fall td1 — — 25 ns

to SDO Active
Delay Time, SCLK Fall td2 — — 25 ns
to SDO Transition
Delay Time, SS Rise td3 — — 25 ns
to SDO Tri-state
Setup Time, SS to tsu1 25 — — ns
SCLK Fall
Hold Time, SS to th1 20 — — ns
SCLK Rise
Setup Time, SDI to tsu2 25 — — ns
SCLK Rise
Hold Time, SDI to th2 20 — — ns
SCLK Rise
Delay Time between tcs 25 — — ns
Slave Selects

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Si5328

Table 5. Jitter Generation1,2,3,4,5,6

Symbol Filter Output Min Typ Max Unit
Frequency
JGEN 12 kHz to 20 MHz 125 MHz — 331 — fs, RMS
JGEN 10 kHz to 1 MHz 125 MHz — 287 — fs, RMS
JGEN 12 kHz to 20 MHz 156.25 MHz — 308 — fs, RMS
JGEN 10 kHz to 1 MHz 156.25 MHz — 263 — fs, RMS
Notes:
1. Input frequency = 25 MHz.
2. XAXB reference = Rakon 40 MHz TCXO model RTX7050A, part number 509768.
3. Vdd = 3.3 V.
4. Clock output = LVPECL.
5. Loop bandwidth = 0.085 Hz.
6. Using Agilent E5052B.

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Table 6. Thermal Characteristics

(VDD = 2.5 ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter Symbol Test Condition Value Unit

Thermal Resistance Junction to Ambient JA Still Air 32 C°/W
Thermal Resistance Junction to Case JC Still Air 14 C°/W

Table 7. Absolute Maximum Ratings

Parameter Symbol Test Condition Min Typ Max Unit

DC Supply Voltage VDD –0.5 — 3.8 V

LVCMOS Input Voltage VDIG –0.3 VDD+0.3 V

CKINn Voltage Level Limits CKNVIN 0 — VDD V

XA/XB Voltage Level Limits XAVIN 0 — 1.2 V

Operating Junction Temperature TJCT –55 — 150 ºC

Storage Temperature Range TSTG –55 — 150 ºC

ESD HBM Tolerance 2 — — kV

(100 pF, 1.5 k); All pins except
CKIN+/CKIN–
ESD MM Tolerance; All pins 150 — — V
except CKIN+/CKIN–
ESD HBM Tolerance 750 — — V
(100 pF, 1.5 k); CKIN+/CKIN–
ESD MM Tolerance; 100 — — V
CKIN+/CKIN–
Latch-up Tolerance JESD78 Compliant

*Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions specified in the operation sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods of time may affect device reliability.

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Si5328
2. Typical Phase Noise Performance

Figure 3. Typical Phase Noise Plot

Table 8. RMS Jitter Values

Jitter Band Jitter (rms)
10 kHz to 1 MHz 263 fs
12 kHz to 20 MHz 309 fs
Notes:
1. input frequency = 25 MHz.
2. XAXB reference = Rakon 40 MHz TCXO model RTX7050A,
part number 509768.
3. Vdd = 3.3 V.
4. Clock output = LVPECL.
5. Loop bandwidth = 0.085 Hz.
6. Using Agilent E5052B.

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 Si5328
3. Typical Application Circuit
Note: For an example schematic and layout, refer to the Si5328-EVB User’s Guide.

C 4 1 µF

System C 1 0.1 µF
Power
Ferrite
Supply
Bead C 2 0.1 µF
V DD = 3.3 V
C 3 0.1 µF
130  130 
0.1 µF
CKIN1+

VDD

GND

GND PAD
GND PAD
CKOUT1+ +

CKIN1– 100 
CKOUT1– –
82  82 
0.1 µF
Clock Outputs
0.1 µF
Input
CKOUT2+ +
Clock V DD = 3.3 V
Sources* 100 
CKOUT2– –
130  130 
0.1 µF
CKIN2+

CKIN2– INT_C1B Interrupt/CKIN1 Invalid Indicator

82  82 
Si5328 C2B CKIN2 Invalid Indicator

V DD
15 k LOL PLL Loss of Lock Indicator
Ref Clk Rate RATE[1:0]2
15 k

A[2:0] Serial Port Address

0.1 µF
Refclk+ XA SDA Serial Data I2C Interface
0.1 µF
Refclk– XB SCL Serial Clock

Control Mode (L) CMODE

CS_CA Clock Select/Clock Active
Reset RST

Notes:
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground),
M (VDD/2), and H (VDD).
3. I2C-required pull-up resistors not shown.

Figure 4. Si5328 Typical Application Circuit (I2C Control Mode)

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Si5328

C4 1 µF
System C1 0.1 µF
Power
Ferrite
Supply
Bead C2 0.1 µF
V DD = 3.3 V
C3 0.1 µF
130  130 
0.1 µF

GND PAD
VDD

GND
CKOUT1+ +
CKIN1+
100 
CKIN1– CKOUT1– –
82  82  0.1 µF
Clock Outputs
0.1 µF
Input CKOUT2+ +
Clock V DD = 3.3 V
Sources* 100 
CKOUT2– –
130  130 
0.1 µF
CKIN2+
INT_C1B Interrupt/CLKIN1 Invalid Indicator
CKIN2–
82  82 
Si5328 C2B CLKIN2 Invalid Indicator

V DD
15 k LOL PLL Loss of Lock Indicator
Ref Clk Rate RATE[1:0]2
15 k
SS Slave Select
0.1 µF
Refclk+ XA SDO Serial Data Out
SPI Interface
0.1 µF SDI Serial Data In
Refclk– XB
SCLK Serial Clock

Control Mode (H) CMODE

CS_CA Clock Select/Clock Active
Reset RST

Notes:
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2),
and H (VDD).

Figure 5. Si5328 Typical Application Circuit (SPI Control Mode)

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 Si5328
4. Functional Description

TCXO or Refclock

Hitless Switching
CKIN1 ÷ N31 Mux
÷ N1_LS CKOUT1
CKIN2 ®
÷ N32 DSPLL ÷ N1_HS
÷ N2_LS CKOUT2

Refclock
÷ N2

Loss of Signal/
VDD (2.5 or 3.3 V)
Frequency Offset Signal Detect Control
Loss of Lock GND

I2C/SPI Port Clock Select

Device Interrupt
Rate Select

Figure 6. Functional Block Diagram

The Si5328 is a jitter-attenuating precision clock The Si5328 supports hitless switching between the two
multiplier for Synchronous Ethernet applications synchronous input clocks in compliance with G.8262
requiring sub 1 ps jitter performance and ultra-low loop that greatly minimizes the propagation of phase
bandwidth. When combined with a low-wander transients to the clock outputs during an input clock
reference oscillator, the Si5328 meets all of the wander, transition (maximum 200 ps phase transient). Manual
MTIE, TDEV, and other requirements that are listed in and automatic revertive and non-revertive input clock
ITU-T G.8262/Y.1362. The Si5328 accepts two input switching options are available. The Si5328 monitors
clocks ranging from 8 kHz to 710 MHz and generates both input clocks for loss-of-signal (LOS) and provides a
two output clocks ranging from 8 kHz to 808 MHz. The LOS alarm (INT_C1B and C2B) when it detects missing
Si5328 can also use its TCXO as a clock source for pulses on either input clock. The device monitors the
frequency synthesis. The device provides virtually any lock status of the PLL. The lock detect algorithm works
frequency translation combination across this operating by continuously monitoring the phase of the input clock
range. Independent dividers are available for each input in relation to the phase of the feedback clock.
clock and output clock, so the Si5328 can accept input The Si5328 also monitors frequency offset alarms
clocks at different frequencies and it can generate (FOS), which indicate if an input clock is within a
output clocks at different frequencies. The Si5328 input specified frequency band relative to the frequency of a
clock frequency and clock multiplication ratio are reference clock. Both Stratum 3/3E and SONET
programmable through an I2C or SPI interface.
Minimum Clock (SMC) FOS thresholds are
Skyworks Solutions offers a PC-based software utility,
supported.The Si5328 provides a digital hold capability
DSPLLsim, that can be used to determine the optimum
that allows the device to continue generation of a stable
PLL divider settings for a given input frequency/clock
output clock when the selected input reference is lost.
multiplication ratio combination that minimizes phase
noise and power consumption. During digital hold, the DSPLL generates an output
frequency based on a historical average frequency that
This utility can be downloaded from
existed for a fixed amount of time before the error event
https://www.skyworksinc.com/en/Application-
occurred, eliminating the effects of phase and frequency
Pages/DSPLL.
transients that may occur immediately preceding digital
The Si5328 is based on Skyworks Solutions' 3rd- hold.
generation DSPLL® technology, which provides any
The Si5328 has two differential clock outputs. The
frequency synthesis and jitter attenuation in a highly
electrical format of each clock output is independently
integrated PLL solution that eliminates the need for
programmable to support LVPECL, LVDS, CML, or
external VCXO and loop filter components. The Si5328
CMOS loads. If not required, the second clock output
PLL loop bandwidth is digitally programmable and
can be powered down to minimize power consumption.
supports a range from less than 0.1 Hz to 6 Hz. The
DSPLLsim software utility can be used to calculate valid
loop bandwidth settings for a given input clock
frequency/clock multiplication ratio.

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Si5328
The phase of one output clock may be adjusted in Report” is a G.8262 test report using a 40 MHz Rakon
relation to the phase of the other output clock with RTX7050A-109 TCXO. See “AN776: Using the Si5328
resolution that varies from 800 ps to 2.2 ns, depending in a G.8262 Compliant SyncE Application” for a
on the PLL divider settings. See Table 9 for instructions discussion of how to select and best use a TCXO as
on ensuring output-to-output alignment. The input to well as a list of other potential TCXO sources.
output skew is not specified or controlled. The
DSPLLsim software utility determines the phase offset 4.2. Further Documentation
resolution for a given input clock/clock multiplication Consult the Skyworks Solutions Si53xx Any Frequency
ratio combination. For system-level debugging, a Precision Clock Family Reference Manual (FRM) for
bypass mode is available which drives the output clock detailed information about the Si5328 functions.
directly from the input clock, bypassing the internal Additional design support is available from Skyworks
DSPLL. The device is powered by a single 2.5 or 3.3 V Solutions through your distributor.
supply. Skyworks Solutions has developed a PC-based
4.1. External XAXB Reference software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
In order to achieve the levels of performance required bandwidth selection.
by G.8262, care must be exercised when selecting an
The FRM and this utility can be downloaded from
XA/XB reference. To meet the wander specifications in
https://www.skyworksinc.com/en/Application-
G.8262, a TCXO or OCXO will be needed.
Pages/DSPLL.
“AN775: Si5328 ITU-T G.8262 SyncE Compliance Test
Table 9. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table
CKOUT_ALWAYS_ON SQ_ICAL Results
0 0 CKOUT OFF until after the first ICAL
0 1 CKOUT OFF until after the first successful
ICAL (i.e., when LOL is low)
1 0 CKOUT always ON, including during an ICAL
1 1 CKOUT always ON, including during an ICAL.
Use these settings to preserve output-to-output
skew

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 Si5328
5. Register Map
All register bits that are not defined in this map should always be written with the specified Reset Values. The writing to these bits of values other than the
specified Reset Values may result in undefined device behavior. Registers not listed, such as Register 64, should never be written to.

Register D7 D6 D5 D4 D3 D2 D1 D0

0 FREE_RUN CKOUT_ALWAYS_ON BYPASS_REG

1 CK_PRIOR2[1:0] CK_PRIOR[1:0]

2 BWSEL_REG[3:0]

3 CKSEL_REG[1:0] DHOLD SQ_ICAL

4 AUTOSEL_REG[1:0] HST_DEL[4:0]

5 ICMOS[1:0]

6 SLEEP SFOUT2_REG[2:0] SFOUT1_REG[2:0]

7 FOSREFSEL[2:0]

8 HLOG_2[1:0] HLOG_1[1:0]

9 HIST_AVG[4:0]

10 DSBL2_ REG DSBL1_ REG

11 PD_CK2 PD_CK1

19 FOS_EN FOS_THR[1:0] VALTIME[1:0] LOCK[T2:0]

20 CK2_BAD_PIN CK1_ BAD_ PIN LOL_PIN INT_PIN

21 CK1_ACTV_PIN CKSEL_PIN

22 CK_ACTV_ POL CK_BAD_ POL LOL_POL INT_POL

23 LOS2_MSK LOS1_MSK LOSX_MSK

24 FOS2_MSK FOS1_MSK LOL_MSK

25 N1_HS[2:0]

31 NC1_LS[19:16]

32 NC1_LS[15:8]

33 NC1_LS[7:0]

34 NC2_LS[19:16]

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Si5328
Register D7 D6 D5 D4 D3 D2 D1 D0

35 NC2_LS[15:8]

36 NC2_LS[7:0]

40 N2_HS[2:0] N2_LS[19:16]

41 N2_LS[15:8]

42 N2_LS[7:0]

43 N31[18:16]

44 N31[15:8]

45 N31[7:0]

46 N32[18:16]

47 N32[15:8]

48 N32[7:0]

55 CLKIN2RATE[2:0] CLKIN1RATE[2:0]

128 CK2_ACTV_REG CK1_ACTV_REG

129 LOS2_INT LOS1_INT LOSX_INT

130 DIGHOLDVALID FOS2_INT FOS1_INT LOL_INT

131 LOS2_FLG LOS1_FLG LOSX_FLG

132 FOS2_FLG FOS1_FLG LOL_FLG

134 PARTNUM_RO[11:4]

135 PARTNUM_RO[3:0] REVID_RO[3:0]

136 RST_REG ICAL GRADE_RO[1:0]

137 FASTLOCK

138 LOS2_EN [1:1] LOS1_EN [1:1]

139 LOS2_EN[0:0] LOS1_EN[0:0] FOS2_EN FOS1_EN

142 INDEPENDENTSKEW1[7:0]

143 INDEPENDENTSKEW2[7:0]

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 Si5328
6. Register Descriptions

Register 0.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name FREE_RUN CKOUT_ALWAYS_ON BYPASS_REG

Type R R/W R/W R R R R/W R

Reset value = 0001 0100

Bit Name Function

7 Reserved Reserved.
6 FREE_RUN Free Run.
Internal to the device, route XA/XB to CKIN2. This allows the device to lock to
its XA-XB reference.
0: Disable
1: Enable
5 CKOUT_ALWAYS_ON CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if SQ_I-
CAL is on and ICAL is not complete or successful. See Table 9 on page 20.
0: Squelch output until part is calibrated (ICAL).
1: Provide an output. Note: The frequency may be significantly off and variable
until the part is calibrated.
4:2 Reserved Reserved.
1 BYPASS_REG Bypass Register.
This bit enables or disables the PLL bypass mode. Use only when the device is
in digital hold or before the first ICAL.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypass-
ing the PLL. Bypass mode does not support CMOS clock outputs.
0 Reserved Reserved.

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Si5328

Register 1.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved CK_PRIOR2 [1:0] CK_PRIOR1 [1:0]

Type R R/W R/W

Reset value = 1110 0100

Bit Name Function

7:4 Reserved Reserved.
3:2 CK_PRIOR2 [1:0] CK_PRIOR 2.
Selects which of the input clocks will be 2nd priority in the autoselection state
machine.
00: CKIN1 is 2nd priority.
01: CKIN2 is 2nd priority.
10: Reserved
11: Reserved
1:0 CK_PRIOR1 [1:0] CK_PRIOR 1.
Selects which of the input clocks will be 1st priority in the autoselection state
machine.
00: CKIN1 is 1st priority.
01: CKIN2 is 1st priority.
10: Reserved
11: Reserved

Register 2.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name BWSEL_REG [3:0] Reserved

Type R/W R

Reset value = 0100 0010

Bit Name Function

7:4 BWSEL_REG [3:0] BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See DSPLLsim for settings. After
BWSEL_REG is written with a new value, an ICAL is required for the change to
take effect.
3:0 Reserved Reserved.

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 Si5328

Register 3.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name CKSEL_REG [1:0] DHOLD SQ_ICAL Reserved

Type R/W R/W R/W R

Reset value = 0000 0101

Bit Name Function

7:6 CKSEL_REG [1:0] CKSEL_REG.
If the device is operating in register-based manual clock selection mode
(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input
clock will be the active input clock. If CKSEL_PIN = 1 and AUTOSEL_REG = 00,
the CS_CA input pin continues to control clock selection and CKSEL_REG is of no
consequence.
00: CKIN_1 selected.
01: CKIN_2 selected.
10: Reserved
11: Reserved
5 DHOLD DHOLD.
Forces the part into digital hold. This bit overrides all other manual and automatic
clock selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of
all of the input clocks.
4 SQ_ICAL SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (dis-
abled) during an internal calibration. See Table 9 on page 20.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
3:0 Reserved Reserved.

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Si5328

Register 4.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name AUTOSEL_REG [1:0] Reserved HIST_DEL [4:0]

Type R/W R R/W

Reset value = 0001 0010

Bit Name Function

7:6 AUTOSEL_REG [1:0] AUTOSEL_REG [1:0].
Selects method of input clock selection to be used.
00: Manual (either register or pin controlled, see CKSEL_PIN)
01: Automatic Non-Revertive
10: Automatic Revertive
11: Reserved
See the Si53xx Family Reference Manual for a detailed description.
5 Reserved Reserved.
4:0 HIST_DEL [4:0] HIST_DEL [4:0].
Selects amount of delay to be used in generating the history information used for
Digital Hold.
See the Si53xx Family Reference Manual for a detailed description.

Register 5.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name ICMOS [1:0] Reserved

Type R/W R

Reset value = 1110 1101

Bit Name Function

7:6 ICMOS [1:0] ICMOS [1:0].
When the output buffer is set to CMOS mode, these bits determine the output buffer drive
strength. The first number below refers to 3.3 V operation; the second to 2.5 V operation.
These values assume CKOUT+ is tied to CKOUT–.
00: 8 mA/5 mA
01: 16 mA/10 mA
10: 24 mA/15 mA
11: 32 mA/20 mA
5:0 Reserved Reserved.

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 Si5328

Register 6.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved SLEEP SFOUT2_REG [2:0] SFOUT1_REG [2:0]

Type R R/W R/W R/W

Reset value = 0010 1101

Bit Name Function

7 Reserved Reserved.
6 SLEEP SLEEP.
In sleep mode, all clock outputs are disabled and the maximum amount of internal
circuitry is powered down to reduce power dissipation and noise generation. This
bit overrides the SFOUTn_REG[2:0] output signal format settings.
0: Normal operation
1: Sleep mode
5:3 SFOUT2_REG [2:0] SFOUT2_REG [2:0].
Controls output signal format and disable for CKOUT2 output buffer.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
2:0 SFOUT1_REG [2:0] SFOUT1_REG [2:0].
Controls output signal format and disable for CKOUT1 output buffer.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL
111: LVDS

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Si5328

Register 7.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved FOSREFSEL [2:0]

Type R R/W

Reset value = 0010 1010

Bit Name Function

7:3 Reserved. Reserved.
2:0 FOSREFSEL [2:0] FOSREFSEL [2:0].
Selects which input clock is used as the reference frequency for frequency offset
(FOS) alarms.
000: XA/XB (External reference)
001: CKIN1
010: CKIN2
011: Reserved
100: Reserved
101: Reserved
110: Reserved
111: Reserved

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 Si5328

Register 8.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name HLOG_2[1:0] HLOG_1[1:0] Reserved

Type R/W R/W R

Reset value = 0000 0000

Bit Name Function

7:6 HLOG_2 [1:0] HLOG_2 [1:0].
00: Normal operation
01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT2 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
5:4 HLOG_1 [1:0].
00: Normal operation
01: Holds CKOUT1 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT1 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
3:0 Reserved Reserved.

Register 9.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name HIST_AVG [4:0] Reserved

Type R/W R R R

Reset value = 1100 0000

Bit Name Function

7:3 HIST_AVG [4:0] HIST_AVG [4:0].
Selects amount of averaging time to be used in generating the history information for
Digital Hold.
See the Si53xx Family Reference Manual for a detailed description
2:0 Reserved Reserved.

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Si5328

Register 10.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved DSBL2_REG DSBL1_REG Reserved Reserved

Type R R/W R/W R R

Reset value = 0000 0000

Bit Name Function

7:4 Reserved Reserved.
3 DSBL2_REG DSBL2_REG.
This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is
selected, the N2_LS output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
2 DSBL1_REG DSBL1_REG.
This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is
selected, the N1_LS output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
1:0 Reserved Reserved.

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 Si5328

Register 11.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved PD_CK2 PD_CK1

Type R R/W R/W

Reset value = 0100 0000

Bit Name Function

7:2 Reserved Reserved.
1 PD_CK2 PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
0 PD_CK1 PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled

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Si5328

Register 19.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name FOS_EN FOS_THR [1:0] VALTIME [1:0] LOCKT [2:0]

Type R/W R/W R/W R/W

Reset value = 0010 1100

Bit Name Function

7 FOS_EN FOS_EN.
Frequency Offset Enable globally disables FOS. See the individual FOS enables
(FOSX_EN, register 139).
0: FOS disable
1: FOS enabled by FOSx_EN
6:5 FOS_THR [1:0] FOS_THR [1:0].
Frequency Offset at which FOS is declared (relative to the selected FOS reference):
00: ± 11 to 12 ppm (Stratum 3/3E compliant, with a Stratum 3/3E used for REFCLK
01: ± 48 to 49 ppm (SMC)
10: ± 30 ppm (SONET Minimum Clock (SMC), with a Stratum 3/3E used for REFCLK.
11: ± 200 ppm
4:3 VALTIME [1:0] VALTIME [1:0].
Sets amount of time for input clock to be valid before the associated alarm is
removed.
00: 2 ms
01: 100 ms
10: 200 ms
11: 13 seconds
2:0 LOCKT [2:0] LOCKT [2:0].
Sets retrigger interval for one shot monitoring phase detector output. One shot is trig-
gered by phase slip in DSPLL. Refer to the Si53xx Family Reference Manual for more
details.
000: 106 ms
001: 53 ms
010: 26.5 ms
011: 13.3 ms
100: 6.6 ms
101: 3.3 ms
110: 1.66 ms
111: .833 ms

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 Si5328

Register 20.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved CK2_BAD_PIN CK1_BAD_PIN LOL_PIN INT_PIN

Type R R/W R/W R/W R/W

Reset value = 0011 1110

Bit Name Function

7:4 Reserved Reserved.
3 CK2_BAD_PIN CK2_BAD_PIN.
The CK2_BAD status can be reflected on the C2B output pin.
0: C2B output pin tristated
1: C2B status reflected to output pin
2 CK1_BAD_PIN CK1_BAD_PIN.
Either LOS1 or INT (see INT_PIN) status can be reflected on the INT_C1B output pin.
0: INT_C1B output pin tristated
1: LOS1 or INT (see INT_PIN) status reflected to output pin
1 LOL_PIN LOL_PIN.
The LOL_INT status bit can be reflected on the LOL output pin.
0: LOL output pin tristated
1: LOL_INT status reflected to output pin
0 INT_PIN INT_PIN.
Reflects the interrupt status on the INT_C1B output pin.
0: Interrupt status not displayed on INT_C1B output pin. Instead, the INT_C1B pin
indicates when CKIN1 is bad. If CK1_BAD_PIN = 0, INT_C1B output pin is tristated.
1: Interrupt status reflected to output pin.

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Si5328

Register 21.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved Reserved CK1_ACTV_PIN CKSEL_ PIN

Type R Force 1 R R R R R/W R/W

Reset value = 1111 1111

Bit Name Function

7:2 Reserved Reserved.
1 CK1_ACTV_PIN CK1_ACTV_PIN.
The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the
CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin
controlled clock selection is not being used. (See CKSEL_PIN)
0: CS_CA output pin tristated.
1: Clock Active status reflected to output pin.
0 CKSEL_PIN CKSEL_PIN.
If manual clock selection is being used, clock selection can be controlled via the
CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when
AUTOSEL_REG = Manual.
0: CS_CA pin is ignored. CKSEL_REG[1:0] register bits control clock selection.
1: CS_CA input pin controls clock selection.

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 Si5328

Register 22.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved CK_ACTV_POL CK_BAD_ POL LOL_POL INT_POL

Type R R/W R/W R/W R/W

Reset value = 1101 1111

Bit Name Function

7:4 Reserved Reserved.
3 CK_ACTV_ POL CK_ACTV_POL.
Sets the active polarity for the CS_CA signals when reflected on an output pin.
0: Active low
1: Active high
2 CK_BAD_ POL CK_BAD_POL.
Sets the active polarity for the INT_C1B and C2B signals when reflected on output
pins.
0: Active low
1: Active high
1 LOL_POL LOL_POL.
Sets the active polarity for the LOL status when reflected on an output pin.
0: Active low
1: Active high
0 INT_POL INT_POL.
Sets the active polarity for the interrupt status when reflected on the INT_C1B output
pin.
0: Active low
1: Active high

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Si5328

Register 23.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved LOS2_ MSK LOS1_ MSK LOSX_ MSK

Type R R/W R/W R/W

Reset value = 0001 1111

Bit Name Function

7:3 Reserved Reserved.
2 LOS2_MSK LOS2_MSK.
Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS2_FLG register.
0: LOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: LOS2_FLG ignored in generating interrupt output.
1 LOS1_MSK LOS1_MSK.
Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOS1_FLG register.
0: LOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: LOS1_FLG ignored in generating interrupt output.
0 LOSX_MSK LOSX_MSK.
Determines if a LOS on XA/XB(LOSX_FLG) is used in the generation of an interrupt.
Writes to this register do not change the value held in the LOSX_FLG register.
0: LOSX alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: LOSX_FLG ignored in generating interrupt output.

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 Si5328

Register 24.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved FOS2_MSK FOS1_MSK LOL_MSK

Type R R/W R/W R/W

Reset value = 0011 1111

Bit Name Function

7:3 Reserved Reserved.
2 FOS2_MSK FOS2_MSK.
Determines if the FOS2_FLG is used in the generation of an interrupt. Writes to this reg-
ister do not change the value held in the FOS2_FLG register.
0: FOS2 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: FOS2_FLG ignored in generating interrupt output.
1 FOS1_MSK FOS1_MSK.
Determines if the FOS1_FLG is used in the generation of an interrupt. Writes to this reg-
ister do not change the value held in the FOS1_FLG register.
0: FOS1 alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: FOS1_FLG ignored in generating interrupt output.
0 LOL_MSK LOL_MSK.
Determines if the LOL_FLG is used in the generation of an interrupt. Writes to this regis-
ter do not change the value held in the LOL_FLG register.
0: LOL alarm triggers active interrupt on INT_C1B output (if INT_PIN=1).
1: LOL_FLG ignored in generating interrupt output.

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Si5328

Register 25.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name N1_HS [2:0] Reserved

Type R/W R

Reset value = 0010 0000

Bit Name Function

7:5 N1_HS [2:0] N1_HS [2:0].
Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 2) low-speed divider.
000: N1 = 4
001: N1 = 5
010: N1 = 6
011: N1 = 7
100: N1 = 8
101: N1 = 9
110: N1 = 10
111: N1 = 11
4:0 Reserved Reserved.

Register 31.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved NC1_LS [19:16]

Type R R/W

Reset value = 0000 0000

Bit Name Function

7:4 Reserved Reserved.
3:0 NC1_LS [19:16] NC1_LS [19:16].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or
odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111=220
Valid divider values=[1, 2, 4, 6, ..., 220]

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 Si5328

Register 32.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name NC1_LS [15:8]

Type R/W

Reset value = 0000 0000

Bit Name Function

7:0 NC1_LS [15:8] NC1_LS [15:8].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or
odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111=220
Valid divider values=[1, 2, 4, 6, ..., 220]

Register 33.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name NC1_LS [7:0]

Type R/W

Reset value = 0011 0001

Bit Name Function

7:0 NC1_LS [19:0] NC1_LS [7:0].
Sets value for N1 low-speed divider, which drives CKOUT1 output. Must be 0 or
odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111=220
Valid divider values=[1, 2, 4, 6, ..., 220]

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Si5328

Register 34.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved NC2_LS [19:16]

Type R R/W

Reset value = 0000 0000

Bit Name Function

7:4 Reserved Reserved.
3:0 NC2_LS [19:16] NC2_LS [19:16].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.
00000000000000000000=1
00000000000000000001=2
00000000000000000011=4
00000000000000000101=6
...
11111111111111111111=220
Valid divider values=[1, 2, 4, 6, ..., 220]

Register 35.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name NC2_LS [15:8]

Type R/W

Reset value = 0000 0000

Bit Name Function

7:0 NC2_LS [15:8] NC2_LS [15:8].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or
odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111=220
Valid divider values=[1, 2, 4, 6, ..., 220]

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 Si5328

Register 36.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name NC2_LS [7:0]

Type R/W

Reset value = 0011 0001

Bit Name Function

7:0 NC2_LS [7:0] NC2_LS [7:0].
Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must be 0 or odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111=220
Valid divider values=[1, 2, 4, 6, ..., 220]

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Si5328

Register 40.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name N2_HS [2:0] Reserved N2_LS [19:16]

Type R/W R R/W

Reset value = 1100 0000

Bit Name Function

7:5 N2_HS [2:0] N2_HS [2:0].
Sets value for N2 high speed divider, which drives N2LS low-speed divider.
000: 4
001: 5
010: 6
011: 7
100: 8
101: 9
110: 10
111: 11
4 Reserved Reserved.
3:0 N2_LS [19:16] N2_LS [19:16].
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [2, 4, 6, ..., 220]

42 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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 Si5328

Register 41.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name N2_LS [15:8]

Type R/W

Reset value = 0000 0000

Bit Name Function

7:0 N2_LS [15:8] N2_LS [15:8].
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [2, 4, 6, ..., 220]

Register 42.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name N2_LS [7:0]

Type R/W

Reset value = 1111 1001

Bit Name Function

7:0 N2_LS [7:0] N2_LS [7:0].
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 220
Valid divider values = [2, 4, 6, ..., 220]

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Si5328

Register 43.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved N31 [18:16]

Type R R/W

Reset value = 0000 0000

Bit Name Function

7:3 Reserved Reserved.
2:0 N31 [18:16] N31 [18:16].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values=[1, 2, 3, ..., 219]

Register 44.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name N31_[15:8]

Type R/W

Reset value = 0000 0000

Bit Name Function

7:0 N31_[15:8] N31_[15:8].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values=[1, 2, 3, ..., 219]

44 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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 Si5328

Register 45.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name N31_[7:0]

Type R/W

Reset value = 0000 1001

Bit Name Function

7:0 N31_[7:0 N31_[7:0].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values=[1, 2, 3, ..., 219]

Register 46.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved N32_[18:16]

Type R R/W

Reset value = 0000 0000

Bit Name Function

7:3 Reserved Reserved.
2:0 N32_[18:16] N32_[18:16].
Sets value for input divider for CKIN2.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values=[1, 2, 3, ..., 219]

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Si5328

Register 47.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name N32_[15:8]

Type R/W

Reset value = 0000 0000

Bit Name Function

7:0 N32_[15:8] N32_[15:8].
Sets value for input divider for CKIN2.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values=[1, 2, 3, ..., 219]

Register 48.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name N32_[7:0]

Type R/W

Reset value = 0000 1001

Bit Name Function

7:0 N32_[7:0] N32_[7:0].
Sets value for input divider for CKIN1.
0000000000000000000 = 1
0000000000000000001 = 2
0000000000000000010 = 3
...
1111111111111111111 = 219
Valid divider values=[1, 2, 3, ..., 219]

46 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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 Si5328

Register 55.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved CLKIN2RATE_[2:0] CLKIN1RATE[2:0]

Type R R/W R/W

Reset value = 0000 0000

Bit Name Function

7:6 Reserved Reserved.
5:3 CLKIN2RATE[2:0] CLKIN2RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
010: 50–105 MHz
011: 95–215 MHz
100: 190–435 MHz
101: 375–710 MHz
110: Reserved
111: Reserved
2:0 CLKIN1RATE [2:0] CLKIN1RATE[2:0].
CKINn frequency selection for FOS alarm monitoring.
000: 10–27 MHz
001: 25–54 MHz
010: 50–105 MHz
011: 95–215 MHz
100: 190–435 MHz
101: 375–710 MHz
110: Reserved
111: Reserved

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Si5328

Register 128.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved CK2_ACTV_REG CK1_ACTV_REG

Type R R R

Reset value = 0010 0000

Bit Name Function

7:2 Reserved Reserved.
1 CK2_ACTV_REG CK2_ACTV_REG.
Indicates if CKIN2 is currently the active clock for the PLL input.
0: CKIN2 is not the active input clock. Either it is not selected or LOS2_INT is 1.
1: CKIN2 is the active input clock.
0 CK1_ACTV_REG CK1_ACTV_REG.
Indicates if CKIN1 is currently the active clock for the PLL input.
0: CKIN1 is not the active input clock. Either it is not selected or LOS1_INT is 1.
1: CKIN1 is the active input clock.

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 Si5328

Register 129.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved LOS2_INT LOS1_INT LOSX_INT

Type R R R R

Reset value = 0000 0110

Bit Name Function

7:3 Reserved Reserved.
2 LOS2_INT LOS2_INT.
Indicates the LOS status on CKIN2.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN2 input.
1 LOS1_INT LOS1_INT.
Indicates the LOS status on CKIN1.
0: Normal operation.
1: Internal loss-of-signal alarm on CKIN1 input.
0 LOSX_INT LOSX_INT.
Indicates the LOS status of the external reference on the XA/XB pins.
0: Normal operation.
1: Internal loss-of-signal alarm on XA/XB reference clock input.

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Si5328

Register 130.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved DIGHOLDVALID Reserved FOS2_INT FOS1_INT LOL_INT

Type R R R R R R

Reset value = 0000 0001

Bit Name Function

7 Reserved Reserved.
6 DIGHOLDVALID Digital Hold Valid.
Indicates if the digital hold circuit has enough samples of a valid clock to meet digital
hold specifications.
0: Indicates digital hold history registers have not been filled. The digital hold output
frequency may not meet specifications.
1: Indicates digital hold history registers have been filled. The digital hold output
frequency is valid.
5:3 Reserved Reserved.
2 FOS2_INT CKIN2 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN2 input.
1 FOS1_INT CKIN1 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN1 input.
0 LOL_INT PLL Loss of Lock Status.
0: PLL locked.
1: PLL unlocked.

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 Si5328

Register 131.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved LOS2_FLG LOS1_FLG LOSX_FLG

Type R R/W R/W R/W

Reset value = 0001 1111

Bit Name Function

7:3 Reserved Reserved.
2 LOS2_FLG CKIN2 Loss-of-Signal Flag.
0: Normal operation.
1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOS2_MSK bit. Flag cleared by writing 0 to
this bit.
1 LOS1_FLG CKIN1 Loss-of-Signal Flag.
0: Normal operation
1: Held version of LOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOS1_MSK bit. Flag cleared by writing 0 to
this bit.
0 LOSX_FLG External Reference (signal on pins XA/XB) Loss-of-Signal Flag.
0: Normal operation
1: Held version of LOSX_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOSX_MSK bit. Flag cleared by writing 0 to
this bit.

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Si5328

Register 132.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved FOS2_FLG FOS1_FLG LOL_FLG Reserved

Type R R/W R/W R/W R

Reset value = 0000 0010

Bit Name Function

7:4 Reserved Reserved.
3 FOS2_FLG CLKIN_2 Frequency Offset Flag.
0: Normal operation.
1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing 0 to
this bit.
2 FOS1_FLG CLKIN_1 Frequency Offset Flag.
0: Normal operation
1: Held version of FOS1_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by FOS1_MSK bit. Flag cleared by writing 0 to
this bit.
1 LOL_FLG PLL Loss of Lock Flag.
0: PLL locked
1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is
enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing 0 to
this bit.
0 Reserved Reserved.

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 Si5328

Register 134.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name PARTNUM_RO [11:4]

Type R

Reset value = 0000 0001

Bit Name Function

7:0 PARTNUM_RO [11:0] Device ID (1 of 2).
0000 0001 1100: Si5328

Register 135.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name PARTNUM_RO [3:0] REVID_RO [3:0]

Type R R

Reset value = 1100 0010

Bit Name Function

7:4 PARTNUM_RO [11:0] Device ID (2 of 2).
0000 0001 1100: Si5328
3:0 REVID_RO [3:0] Device Revision.
0010: Revision C
Others: Reserved

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Si5328

Register 136.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name RST_REG ICAL Reserved

Type R/W R/W R

Reset value = 0000 0000

Bit Name Function

7 RST_REG Internal Reset (Same as Pin Reset).
Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.
0: Normal operation.
1: Reset of all internal logic. Outputs disabled or tristated during reset.
6 ICAL Start an Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence. ICAL
is a self-clearing bit. Writing a “1” to this location initiates an ICAL. The calibration is com-
plete once the LOL alarm goes low.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-calibra-
tion, LOL will go low.
Notes:
1. A valid stable clock (within 100 ppm) must be present to begin ICAL.
2. If the input changes by more than 500 ppm, the part may do an autonomous ICAL.
3. See Table 10, “Register Locations Requiring ICAL,” on page 62 for register changes that
require an ICAL.
5:0 Reserved Reserved.

Register 137.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name FASTLOCK

Type R R R R R R R R/W

Reset value = 0000 0000

Bit Name Function

7:1 Reserved Do not modify.
0 FASTLOCK This bit must be set to 1 to enable FASTLOCK. This improves initial lock time by
dynamically changing the loop bandwidth.

54 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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 Si5328

Register 138.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved LOS2_EN[1:1] LOS1_EN [1:1]

Type R R/W R/W

Reset value = 0000 1111

Bit Name Function

7:2 Reserved Reserved.
1 LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).
Note: LOS2_EN is split between two registers.
00: Disable LOS monitoring
01: Reserved
10: Enable LOSA monitoring
11: Enable LOS monitoring
LOSA is a slower and less sensitive version of LOS. SEe the Si53xx Family Refer-
ence Manual for details.
0 LOS1_EN [1:0] Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring
01: Reserved
10: Enable LOSA monitoring
11: Enable LOS monitoring
LOSA is a slower and less sensitive version of LOS. See the Si53xx Family Refer-
ence Manual for details.

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 55
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Si5328

Register 139.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name Reserved LOS2_EN [0:0] LOS1_EN [0:0] Reserved FOS2_EN FOS1_EN

Type R R/W R/W R R/W R/W

Reset value = 1111 1111

Bit Name Function

7:6 Reserved Reserved.
5 LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2).
Note: LOS2_EN is split between two registers.
00: Disable LOS monitoring
01: Reserved
10: Enable LOSA monitoring
11: Enable LOS monitoring
LOSA is a slower and less sensitive version of LOS. See the Si53xx Family Refer-
ence Manual for details
4 LOS1_EN [1:0] Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2).
Note: LOS1_EN is split between two registers.
00: Disable LOS monitoring
01: Reserved
10: Enable LOSA monitoring
11: Enable LOS monitoring
LOSA is a slower and less sensitive version of LOS. See the Si53xx Family Refer-
ence Manual for details.
3:2 Reserved Reserved.
1 FOS2_EN Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring
1: Enable FOS monitoring
0 FOS1_EN Enables FOS on a Per Channel Basis.
0: Disable FOS monitoring
1: Enable FOS monitoring

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 Si5328

Register 142.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name INDEPENDENTSKEW1 [7:0]

Type R/W

Reset value = 0000 0000

Bit Name Function

7:0 INDEPEND-ENTSKEW1 [7:0] INDEPENDENTSKEW1.
Eight-bit field that represents a 2’s complement of the phase offset in
terms of clocks from the high speed output divider.

Register 143.

Bit D7 D6 D5 D4 D3 D2 D1 D0

Name INDEPENDENTSKEW2 [7:0]

Type R/W

Reset value = 0000 0000

Bit Name Function

7:0 INDEPEND-ENTSKEW2 [7:0] INDEPENDENTSKEW2.
Eight-bit field that represents a 2’s complement of the phase offset in
terms of clocks from the high speed output divider.

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Si5328
7. Pin Descriptions: Si5328

CKOUT1–
CKOUT1+
CKOUT2+
CKOUT2–
CMODE

VDD
GND
NC

NC
36 35 34 33 32 31 30 29 28
RST 1 27 SDI
NC 2 26 A2_SS
INT_C1B 3 25 A1
C2B 4 24 A0
VDD 5
GND 23 SDA_SDO
XA 6
Pad 22 SCL
XB 7 21 CS_CA
GND 8 20 NC
NC 9 19 NC
10 11 12 13 14 15 16 17 18
NC
RATE0

CKIN2–

RATE1

CKIN1–
LOL
VDD

CKIN2+

CKIN1+

Pin # Pin Name I/O Signal Level Description

1 RST I LVCMOS External Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state and forces the device reg-
isters to their default value. Clock outputs are tristated during reset.
The part must be programmed after a reset or power on to get a
clock output. See the Si53xx Family Reference Manual for details.
This pin has a weak pull-up.
2, 9, 14, NC — — No Connection.
19, 20, 30, Leave floating. Make no external connections to this pin for normal
33 operation.
3 INT_C1B O LVCMOS Interrupt/CKIN1 Invalid Indicator.
This pin functions as a device interrupt output or an alarm output for
CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The
pin functions as a maskable interrupt output with active polarity con-
trolled by the INT_POL register bit.
If used as an alarm output, the pin functions as a LOS (and option-
ally FOS) alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and
INT_PIN = 0.
0 = CKIN1 present
1 = LOS (FOS) on CKIN1
The active polarity is controlled by CK_BAD_POL. If no function is
selected, the pin tristates.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.

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Pin # Pin Name I/O Signal Level Description
4 C2B O LVCMOS CKIN2 Invalid Indicator.
This pin functions as a LOS (and optionally FOS) alarm indicator for
CKIN2 if CK2_BAD_PIN = 1.
0 = CKIN2 present
1 = LOS (FOS) on CKIN2
The active polarity can be changed by CK_BAD_POL. If
CK2_BAD_PIN = 0, the pin tristates.
5, 10, 32 VDD VDD Supply Supply.
The device operates from a 2.5 or 3.3 V supply. Bypass capacitors
should be associated with the following VDD pins:
5 0.1 µF
10 0.1 µF
32 0.1 µF
A 1.0 µF should also be placed as close to the device as is practical.
7 XB I Analog Reference Clock.
6 XA A TCXO or OCXO should be connected to these pins. Refer to the
Si53xx Family Reference Manual for interfacing to the external ref-
erence. External reference must be from a high-quality clock source
(TCXO, OCXO). Frequency of crystal or external clock is set by
RATE[1:0] pins.
8, 31 GND GND Supply Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
11 RATE0 I 3-Level Reference Clock Rate.
15 RATE1 Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Si53xx
Family Reference Manual for settings. These pins have both a weak
pull-up and a weak pull-down; they default to M.
L setting corresponds to ground.
M setting corresponds to VDD/2.
H setting corresponds to VDD.
Some designs may require an external resistor voltage divider when
driven by an active device that will tristate.
16 CKIN1+ I Multi Clock Input 1.
17 CKIN1– Differential input clock. This input can also be driven with a single-
ended signal.
12 CKIN2+ I Multi Clock Input 2.
13 CKIN2– Differential input clock. This input can also be driven with a single-
ended signal.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.

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Si5328
Pin # Pin Name I/O Signal Level Description
18 LOL O LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN register bit is set to 1.
0 = PLL locked
1 = PLL unlocked
If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by
the LOL_POL bit. The PLL lock status will always be reflected in the
LOL_INT read only register bit.
21 CS_CA I/O LVCMOS Input Clock Select/Active Clock Indicator.
Input: In manual clock selection mode, this pin functions as the
manual input clock selector if the CKSEL_PIN is set to 1.
0 = Select CKIN1
1 = Select CKIN2
If CKSEL_PIN = 0, the CKSEL_REG register bit controls this func-
tion and this input tristates. If configured for input, must be tied high
or low.
Output: In automatic clock selection mode, this pin indicates which
of the two input clocks is currently the active clock. If alarms exist on
both clocks, CK_ACTV will indicate the last active clock that was
used before entering the digital hold state. The CK_ACTV_PIN reg-
ister bit must be set to 1 to reflect the active clock status to the
CK_ACTV output pin.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status will
always be reflected in the CK_ACTV_REG read only register bit.
22 SCL I LVCMOS Serial Clock.
This pin functions as the serial clock input for both SPI and I2C
modes.
This pin has a weak pull-down.
23 SDA_SDO I/O LVCMOS Serial Data.
In I2C control mode (CMODE = 0), this pin functions as the bidirec-
tional serial data port.
In SPI control mode (CMODE = 1), this pin functions as the serial
data output.
25 A1 I LVCMOS Serial Port Address.
24 A0 In I2C control mode (CMODE = 0), these pins function as hardware
controlled address bits. The I2C address is 1101 [A2] [A1] [A0].
In SPI control mode (CMODE = 1), these pins are ignored.
These pins have a weak pull-down.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.

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 Si5328
Pin # Pin Name I/O Signal Level Description
26 A2_SS I LVCMOS Serial Port Address/Slave Select.
In I2C control mode (CMODE = 0), this pin functions as a hardware
controlled address bit [A2].
In SPI control mode (CMODE = 1), this pin functions as the slave
select input.
This pin has a weak pull-down.
27 SDI I LVCMOS Serial Data In.
In I2C control mode (CMODE = 0), this pin is ignored.
In SPI control mode (CMODE = 1), this pin functions as the serial
data input.
This pin has a weak pull-down.
29 CKOUT1– O Multi Output Clock 1.
28 CKOUT1+ Differential output clock with a frequency range of 8 kHz to
808 MHz. Output signal format is selected by SFOUT1_REG regis-
ter bits. Output is differential for LVPECL, LVDS, and CML compati-
ble modes. For CMOS format, both output pins drive identical
single-ended clock outputs.
34 CKOUT2– O Multi Output Clock 2.
35 CKOUT2+ Differential output clock with a frequency range of 8 kHz to
808 MHz. Output signal format is selected by SFOUT2_REG regis-
ter bits. Output is differential for LVPECL, LVDS, and CML compati-
ble modes. For CMOS format, both output pins drive identical
single-ended clock outputs.
36 CMODE I LVCMOS Control Mode.
Selects I2C or SPI control mode.
0 = I2C Control Mode
1 = SPI Control Mode
This pin must not be NC. Tie either high or low.
See the Si53xx Family Reference Manual for details on I2C or SPI
operation.
Ground Pad.
GND PAD GND GND Supply The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.

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Si5328
Table 10 lists all of the register locations that should be followed by an ICAL after their contents are changed.

Table 10. Register Locations Requiring ICAL

Addr Register
0 BYPASS_REG
0 CKOUT_ALWAYS_ON
1 CK_PRIOR2
1 CK_PRIOR1
2 BWSEL_REG
4 HIST_DEL
5 ICMOS
7 FOSREFSEL
9 HIST_AVG
10 DSBL2_REG
10 DSBL1_REG
11 PD_CK2
11 PD_CK1
19 FOS_EN
19 FOS_THR
19 VALTIME
19 LOCKT
25 N1_HS
31 NC1_LS
34 NC2_LS
40 N2_HS
40 N2_LS
43 N31
46 N32
55 CLKIN2RATE
55 CLKIN1RATE

Table 11. Si5328 Pull up/Pull down

Pin # Si5328 Pull up/Pull down
1 RST U
11 RATE0 U, D
15 RATE1 U, D
21 CS_CA U, D
22 SCL D
24 A0 D
25 A1 D
26 A2_SS D
27 SDI D
36 CMODE U, D

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 Si5328
8. Ordering Guide

Ordering Part Output Clock Frequency Package ROHS6, Temperature Range

Number Range Pb-Free

Si5328B-C-GM 8 kHz–808 MHz 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C

Si5328C-C-GM 8 kHz–346 MHz 36-Lead 6 x 6 mm QFN Yes –40 to 85 °C
Si5328-EVB 8 kHz–808 MHz Evaluation Board — –40 to 85 °C
Note: Add an R at the end of the device to denote tape and reel options.

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Si5328
9. Package Outline: 36-Pin QFN
Figure 7 illustrates the package details for the Si5328. Table 12 lists the values for the dimensions shown in the
illustration.

Figure 7. 36-Pin Quad Flat No-lead (QFN)

Table 12. Package Dimensions

Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A 0.80 0.85 0.90 L 0.50 0.60 0.70
A1 0.00 0.02 0.05  — — 12º
b 0.18 0.25 0.30 aaa — — 0.10
D 6.00 BSC bbb — — 0.10
D2 3.95 4.10 4.25 ccc — — 0.08
e 0.50 BSC ddd — — 0.10
E 6.00 BSC eee — — 0.05
E2 3.95 4.10 4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.

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 Si5328
10. Recommended PCB Layout

Figure 8. PCB Land Pattern Diagram

Figure 9. Ground Pad Recommended Layout

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Si5328

Table 13. PCB Land Pattern Dimensions

Dimension MIN MAX
e 0.50 BSC.
E 5.42 REF.
D 5.42 REF.
E2 4.00 4.20
D2 4.00 4.20
GE 4.53 —
GD 4.53 —
X — 0.28
Y 0.89 REF.
ZE — 6.31
ZD — 6.31
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut, and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
9. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.

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 Si5328
11. Si5328 Device Top Mark

Mark Method: Laser

Font Size: 0.80 mm

Right-Justified
Line 1 Marking: Si5328Q Customer Part Number
Q = Speed Code: C
See “8.Ordering Guide” for options
Line 2 Marking: C-GM C = Product Revision
G = Temperature Range –40 to 85 °C (RoHS6)
M = QFN Package
Line 3 Marking: YYWWRF YY = Year
WW = Work Week
R = Die Revision
F = Internal code
Assigned by the Assembly House. Corresponds to the year
and work week of the mold date.
Line 4 Marking: Pin 1 Identifier Circle = 0.75 mm Diameter
Lower-Left Justified
XXXX Internal Code

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Si5328
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 1.0
 Removed Vdd of 1.8 V.
 Updated lock and settling time specs.
 Added B speed grade with 808 MHz output
frequency.

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 Si5328
NOTES:

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