Extending a Traditional VIP to
Solve PHY Verification Challenges
Amit Tanwar and Manoj Manu,
Questa VIP Engineering
© Accellera Systems Initiative 1
Outline
• Overview
– VIP
– PHY
• Verification Environment
• Verification Stages
• Initial Challenges
• Verification Challenges
• Conclusion
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Overview - VIP
• Verification IP – Definition?
– Kind of S/W that reduces the pain of Verification Engineer
• VIP quality metrics
– Easy hook-up
• Connection A complex design (like PCIE)
• Configuration needs to serves 1-5 different
configuration whereas a VIP
– Stimulus needs to serve 100 times
– Assertions
– Coverage
– Test-suit (compliance, test plan)
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Overview – VIP (Cont..)
• Example – PCI Express Configurations
LANE X1 X2 X4 X8 X16 5
INTERFACE Serial PIPE-8 PIPE-16 PIPE-32 4
VERSION 1.0 2.0 3.0 4.0 4
PORT RC EP 2
PIPE NODE MAC PHY 2
LANE CFG Straight Reverse 2
Other Scramb- Polarity Up Skew 4
ling Config
Total >500
Combinations
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Overview - PHY
• PHY - A physical layer of serial bus protocol
• PCI Express, USB, and SATA shares the common PHY
MAC MAC
PHY PHY
(PCIE/USB/SATA) (PCIE/USB/SATA)
• SSIC, MPCIe, and LLI shares the common MPHY
Protocol Stack Protocol Stack
MPHY MPHY
(SSIC/MPCIe/LLI) (SSIC/MPCIe/LLI)
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Overview – PHY (Cont..)
• PHY
– Functionality mainly in terms of PCI Express and USB
• Various serial data transmission rates
• Clock and data recovery
• Encode/decode and error indications
• Receiver detection
• Low frequency periodic signaling (LFPS) transmission
• Multi-lane de-skew
– Need of a PHY verification kit
• A typical VIP needs to focus on >500 configurations
• PHY needs a special VIP which completely focus on PHY related
aspects and reduces the verification cycle
© Accellera Systems Initiative 6
Verification Environment
• Host on serial I/F, Device on PIPE I/F
Host VIP Device VIP
PHY
MAC PHY DUT MAC
SERIAL PIPE
• Device on PIPE I/F, Host on serial I/F
Host VIP Device VIP
PHY
MAC DUT PHY MAC
PIPE SERIAL
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Verification Environment (Cont..)
• Dual PHY
Host VIP Device VIP
PHY PHY
MAC DUT DUT MAC
PIPE SERIAL PIPE
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Verification Stages
• Initial Stage
– Pin connection
– Configuration
– Link Up and First Transaction
• Verification Stage
– Test Plan
– Test Case
– Test Run
– Debug
• Regression Stage
– Regression Environment
– Coverage Metrics
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Initial Challenges
• Pin Connections byte63 byte62 byte3 byte2 byte1 byte0
– 4 lanes with 16 bit data 1st byte of second lane or
2nd byte of first lane ??
– Change in Signal width across version
– Shared/Unshared signals across lanes V4.3 V3.0
– Clock Connection
• Test bench driven or PHY generated clock
• Leads to no connection or multiple driver
– Reset
• Always High or Low??
• Too long or short durations
© Accellera Systems Initiative 10
Initial Challenges (Cont..)
• Configurations
– Verification kit will enable engineers to directly focus on
configuration issues such as
• Scrambler enabling/disabling
MAC Serial
(Enabled for PHY Device
Scrambling) DUT
• Loopback master settings in loopback MAC
PHY
Serial
DUT
• LTSSM timers
(Disabled for Device
PIPE Interface
Scrambling) Serial Interface
(Enabled for
Scrambling)
(Scrambled Data) (Scrambled Data)
– Match as per DUT
PIPE Interface Serial Interface
– Downscale for faster simulations (Unscrambled Data) (Scrambled Data)
• Speed change configuration
• Initial link up setting in PIPE width change scenarios
– Can save a lot of time
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Initial Challenges (Cont..)
• Link Up and first transaction
– Various issues during link up like
• Receiver detection not completing
– Multiple receiver detection required
– No Response due to reset
• No Response to power down change
• Incorrect TxElecIdle/RxElecIdle timings
• Incorrect Co-efficient values during first equalization process
• No speed change due to incorrect rate signals
– Need some kind of debug messages to quickly resolve
these initial hiccups
© Accellera Systems Initiative 12
Verification Challenges
• Test Planning
– Traditional VIP provides a test suite for all layers
• Can physical layer test suite be extracted?? Yes
• Is this sufficient for PHY Verification?? No
– For Comprehensive verification it should exercise cases like:
• Disparity/Encoding Errors
• Loopback signaling
• Frequency compensation
• Receiver underflow/overflow
• Polarity inversions
• Low states entry and exits
– Ready-to-run test cases to cover corner cases will reduce the
verification time and ensure quality testing
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Verification Challenges (Cont..)
• Robust Regression Environment
– Independent design compilation
– Independent test bench compilation
– Parallelism in running test
– Failures can be easily checked and reproduced
– Test association with log/waveform file names
– Capability to save individual test coverage data
• Coverage Metrics
– Required to track verification objectives
– Simulator switches for code coverage
– Covergroups for functional coverage
– Capability to map testplan (XML or some other format) with
covergroups
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Conclusion
• Comprehensive PHY verification with traditional VIP
solution takes more time than expected
• Extending a VIP for PHY verification will
– Allow complete focus on PHY verification
– Cover all stages from Initial to Regression
– Reduce verification cycles
• Link Up
– Traditional VIP: 2-3 weeks
– With this concept: 1-3 days
• Verification
– One can achieve 70 % of verification target in 3-4 weeks time
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Questions ?
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