HDL
(Hardware Description Language)
Presented by:
Ms.Sejal Rathod
Masters of Engineering,
Electronics & Communication
DIFFERENCE BETWEEN COMBINATIONAL AND SEQUENTIAL CIRCUITS
ASYNCHRONOUS INPUTS
PRESET CLEAR OUTPUT
0 0 NO CHANGE
JK,T ,D WILL RESPONSIBLE
0 1 Q=0
1 0 Q=1
1 1 X (DON’T CARE)
ASYNCHRONOUS INPUTS
PREDEFIND ATTRIBUTES IN VHDL AND VERILOG
In the Listing, rising_edge OR falling_edge (VHDL) and posedge
OR negedge (Verilog) are predefined words called attributes.
They represent the positive edge of the clock (clk). For VHDL, the
clk has to be in std_logic to use this attribute.
always @(posedge Clock)
always @(negedge Clock)
always @(posedge Clock or posedge Reset)
always @(posedge Clock or negedge Reset)
always @(negedge Clock or posedge Reset)
always @(negedge Clock or negedge Reset)
VHDL ATTRIBUTES FOR CLOCK
SR LATCH WITH NOR VERILOG CODE
module sr_latch(
input wire S, R;
output wire Q, Q_not);
assign Q = ~(R | Q_not);
assign Q_not = ~(S | Q);
endmodule
SR LATCH NOR VHDL
VHDL Description
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
SR NOR VHDL AND VERILOG
entity nor2 is IN STRUCTRUL STYLE
port (I1, I2 : in std_logic; O1 : out std_logic);
end nor2;
architecture nor2_0 of nor2 is Verilog Description
begin module SR_Latch (R, S, Q, Qbar);
O1 <= I1 nor I2; input R, S;
end nor2_0; output Q, Qbar;
library IEEE; nor (Qbar, S,Q);
use IEEE.STD_LOGIC_1164.ALL; nor (Q, R, Qbar);
entity SR_latch is endmodule
port (R, S : in std_logic;
Q, Qbar : buffer std_logic);
end SR_latch;
architecture SR_strc of SR_latch is
component nor2
port (I1, I2 : in std_logic; O1 : out std_logic);
end component;
begin
n1 : nor2 port map (S, Q, Qbar);
n2 : nor2 port map (R, Qbar, Q);
end SR_strc;
SR latch with NAND gate (VHDL AND VERILOG)
D Latch D Flip-Flop
S
D’ R
R
D S
SR Latch
CLK D Qn+1
0 X Qn
1 0 Reset
1 1 Set
VHDL Code for Behavioral Description of a D-Latch Using Signal-Assignment Statements
entity Dltch_sig is
port (d, E : in bit; Q : buffer bit; Qb : out bit);
--Q is declared as a buffer because it is an input/output signal;
end Dltch_sig;
architecture DL_sig of Dltch_sig is
begin
process (d, E) architecture DLCH_VAR of DLTCH_var is
begin begin
VAR : process (d, E)
if E = ‘1’ then variable temp1, temp2 : bit;
Q <= d; -- signal assignment begin
Qb <= not Q; -- signal assignment if E = ‘1’ then
temp1 := d; -- This is a variable assignment statement.
end if; temp2 := not temp1; -- This is a variable assignment statement.
end process; end if;
end DL_sig; Qb <= temp2; -- Value of temp2 is passed to Qb
Q <= temp1; -- Value of temp1 is passed to Q
end process VAR;
end DLCH_VAR;
LISTING 3.4 Verilog Code for Behavioral Description of a D-Latch
module D_latch (d, E, Q, Qb);
input d, E;
output Q, Qb;
reg Q, Qb;
always @ (d, E)
begin // Alternative syntax
if (E == 1) module D_latch (output reg Q,
begin
Q = d; input enable, D);
Qb = ~ Q; always @ (enable, D)
end
end if (enable) Q <= D;
endmodule // Same as: if (enable == 1)
endmodule
D latch with structural
`timescale 1ns/1ps
module D_latch (Q, Qb, D, enable);
output Q, Qb;
input D, enable;
wire T1, T2, T3; T1
nand (T1, D, enable);
not (T3, D);
nand (T2, T3, enable);
nand (Q, T1, Qb);
T3
nand (Qb, T2, Q);
T2
endmodule
D LATCH WITH DATA FLOW
module D_latch (Q, Qb, D, enable);
output Q, Qb;
input D, enable;
wire T1, T2, T3;
assign T1 = !(D && enable);
assign T3 = !(D);
assign T2 = !(T3 && enable);
assign Q = !(T1 && Qb);
assign Qb = !(T2 && Q);
endmodule
D FLIP FLOP IN VHDL
Rising edge DFF with asynchronous active high reset and type bit
D FLIP FLOP IN VERILOG
always @(posedge Clock)
always @(negedge Clock)
always @(posedge Clock or posedge Reset)
always @(posedge Clock or negedge Reset)
always @(negedge Clock or posedge Reset)
always @(negedge Clock or negedge Reset)
module dff (input d, module dff (input d,
input rstn, input rstn,
input clk, input clk,
output reg q); output reg q);
always @ (posedge clk or negedge rstn) always @ (posedge clk)
if (!rstn) if (!rstn)
q <= 0; q <= 0;
else else
q <= d; q <= d;
endmodule endmodule
CLK J K Qn+1
0 X X Storage
Mode
1 0 0 No Change
1 0 1 Reset
1 1 0 Set
1 1 1 Toggle
In the Listing, rising_edge (VHDL) and posedge
OR negedge (Verilog) are predefined words called
attributes. They represent the positive edge of
the clock (clk). If the positive edge is present, the
attribute yields to true. For VHDL, the clk has to
be in std_logic to use this attribute.
VHDL Description
library ieee; Verilog Description
use ieee.std_logic_1164.all; module JK_FF (JK, clk, q, qb);
entity JK_FF is input [1:0] JK;
port(JK : in bit_vector (1 downto 0); input clk;
clk : in std_logic; q, qb : out bit); output q, qb;
end JK_FF; reg q, qb;
architecture JK_BEH of JK_FF is always @ (posedge clk)
begin begin
P1 : process (clk) case (JK)
variable temp1, temp2 : bit; 2’d0 : q = q;
begin 2’d1 : q = 0;
if rising_edge (clk) then 2’d2 : q = 1;
case JK is 2’d3 : q =~ q;
when “01” => temp1 := ‘0’; endcase
when “10” => temp1 := ‘1’; qb =~ q;
when “00” => temp1 := temp1; end
when “11” => temp1 := not temp1; endmodule
end case;
q <= temp1;
temp2 := not temp1;
qb <= temp2;
end if;
end process P1;
end JK_BEH;
T FLIP FLOP VHDL
THANK YOU
