APL3528

Ultra-Low On-Resistance, 6A Dual Load Switch with Soft Start

Features General Description

• 20mΩ(Typical) On-resistance per Channel The APL3528 is an ultra-low on-resistance, dual power-
• 6A Continuous Current distribution switch with external soft start control. It inte-
grates two N-channel MOSFETs that can deliver 6A con-
• Soft Start Time Programmable by External
tinuous load current each.
Capacitor
The device integrates over-temperature protection. The
• Wide Input Voltage Range (VIN): 0.8V to 5.5V
over temperature protection function shuts down the N-
• Supply Voltage Range (VBIAS): 3V to 5.5V channel MOSFET power switch when the junction tem-
• Output Discharge when Switch Disabled perature rises beyond 160oC and will automatically turns
• Reverse Current Blocking when Switch Disabled on the power switch when the temperature drops by 40oC.
• Over-Temperature Protection The device is available in lead free TDFN2x3-14A
• Enable Input packages.

• Lead Free and Green Devices Available (RoHS

Compliant)

Applications Simplified Application Circuit

• Notebook VBIAS
• AIO PC BIAS

VIN1
VOUT1
Pin Configurations
VIN1 VOUT1

VIN2 APL3528
VIN2
APL3528
VOUT2 VOUT2
VIN1 1 14 VOUT1
VIN1 2 13 VOUT1 On EN1
EN1 3 12 SS1 Off
EN2
BIAS 4 11 GND
EN2 5 10 SS2 SS1 SS2 GND

VIN2 6 9 VOUT2
VIN2 7 8 VOUT2

TDFN2x3-14
(Top View)

= Exposed Pad

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.

Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Rev. A.3 - Apr., 2024
APL3528

Ordering and Marking Information

APL3528 Package Code
QB : TDFN2x3-14A
Assembly Material Operating Ambient Temperature Range
I : -40 to 85oC
Handling Code Handling Code
TemperatureRange TR : Tape & Reel
Assembly Material
Package Code G : Halogen and Lead Free Device

L 3528 XXXXX-Date Code

APL3528 QB: XXXXX

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant)and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).

Absolute Maximum Ratings (Note 1)

Symbol Parameter Rating Unit
VBIAS BAIS to GND Voltage -0.3 ~ 6 V
VIN1, VIN2 VIN1, VIN2 to GND Voltage -0.3 ~ 6 V
VOUT1, VOUT2 VOUT1, VOUT2 to GND Voltage -0.3 ~ 6 V
VEN1, VEN2 EN1, EN2 to GND Voltage -0.3 ~ 6 V
o
TJ Maximum Junction Temperature -40 ~ 150 C
o
TSTG Storage Temperature -65 ~ 150 C
o
TSDR Maximum Lead Soldering Temperature (10 Seconds) 260 C
Note 1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

Thermal Characteristics
Symbol Parameter Typical Value Unit

θJA
(Note 2) o
Junction-to-Ambient Resistance in Free Air 80 C/W

Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.

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Rev. A.3 - Apr., 2024
APL3528

Recommended Operating Conditions (Note 3)

Symbol Param eter Range Unit

VBIAS VBIAS In put Voltage (V BIAS>VIN) 3.0 ~ 5.5 V
VIN VIN Inp ut Voltage 0.8 ~ 5.5 V
VOUT Ou tpu t Curren t (Single Chan nel) 0~6
I OUT Maximum Pulsed S witch Curren t, P ulse<300µs, 1% Duty Cycle A
8
(Single Cha nnel)
o (Note4 )
PD Maximum Power Dissipation, T A=50 C 0.9 4 W
VIH EN/ENB Lo gic Hig h Inpu t Voltage 1.2 ~ 5.5 V
V IL EN/ENB Lo gic L ow Inpu t Voltage 0 ~ 0.4 V
o
TA Amb ient Temp erature -4 0 ~ 85 C
o
TJ Junction Tempera tu re -40 ~ 12 5 C

Note 3 : Refer to the typical application circuit.

Note 4 : Refer to the thermal consideration on page 14.

Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN1= VIN2= 0.8V~5.5V, VEN1= VEN2=VBIAS =5V and TA= -40~85oC.
Typical values are at TA=25oC.

APL35 28
Sym bol P ara met er Test Conditions Unit
Min. Typ. Max .

SUPPLY CURRENT
BIAS Suppl y Curren t (bo th
No load, VBIAS=5V =VEN1,2=5V - 20 30 µA
chan nels)
I BIAS
BIAS Suppl y Curren t (singl e
No load, VBIAS=5V, VEN1 =5V, VEN 2=0 V - 15 25 µA
chan nel)
BIAS Suppl y Curren t at
I SD No load, VBIAS=5V, VEN1 ,2 =0V - - 1 µA
Sh utd own
No load, VBIAS=5V, VEN1 ,2 =0V, VIN1 ,2=5V - 0.1 8 µA
No load, VBIAS=5V, VEN1 ,2 =0V, VIN1 ,2=3.3V - 0.1 3 µA
VIN Off-Sta te Supply Curren t
IOFF No load, VBIAS=5V, VEN1 ,2 =0V, VIN1 ,2=1.8V - 0.1 2 µA
(pe r ch anne l)

No load, VBIAS=5V, VEN1 ,2 =0V, VIN1 ,2=0.8V - 0.1 1 µA

Reverse Lea ka ge Curren t (pe r
VEN1 ,2 =0V, VIN1, 2=0V - 0.1 16 µA
chan nel)
UNDE R-VOLTAGE LOCKOUT (UVLO)
Rising BIAS UVLO Thre sh old V BIAS rising 2 2.3 2.6 V
BIAS UVL O Hyste resis - 0.1 - V
POWER SWITCH
o
IOUT =2 00mA, T J= 2 5 C,
VBIAS=5V - 20 23 mΩ
o Chann el 1
IOUT =2 00mA, T J= -4 0~1 25 C,
- - 27 mΩ
R DS(ON) Po we r S wi tch On Resista nce VBIAS=5V
o
IOUT =2 00mA, T J= 2 5 C,
- 20 23 mΩ
VBIAS=5V
Chann el 2
IOUT =2 00mA, T J= -4 0~1 25oC,
- - 27 mΩ
VBIAS=5V
VOUT Di scha rge Resistance VEN1 ,2 =0V, VO UT1 or VO UT2 force 1V - 1 50 - Ω

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Rev. A.3 - Apr., 2024
APL3528

Electrical Characteristics (Cont.)

Unless otherwise specified, these specifications apply over VIN1= VIN2= 0.8V~5.5V, VEN1= VEN2=VBIAS =5V and TA= -40~85oC.
Typical values are at TA=25oC.

APL35 28
Sym bol P ara met er Test Conditions Unit
Min. Typ. Max .

SOFT-START CONTROL PIN

VSS1,2=6V, VEN1, 2=0V, EN2=low, m easured at
SS Discharge Cur rent - 5 60 - µA
SS1 o r S S2
EN INPUT PIN
Input Logic High 1.2 - - V

Input Logic Low - - 0.4 V

Input Current - - 1 µA
OVERT-TEMPERATURE PROTECTION ( OTP)

Over-Te mperature Thre sh old T J rising - 1 50 - °C

Over-Te mperature Hyster esis - 30 - °C

Timing Chart

50% 50%
tR tF
VEN

tON tOFF
90% 90%

50% 50%
VOUT VOUT
10% 10%

tD

Figure 1. tON/tOFF, tR/tF Waveforms

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Rev. A.3 - Apr., 2024
APL3528

Typical Operating Characteristics

Quiescent Current vs. BIAS Supply Quiescent Current vs. BIAS Supply
Voltage (Both Channels) Voltage (Single Channel)
25 15
- 40 - 40
VBIAS=VIN VBIAS=VIN
25 25

Quiescent Current, IBIAS(µA)

Quiescent Current, IBIAS(µA)

21 85 13 85
125 125

17 11

13 9

9 7

5 5
3 3.5 4 4.5 5 5.5 3 3.5 4 4.5 5 5.5
BIAS Supply Voltage, VBIAS(V) BIAS Supply Voltage, VBIAS(V)

Shutdown Current vs. BIAS Supply Off-Stage Supply Current vs. VIN
Voltage (Both Channels) Supply Voltage (Single Channel)
0.5 14
- 40 - 40
VBIAS=5.5V
Off-Stage Supply Current, IOFF(µA)

VBIAS=VIN
25 12 25
0.4 85 85
Quiescent Current, ISD(µA)

125 10 125

0.3 8

6
0.2

4
0.1
2

0 0
3 3.5 4 4.5 5 5.5 3 3.5 4 4.5 5 5.5
BIAS Supply Voltage, VBIAS(V) VIN Supply Voltage, VIN(V)

Switch On Resistance vs. VIN Switch On Resistance vs. VIN

Supply Voltage Supply Voltage
- 40 VBIAS=5.5V - 40
Switch On Resistance, RDS(ON)(mΩ)

VBIAS=3 V
Switch On Resistance, RDS(ON)(m0 )

36 0 28 0
25 25
50 50
32 75 75
100 24 100
125 125
28

20
24

16
20

16 12
0.5 1 1.5 2 2.5 3 0.5 1.5 2.5 3.5 4.5 5.5
VIN Supply Voltage, VIN(V) VIN Supply Voltage, VIN(V)

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Rev. A.3 - Apr., 2024
APL3528

Typical Operating Characteristics (Cont.)

Switch On Resistance vs. VIN Switch On Resistance vs. Output

Supply Voltage Current
30 30

Switch On Resistance, RDS(ON)(mΩ)

T A=25 OC V BIAS=5V,VIN=5V,TA=25O C
Switch On Resistance, RDS(ON)(mΩ)

28 28

VBIAS=3.3V
26 26

24 24

VBIAS=5V
22 22

20 20
0 .5 1 .5 2.5 3.5 4.5 5.5 0 1 2 3 4 5 6
VIN Supply Voltage, VIN(V) Output Current, IOUT(A)

Turn On Delay Time vs. VIN Supply Turn On Delay Time vs. VIN Supply
Voltage Voltage
400 500
VBIAS=3V ,R L=10Ω - 40 V BIAS=5.5V,RL =10 Ω - 40
CSS =OPEN,C OUT =0.1uF 25 C SS=OPEN,COUT = 0.1 uF 25
350 450
Turn On Delay Time, tD(µs)

Turn On Delay Time, tD(µs)

85 85
125 125
300 400

250 350

200 300

150 250

100 200
0.8 1.2 1.6 2 2 .4 2.8 0 .5 1.5 2.5 3.5 4.5 5.5
VIN Supply Voltage, VIN(V) VIN Supply Voltage, VIN(V)

Turn On Time vs. VIN Supply Turn On Time vs . VIN Supply

Voltage Voltage
400 500
VBIAS=3V,RL =10 Ω - 40 VBIAS=5.5 V,R L =10Ω - 40
C SS=OPEN ,C OUT =0 .1uF 25 C SS=OPENC OUT=0.1uF 25
350 450
85 85
Turn On Time, tON(µs)
Turn On Time, tON(µs)

125 125
300 400

250 350

200 300

150 250

100 200
0.8 1.2 1.6 2 2.4 2.8 0.5 1.5 2.5 3.5 4.5 5.5
VIN Supply Voltage, VIN(V) VIN Supply Voltage, VIN(V)

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Rev. A.3 - Apr., 2024
APL3528

Typical Operating Characteristics (Cont.)

Falling Time vs . VIN Supply Falling Time vs . VIN Supply
Voltage Voltage
5 5
VBIAS=3 V,RL =10Ω - 40 VBIAS=5.5 V,R L=10Ω - 40
C SS=OPEN ,C OUT =0 .1uF 25 C SS=OPEN ,C OUT =0 .1uF 25
4 85 4 85

Falling Time, tF(µs)

125
Falling Time, tF(µs)

125

3 3

2 2

1 1

0 0
0.8 1.2 1.6 2 2.4 2 .8 0.5 1.5 2.5 3.5 4.5 5 .5
VIN Supply Voltage, V IN(V) VIN Supply Voltage, VIN(V)

Turn Off Time vs. VIN Supply Turn Off Time vs. VIN Supply
Voltage Voltage
8 8
VBIAS=3 V,R L=10Ω - 40 VBIAS=5.5V,R L=10Ω - 40
C SS=OPEN ,C OUT =0.1uF 25 CSS =OPEN,C OUT =0.1uF 25
85 85
Turn Off Time, tOFF(µs)
Turn Off Time, tOFF(µs)

6 6
125 125

4 4

2 2

0 0
0.8 1.2 1.6 2 2.4 2 .8 0.5 1 .5 2.5 3.5 4.5 5.5
VIN Supply Voltage, VIN(V) VIN Supply Voltage, V IN(V)

Rising Time vs. VIN Supply Voltage Rising Time vs. VIN Supply Voltage
VBIAS=3V,R L=10Ω - 40 VBIAS=5.5V,R L=10 Ω - 40
CSS=OPEN,C OUT=0.1uF 25 CSS=OPEN,C OUT=0.1uF 25
90 90
85 85
Rising Time, tR(µs)

Rising Time, tR(µs)

125 125

70 70

50 50

30 30
0 .8 1.2 1.6 2 2.4 2.8 0.5 1.5 2 .5 3 .5 4.5 5 .5
VIN Supply Voltage, VIN(V) VIN Supply Voltage, VIN(V)

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Rev. A.3 - Apr., 2024
APL3528

Typical Operating Characteristics (Cont.)

Rising Time vs. VBIAS Supply
Voltage
VIN=3V ,R L=10Ω - 40
CSS=OPEN,C OUT=0.1uF 25
110
85
Rising Time, tR(µs)

125

90

70

50
3 3.5 4 4 .5 5 5 .5
VBIAS Supply Voltage, VBIAS(V)

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Rev. A.3 - Apr., 2024
APL3528

Operating Waveforms

Enable Shutdown

EN EN
1 1

VOUT
VOUT
2 2

VBIAS=5V,VIN=0.8V VBIAS=5V,VIN=0.8V
COUT=0.1µF,CSS=1nF COUT=0.1µF,CSS=1nF
CH1:VEN,5V/Div, DC CH1:VEN,5V/Div, DC
CH2:VOUT,200mV/Div, DC CH2:VOUT,200mV/Div, DC
TIME:200µs/Div TIME:20µs/Div

Enable Shutdown

EN
EN
1 1

VOUT VOUT

2 2

VBIAS=5V,VIN=5V VBIAS=5V,VIN=5V
COUT=0.1µF,CSS=1nF COUT=0.1µF,CSS=1nF
CH1:VEN,5V/Div, DC CH1:VEN,5V/Div, DC
CH2:VOUT,2V/Div, DC CH2:VOUT,2V/Div, DC
TIME:500µs/Div TIME:10µs/Div

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Rev. A.3 - Apr., 2024
APL3528

Pin Description
PIN
FUNCTION
NO. NAME
1 VIN1
Power supply Input of switch 1. Connect this pin to an external DC supply.
2 VIN1
3 EN1 Enable input of switch 1. Logic high turns on switch 1. The EN1 pin cannot be left floating.
4 BIAS Bias voltage input pin for internal control circuitry.
5 EN2 Enable input of switch 2. Logic high turns on switch 2. The EN2 pin cannot be left floating.
6 VIN2
Power supply Input of switch 2. Connect this pin to an external DC supply.
7 VIN2
8 VOUT2
Switch 2 output.
9 VOUT2

Soft start control of switch 2. A capacitor from this pin to ground sets the VOUT2’s rise slew
10 SS2
rate.

11 GND Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
Soft start control of switch 1. A capacitor from this pin to ground sets the VOUT1’s rise slew
12 SS1
rate.
13 VOUT1
Switch 1 output.
14 VOUT1

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Rev. A.3 - Apr., 2024
APL3528

Block Diagram

Bulk
Select
VIN1 VOUT1

UVLO Charge
BIAS
Pump

SS1

Control OTP1
EN1 Logic
OTP2

EN2

Bulk
Select

VIN2 VOUT2

Charge
Pump

SS2

GND

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Rev. A.3 - Apr., 2024
APL3528

Typical Application Circuit

VBIAS
4
BIAS
C BIAS
0.1µF

V IN1 1, 2
VIN1 VOUT1 13 , 14
C IN1 C OUT1 C L1
1µF RLOAD 1
0.1µF 150µF
VIN2
APL3528
6, 7
VIN2
CIN2
1µF 8 ,9
VOUT2
C OUT2 CL 2 R LOAD2
3 0.1µF 150 µF
On EN1

Off 5
EN2

SS1 SS2 GND

12 10 11

C SS1 C SS2

Soft-Start Time (µs) 10% t o 90 %, V BIA S=5V, C L=0.1µF, CIN=1µF, RL =1 0Ω, Typical values are at TA =25 °C
C SS(pF)
VIN=5V VIN=3.3V VIN=1.8V VIN=1.5V VIN=1.2V VIN=1.05V V IN=0 .8V
0 10 0 80 61 59 52 50 45
220 50 1 352 227 202 1 71 15 7 13 2
330 71 0 490 310 270 2 23 211 15 6
470 1013 694 427 369 3 17 28 2 23 4
100 0 1949 1 339 795 688 5 82 52 8 43 2
220 0 4381 2 984 17 96 15 33 127 7 11 50 92 6
470 0 9825 6 601 39 51 34 16 277 0 2534 2039

1 0000 197 21 1349 6 78 71 67 37 560 4 5013 4086

Note: The table Contains soft-start time values measured on a typical device. The soft-start times shown are only valid for the power-
up sequence where VIN and VBIAS are already in steady state condition, and EN pin is asserted high.

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Rev. A.3 - Apr., 2024
APL3528

Function Description
VIN Under-voltage Lockout (UVLO)

A under-voltage lockout (UVLO) circuit monitors the VBIAS

pins voltage to prevent wrong logic controls. The UVLO
function initiates a soft-start process after the BIAS sup-
ply voltages exceed rising UVLO voltage threshold dur-
ing powering on.

Power Switch

The power switch is an N-channel MOSFET with a ultra-

low RDS(ON). When IC is in shutdown state (VEN1,2=0V), the
MOSFET prevents a reverse current flowing from the VOUT
back to VIN. When IC is in UVLO state, the internal para-
sitic diodes connected from VOUT to VIN will be forward
biased.

Soft-start

The APL3528 Provides an adjustable soft-start circuitry

to control rise rate of the output voltage and limit the cur-
rent surge during start-up. The soft-start time is set with a
capacitor from the SS pin to the ground.

Enable Control

The APL3528 has a dedicated enable pin (EN). A logic

low signal applied to this pin shuts down the output. Fol-
lowing a shutdown, a logic high signal re-enables the
output through initiation of a new soft-start cycle.

Over-Temperature Protection (OTP)

When the junction temperature exceeds 150oC, the inter-
nal thermal sense circuit turns off the power FET and
allows the device to cool down. When the device’s junc-
tion temperature cools by 30 oC, the internal thermal
sense circuit will enable the device, resulting in a pulsed
output during continuous thermal protection. Thermal pro-
tection is designed to protect the IC in the event of over
temperature conditions. For normal operation, the junc-
tion temperature cannot exceed TJ=+125oC.

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Rev. A.3 - Apr., 2024
APL3528

Application Information
Power Sequencing A bulk output capacitor, placed close to the load, is rec-
VBIAS ommended to support load transient current.

VIN1, VIN2 Soft-Start Capacitor

The soft-start capacitor on SS pin can reduce the inrush
VEN1, VEN2
current and overshoot of output voltage. The soft-start
VOUT1, VOUT2 time is set with a capacitor from the SS pin to the ground.

Thermal Consideration

VEN1, VEN2
The APL3528 maximum power dissipation depends on
the differences of the thermal resistance and tempera-
VOUT1, VOUT2 ture between junction and ambient air. The power dissi-
pation PD across the device is:
VIN1, VIN2
PD = (TJ - TA) / θJA
VBIAS where (TJ-TA) is the temperature difference between the
junction and ambient air. θJA is the thermal resistance
Figure 2. APL3528 Power Sequencing Diagram
between junction and ambient air. Assuming the TA=25°C
The APL3528 has a built-in reverse current blocking cir- and maximum TJ=150°C (typical thermal limit threshold),
cuit to prevent a reverse current flowing through the body the maximum power dissipation is calculated as:
diode of power switch from the VOUT back VIN pin when
PD(max)=(150-25)/80
power switch disabled. The reverse current blocking cir-
= 1.56(W)
cuit is not active before VBIAS is ready. When IC is in UVLO
state, the internal parasitic diodes of power switch con- For normal operation, do not exceed the maximum oper-
nected from VOUT to VIN will be forward biased. ating junction temperature of TJ = 125°C. The calculated
Otherwise, VOUT should not be higher than VBIAS, and power dissipation should be less than:
VBIAS must be higher than the voltage of any other input PD =(125-25)/80
pin, the reason is that the internal parasitic diodes con- = 1.25(W)....................................................TA=25oC
nected from VOUT to VBIAS will be forward biased. PD =(125-85)/80
Capacitor Selection = 0.5(W)......................................................TA=85oC
The APL3528 requires proper input capacitors to supply
current surge during stepping load transients to prevent
The power dissipation depends on operating ambient
the input voltage rail from dropping. Because the para-
temperature for fixed TJ=125oC and thermal resistance
sitic inductor from the voltage sources or other bulk ca-
θJA. For APL3528 packages, the Figure 3~4 of derating
pacitors to the VIN pin limit the slew rate of the surge
curves allows the designer to see the effect of rising
currents, more parasitic inductance needs more input
ambient temperature on the maximum power allowed.
capacitance.
For normal applications (except OTP or output short cir- PD = (I2OUT1 + IOUT2
2
) ⋅ RDS,ON
cuit has occurred), the recommended input capacitance RDS,ON = 0.031Ω LLLLLLLL TJ = 125 ° C
of VIN is 1µF. Additional input capacitance may be needed
IOUT2 = k ⋅ IOUT1 LLLLLLLLk ≤ 1
on the input to reduce voltage overshoot from exceeding
or
the absolute maximum voltage of the device during load
transient conditions. The output capacitance of VOUT is IOUT1 = k ⋅ IOUT2 LLLLLLLLk ≤ 1
0.1µF at least. Please place the capacitors near the IOUT1,2(MAX) = 6A
APL3528 as close as possible.

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Rev. A.3 - Apr., 2024
APL3528

Application Information (Cont.)

1.3 Layout Consideration
TDFN2x3-14A
1.2
The PCB layout should be carefully performed to maxi-
Power Dissipation (W)

1.1
mize thermal dissipation and to minimize voltage drop,
1.0
droop and EMI. The following guidelines must be
0.9
considered:
0.8
1. Please place the input capacitors near the VIN pin as
0.7
close as possible.
0.6
2. Output decoupling capacitors for load must be placed
0.5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 near the load as close as possible for decoupling high
Ambient Temperature (oC)
frequency ripples.
Figure 3. Derating Curves for APL3528 Package
3. Locate APL3528 and output capacitors near the load to
12
TDFN2x3-14A reduce parasitic resistance and inductance for excellent
Output Current, IOUT1+IOUT2 (A)

11 VBIAS=5V
10
9
load transient performance.
8
4. The negative pins of the input and output capacitors
7
6 and the GND pin must be connected to the ground plane
5
4 of the load.
3
k=1 k=0.5
2 5. Keep VIN and VOUT traces as wide and short as
1 k=0 k=0.2
0 possible.
-40 -35 -30 -25-20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85

Ambient Temperature (oC)

Recommended Minimum Footprint
12
VBIAS=5V, TDFN2x3-14A The Via Diameter = 0.3, (0.011)
11 IOUT1=IOUT2 (k=1) Hole Size = 0.2, (0.008)
Output Current, IOUT1+IOUT2 (A)

10 0.48 1.3
9 (0.0192) (0.051)
8
0.2
7 (0.008)
0.55 0.6
6 (0.021) (0.0236)
5
4 0.2
100% On Time
3 (0.008)
90% On Time 0.2
2 (0.008) 0.7
70% On Time
1 (0.027)
50% On Time
(0.098)

0
2.5

-40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85

Ambient Temperature (oC) 0.4

(0.016)

Figure 4. Safe Operating Area for APL3528 Package

0.9
(0.035)
0.2
(0.008) 0.2
(0.008)
TDFN2x3-14 Unit: mm, (Inch)

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Rev. A.3 - Apr., 2024
APL3528

Package Information
TDFN2x3-14
D A

Pin 1

b
E

A1
D2
A3

NX
aaa c
SEATING PLANE
Pin 1 Cornar

E2
e

K L

S TDFN2x3-14
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 0.70 0.80 0.028 0.031

A1 0.00 0.05 0.000 0.002

A3 0.11 REF 0.004 REF

b 0.15 0.25 0.006 0.010

D 1.90 2.10 0.075 0.083

D2 0.80 1.00 0.031 0.039

E 2.90 3.10 0.114 0.122

E2 2.40 2.60 0.094 0.102

e 0.40 BSC 0.016 BSC

L 0.30 0.40 0.012 0.016

K 0.20 0.008

aaa 0.08 0.003

Copyright  ANPEC Electronics Corp. 16 www.anpec.com.tw

Rev. A.3 - Apr., 2024
APL3528

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 A
OD1 B
B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
8.4+2 .0 0 13.0+0 .5 0
178.0±2.00 50 MIN. 1 .5 MIN. 2 0.2 MIN. 8.0±0.20 1.75±0.10 3.50±0.05
-0.00 - 0.2 0
TDFN2x3 -14 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10
4.0±0.10 4.0 ±0.1 0 2.0±0.05 1 .5 MIN. 0.25±0.05 2.3 0±0.20 3.30 ±0 .2 0 1.00±0.20
-0.00

(mm)

Devices Per Unit

Package Type Unit Quantity
TDFN2x3-14 Tape & Reel 3000

Copyright  ANPEC Electronics Corp. 17 www.anpec.com.tw

Rev. A.3 - Apr., 2024
APL3528

Taping Direction Information

TDFN2x3-14

USER DIRECTION OF FEED

Classification Profile

Copyright  ANPEC Electronics Corp. 18 www.anpec.com.tw

Rev. A.3 - Apr., 2024
APL3528

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (t s)

Average ramp-up rate

3 °C/second max. 3°C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature See Classification Temp in table
See Classification Temp in table 1
(Tp)* 2
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (T p to Tsmax) 6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Note: ANPEC’s green products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL
classification at lead-free peak reflow temperature.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3 3
Package Volume mm Volume mm
Thickness <350 ≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
3 3 3
Package Volume mm Volume mm Volume mm
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C

Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA

Copyright  ANPEC Electronics Corp. 19 www.anpec.com.tw

Rev. A.3 - Apr., 2024
APL3528

Customer Service

Head Office :
No.6, Duxing 1st Rd., East Dist.,
Hsinchu City 300096, Taiwan (R.O.C.)
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No.11, Ln. 218, Sec. 2, Zhongxing Rd., Xindian Dist.,
New Taipei City 231037, Taiwan (R.O.C.)
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

Copyright  ANPEC Electronics Corp. 20 www.anpec.com.tw

Rev. A.3 - Apr., 2024