Received: 18 December 2020 Revised: 3 March 2021 Accepted: 21 March 2021

DOI: 10.1002/cta.3014

ORIGINAL PAPER

A twice boost nine-level switched-capacitor multilevel

(2B-9L-SCMLI) inverter with self-voltage balancing
capability

Manita Kumari1 | Marif Daula Siddique2 | Adil Sarwar1 |

3,4 1
Saad Mekhilef | Mohd Tariq

1
Department of Electrical Engineering,
Aligarh Muslim University, Aligarh, India Summary
2
Department of Electrical Engineering, The research on the multilevel inverter structures has been focused on reduc-
Qatar University, Doha, Qatar ing the number of voltage sources and the components while obtaining voltage
3
Power Electronics and Renewable boosting in the output voltage. A lesser number of components would ensure
Energy Research Laboratory, Department
of Electrical Engineering, University of
lesser cost while higher boosting ability increases its application potential.
Malaya, Kuala Lumpur, Malaysia Based on these features, the paper presents a new topology for switched-
4
School of Software and Electrical capacitor multi-level inverter (SCMLI), which can produce an output voltage
Engineering, Swinburne University of
waveform of nine levels with a voltage boosting of twice the input voltage
Technology, Melbourne, Victoria,
Australia employing a single dc voltage source, three capacitors, and 11 power switches.
The operation of switches, capacitors with a self-charge balancing modulation
Correspondence
scheme, and a voltage source for producing nine-level boosted output voltage
Marif Daula Siddique, Department of
Electrical Engineering, Qatar University, make this topology useful, and it is capable of supplying different types of
Doha, Qatar. load with efficiency above 97%. The simulation results and the hardware
Email: marifdaula1@gmail.com
results are provided to verify the satisfactory operation of the proposed
Funding information topology.
Ministry of Higher Education, Malaysia,
Grant/Award Number: LRGS/1/2019/ KEYWORDS
UKM-UM/01/6/3 boost inverter topology, multi-level inverter, self-voltage balancing, switched capacitor, total
stanging voltage (TSV)

1 | INTRODUCTION

Multi-level inverters are the preferred inverters in the industry due to their superior power quality, using lower-rated
power switches to produce higher voltage levels. Moreover, the lower voltage stress across the switches support
operation at small and high frequency at higher efficiency. The stepped output voltage reduces the harmonic
component in the output voltage. The conventional multi-level inverters (like neutral point clamped, flying capacitor,
and cascaded H-bridge) are being used for medium and high voltage applications. For producing multi-level output
with CHB, H-bridge units are cascaded due to their unique features of modularity and a lower number of power
components.1,2 Although the conventional multi-level inverters are modular and have low dv/dt stress across the
semiconductor devices, there are some limitations with traditional multi-level inverter topologies. To increase the
number of high voltage generation levels, NPC (neutral point clamped) requires a large number of diodes and switches.
Further, with NPC, a high dc-link voltage is required as the output peak is half of the dc-link voltage. Similarly, the
cascaded H-bridge inverter needs more isolated dc sources with an increase in the numeral of levels or developing the

Int J Circ Theor Appl. 2021;1–15. wileyonlinelibrary.com/journal/cta © 2021 John Wiley & Sons, Ltd. 1
2 KUMARI ET AL.

higher voltage at the output side. Furthermore, flying capacitor (FC) multi-level inverters need a considerably large
amount of flying capacitors for increasing the number of levels of output voltage, which increases the volume and cost
of the inverter along with control complexity of the capacitor voltages.3–6
To mitigate the limitations of conventional multi-level inverters, different authors have proposed various
topologies with the primary objective of reducing the number of components in a topology, that is, with a
minimum number of dc sources, semiconductor devices, capacitors.7–17 A new nine-level quadruple switched-capacitor
inverter is introduced in.18 It has been implemented with a single dc source, three capacitors, three diodes, and eight
switches. It has self-voltage balancing capability with voltage boosting ability without any backend H-bridge. The
capacitors voltage rating is high, that is, 2Vdc for two capacitors and Vdc for the third capacitor. A single-stage switched
capacitor MLI for cascaded MLI, which can be cascaded to produce up to ‘n’ levels, has been reported in previous
work.19 It has 12 switches for producing the nine-level voltage with a voltage gain of two. Another topology without
any backend bridge is introduced in previous work,20 but there are plenty of bidirectional switches. A nine-level T-type
packed U-cell inverter with minimum device count has been presented in previous work,21 which required two isolated
dc sources. However, it does not have a voltage-boosting property.
A nine-level inverter has been developed with voltage boosting ability,22 which needed fewer semiconductor devices
and sources than the conventional MLI topologies. However, the capacitor voltage ratings are significantly high. A multi-
level inverter topology proposed in a previous paper23 has a voltage boosting capability of four times the input source, but
switches have to withstand voltage stress of twice the input source. Since peak inverse voltage (PIV) is an essential factor
for analyzing a topology's performance,23 do have higher voltage stress issues. There are two charging structures of
switched-capacitor multi-level inverter proposed in previous work,24 by cascading H-bridge units. The isolated dc sources
of each cell have been replaced by charging capacitors to reduce the large number of separate dc sources, which are
generally required for cascading H-bridge cells. On the other hand, it is implemented with a single dc source. Besides, the
number of switches is expressively high, so that the associated losses will be high as well.24 Thus, there are several short-
comings in the various topologies presented in the literature. Some of the issues have been taken up in the present paper.
A nine-level switched-capacitor multi-level inverter with voltage boosting and self-voltage balancing ability has been
presented in this paper. The circuit structure and operation principles with conduction diagrams have been explained
in Section 2. Section 3 discusses the power loss analysis. The comparative study of the proposed topology with the
recently developed nine-level switched-capacitor multi-level inverter has been discussed in part 4, and the switching
technique applied to the proposed topology is briefly discussed in Section 5. Simulation and practical results are
presented in Section 6.

2 | P R O P O S ED T O P O L O G Y

2.1 | Configuration of the proposed topology

Figure 1 shows the proposed configuration of the switched-capacitor multi-level inverter. This topology consists
of a single dc voltage source, three capacitors, 11—switches out of which S3 is a bidirectional switch, and the rest
(S1, S2, S4-S11) are unidirectional switches. Capacitors C1 and C2 are always connected in parallel with the voltage
source. This structure is able to produce 2Vdc with a stepped output voltage waveform of nine levels. Table 1. illustrates
the switching configuration of topology to create various output voltage levels.

2.2 | Operating principle

i. +2Vdc level: As shown in Figure 2A, the load's required energy is provided through stored energy in C3 and input
voltage source by turning S2, S4, S8, and S10 on. Simultaneously, C1 and C2 are parallelized with the power supply
and charged up to 0.5Vdc each.
ii. +1.5Vdc level: As shown in Figure 2B, the load's required energy is provided through stored energy in C3 and C1 by
turning S3, S4, S8, and S10 on. Simultaneously, C1 and C2 are parallelized with the power supply.

iii. +Vdc level: As shown in Figure 2C, the load's required energy is provided by voltage source Vdc by turning S2, S4,
S5, S6, S7, and S10 on. Simultaneously, C3 is parallelized with the power supply and gets charged to Vdc.
KUMARI ET AL. 3

FIGURE 1 Proposed switched-capacitor multi-level inverter (SCMLI) topology [Colour figure can be viewed at wileyonlinelibrary.com]

T A B L E 1 Switching states of the

S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 Vo VC3
proposed topology
0 1 0 1 0 0 0 1 0 1 0 2Vdc D
0 0 1 1 0 0 0 1 0 1 0 1.5Vdc D
0 1 0 1 1 1 1 0 0 1 0 Vdc C
0 0 1 1 0 1 0 0 0 1 0 0.5Vdc —
1 0 0 1 0 1 0 0 0 1 0 0 —
0 1 0 0 1 0 1 0 0 0 1
0 0 1 0 1 0 1 0 0 0 1 −0.5Vdc —
1 0 0 1 1 1 1 0 0 0 1 −Vdc C
0 0 1 0 1 0 0 0 1 0 1 −1.5Vdc D
1 0 0 0 1 0 0 0 1 0 1 −2Vdc D

iv. +0.5Vdc level: As shown in Figure 2D, the load's required energy is provided by energy stored in C1 by turning on
switches S3, S4, S5, S6, and S10.
v. 0 level: there are two possible conditions for zero voltage output.
0 level Redundant state 1: as shown in Figure 3A, no energy is provided to load by turning on S2, S5, S7, and S11.

0 level redundant state 2: as shown in Figure 3B, no energy is provided to load by turning on S1, S4, S6, and S10

vi. −2Vdc level: As shown in Figure 4A, the load's required energy is provided through stored energy in C3 and input
voltage source by turning S1, S5, S9, and S11 on. Simultaneously, C1 and C2 are parallelized with the power supply
and charged up to 0.5Vdc each.

vii. −1.5Vdc level: As shown in Figure 4B, the load's required energy is provided through stored energy in C3 and C1 by
turning S3, S5, S9, and S11 on. Simultaneously, C1 and C2 are parallelized with the power supply.

viii. −Vdc level: As shown in Figure 4C, the load's required energy is provided by voltage source Vdc by turning S1, S4,
S5, S6, S7, and S11 on. Simultaneously C3 is parallelized with the power supply charged to Vdc.
ix. −0.5Vdc level: As shown in Figure 4D, the load's required energy is provided by energy stored in C2 by turning S3,
S5, S7, and S11 on.
4 KUMARI ET AL.

F I G U R E 2 Current flowing paths and component's states at different positive voltage levels: (A) Vo = +2Vdc, (B) Vo = +1.5Vdc,
(C) Vo = +Vdc and (D) Vo = +0.5Vdc [Colour figure can be viewed at wileyonlinelibrary.com]

FIGURE 3 Current flowing paths for zero voltage (A) Vo = 0 and (B) Vo = 0 [Colour figure can be viewed at wileyonlinelibrary.com]

Table 2 represents the voltage stress that appeared across the switches when it is in an OFF state, and the switch
should withstand this value without damaging itself. The blocking voltage of switches (S1, S2) and (S4-S11) is Vdc, and
for S3, it is 0.5Vdc. The voltage rating of C1 and C2 is 0.5Vdc, while C3's voltage rating is Vdc. Since the voltage stress
across the switches, as well as voltage ratings of capacitors for this topology, is limited to the input voltage source (Vdc),
it is advantageous in minimizing the overall cost.

3 | POWER L OS S A NALY SIS

Losses in an inverter topology mainly consist of conduction losses, switching losses, and this section comprises the
calculation of theoretical values of losses for the proposed nine-level inverter. Conduction loss is due to the forward
KUMARI ET AL. 5

F I G U R E 4 Current flowing paths and component's states at different negative voltage levels: (A) Vo = −2Vdc, (B) Vo = −1.5Vdc,
(C) Vo = −Vdc, and (D) Vo = −0 [Colour figure can be viewed at wileyonlinelibrary.com]

T A B L E 2 Stress distribution across

Components Voltage stress
switches of the proposed topology
S1, S2, S4, S5, S6, S7, S8, S9, S10 and S11 Vdc
S3 0.5Vdc

resistance of switches, diodes, capacitors, and the voltage drop across it when current flows through them. To calculate
conduction loss, we need to consider the internal resistance of each of these devices. Therefore, the conduction loss of a
semiconductor switch is given by the sum of losses across the switch and its antiparallel diode given by the following
equation.

PC,sw = V SW ,ON iðt Þ + RSW iβ ðt Þ ð1Þ

PC,D = V D,ON iðt Þ + RD i2 ðt Þ ð2Þ

where VSW, ON and VD, ON are ON state voltage drops of a switch and its antiparallel diode, respectively. Similarly, RSW
and RD represent the forward resistances of switch and diode, respectively. The value of β is associated with the parame-
ters of a switch, which are generally mentioned in the respective datasheet. The average conduction loss of switch for
one complete cycle (2π) is determined as

XN SW 1 2π
  XN D 1 2π
 
PC = x = 1 2π
V SW ,ON + RSW iβ ðt Þ dt + x = 1 2π
V D,ON iðtÞ + RD i2 ðt Þ dt ð3Þ
ð 0 ð 0
6 KUMARI ET AL.

where NSW and ND are the total number of switches and diodes, respectively. Since semiconductor switches are not
ideal and take some time for changing their state from blocking state to conducting state and vice versa, consequently,
switching loss occurs due to the voltage across and current through the switches while turning on and turning off
period. By considering the linear variation of voltage and current during transition periods switching loss (PSW) is given
by the following equation.
hXN i
ð Þ ×f ð4Þ
SW
PSW = x=1
N x,ON E x,ON + N x,OFF E x,OFF

Figure 5A,B represent the power loss distribution for a resistive load of 100 Ω and 20 Ω, respectively, whereas,
Figure 5C,D represent the power loss distribution across switches for an inductive load of (R = 100 Ω, L = 100 mH)
and (R = 20 Ω, L = 20 mH), respectively. From the given graphs, it can be observed that the conduction loss of switches
(S1-S5, S8-S11) is high as compared to their switching loss and diode conduction loss. However, conduction losses of
diodes are more for switches S6 and S7.
The efficiency (ɳ), is given by the ratio of output power (Po) to input power (i.e., algebraic sum of output power,
conduction losses, and switching losses).

Po
ɳ= ð5Þ
Po + PC + PSW

F I G U R E 5 Power loss distribution across switches and its antiparallel diodes for resistive load (A, B) and inductive load (C, D) [Colour
figure can be viewed at wileyonlinelibrary.com]
KUMARI ET AL. 7

The input power versus efficiency curve is shown in Figure 6, and it is observed that the proposed multi-level inverter
is able to provide supply to the load with efficiency as high as 97% and even more. This plot of efficiency for different
input power is taken using PLECS software and Figure 7 represents the operational PLECS model for calculating effi-
ciency. It can be seen that for the input power of approximately 101 W, the efficiency is nearly 97.55%.

4 | C OM P ARA T I V E ST UD Y

The comparative study of recently developed nine-level switched-capacitor multi-level inverters is represented in
Table 3. The comparison is made on the basis of quantitative analysis of components, that is, no. of switches, capacitors,
dc sources, diodes, voltage rating of capacitor, voltage boosting ability, charge balancing, and the total standing voltage.

4.1 | Total standing voltage

Total standing voltage is the reflection of the cost requirement of a topology as it defines the overall voltage rating of
required semiconductor devices (switches, diodes) present in topology and is given by

F I G U R E 6 Efficiency versus input power curve for proposed

topology [Colour figure can be viewed at wileyonlinelibrary.com]

FIGURE 7 The PLECS model for the proposed topology [Colour figure can be viewed at wileyonlinelibrary.com]
8 KUMARI ET AL.

TABLE 3 Comparative study of nine-level SCMLIs

Voltage
boosting Charge MBV TSV ɳ
[T] NSW Ndriver NCAP NDC ND VC,rating feature Gain balancing (pu) (pu) CF (%)
18
8 8 3 1 3 2Vdc, Vdc Yes 4 Series– 4 5.75 23.43 93
parallel
19
12 10 2 1 0 0.5Vdc Yes 2 Series– 1 5.5 26.75 80.61
parallel
20
10 8 2 1 1 Vdc Yes 2 Series– 3 6 24.0 95
parallel
21
8 7 2 2 0 0.5Vdc No - Modulation 2 4.5 21.5 NA
based
22
12 11 3 1 0 2Vdc, Vdc Yes 4 Series– 4 6 27.5 97.7
parallel
23
12 12 2 1 0 2Vdc, Vdc Yes 4 Series– 2 5.25 27.31 NA
parallel
[P] 12 11 3 1 0 0.5Vdc, Vdc Yes 2 Series– 1 5.25 28.62 97.55
parallel

Note: NSW, Ndriver, NCAP, NDC, ND, and VC,rating represents the number of switches, drivers, capacitors, isolated dc sources, diodes, and capacitor voltage ratings,
respectively. MBV: maximum blocking voltage of individual switch, TSV: total standing voltage, CF: Cost function, ɳ: efficiency. NA: not available.

Pn Pm
i = 1 V bswitch ,i + j = 1 V bdiode ,j
TSV = ð6Þ
V omax

where V bswitch ,i and V bdiode ,j represents the maximum blocking voltage across each switch and diode respectively, and
V omax is the peak value of output voltage in the given topology.

4.2 | Cost function

In order to evaluate various topologies, a factor called cost function may be determined with respect to the number of
output voltage levels and is given by the following equation
 
αðTSV Þpu
CF = N SW + N driver + N D + N CAP + ð7Þ
Gain

It is calculated by the number of IGBT switches, drivers, diodes, capacitors, and since we include the semiconductor
switches ratings, so TSV is an essential factor to consider in it. Gain is also incorporated to analyze the boosting ability.
The factor α is a weight coefficient, and its value may vary near to 1, here it is taken as 1.18
From the comparative study of various switched capacitor multi-level inverter, it can be perceived that the
maximum blocking voltage is as high as 4 (in the per-unit system) for some of the switches of topologies proposed
in.18,22 In contrast, some of the topologies have MBV of 320 and 221,23 also, which necessitates the use of highly
rated switches which in turn leads to increment in overall cost, however, in the proposed topology MBV is limited
to the input source voltage. Moreover, capacitor voltage ratings are quite high for some of the topologies whereas,
the proposed topology needed capacitors of rating up to input voltage. The proposed topology produces boosted out-
put voltage with a single dc source, devices used are of lower ratings and the voltage stress across devices is limited
to the value of input dc source, which reduces the overall cost. Moreover, it does not require an additional circuit
for capacitor voltage balancing.
KUMARI ET AL. 9

5 | NEAREST LEVEL CONTROL

There are various modulation techniques (for high frequency as well as for low-frequency applications) that have been in
use for many decades like sine triangular pulse width modulation (SPWM), which is valuable in terms of reducing lower
order harmonics but with a cost of an increase in switching losses. Phase displacement PWM (PDPWM), third harmonic

F I G U R E 8 Basic operational diagram of nearest level control

[Colour figure can be viewed at wileyonlinelibrary.com]

FIGURE 9 Block diagram illustration of nearest level control (NLC) [Colour figure can be viewed at wileyonlinelibrary.com]

F I G U R E 1 0 Simulation results of load voltage, load current (amplified by a gain of 10), and the voltage across capacitor C3 with
different load conditions (only resistance value is varied while inductance value is kept constant at 50 mH) [Colour figure can be viewed at
wileyonlinelibrary.com]
10 KUMARI ET AL.

injection PWM (THIPWM) contains a modulating wave that is consists of fundamental components and third harmonic
components but has the limitation of absence of any particular procedure to calculate the third harmonic component
required to be added.25,26 Selective harmonic elimination PWM (SHPWM) in this method, certain angles are calculated to
remove odd harmonics, whereas, with an increasing number of levels, the evaluation of angles becomes difficult.27,28 Space
vector pulse width modulation (SVPWM) is used in low-frequency applications, and it is a highly computation-based tech-
nique.29 However, the nearest level control (NLC) method is a very simple modulation technique and can be implemented
with almost any topology, also known as the round value method as it takes the rounded value of levels for intermediate
values, which is represented in Figure 8 and block diagram illustration is shown in Figure 9. NLC method is implemented
with the fundamental frequency and used in high voltage applications. In this method, a variable ‘v’ is defined as

ðN L −1Þ
v= ð8Þ
2

where NL is the number of voltage levels given by inverter topology. Generally, a sine wave with fundamental frequency
is taken as the reference signal and multiplied with variable ‘v’ in order to get the amplified signal. This amplified
signal is compared with constant dc lines, and then after application of logic, produced switching signals are given to
the gates of inverter switches.

6 | SIMULATI ON AN D EX PE R I M E NT A L RE SUL T S

The simulation result for the proposed inverter topology is observed in MATLAB/Simulink environment with the fundamen-
tal frequency (50 Hz), an input voltage source (Vdc) of 100 V, and all three capacitors (C1, C2, and C3) values are set to 4.7 mF.

F I G U R E 1 1 Waveforms representing voltage across capacitors

C1, C2, and C3 for an inductive load (R = 80, L = 50 mH) [Colour
figure can be viewed at wileyonlinelibrary.com]
KUMARI ET AL. 11

The voltage across and current (which has been amplified with a gain of 10 in order to make it noticeable) through
the load are taken by varying the load several times, which are shown in Figure 10. The simulation results are pres-
ented with RL load. Initially, the resistance value is kept low from 0.02 to 0.1 s, and then it is increased onwards from
0.1 s to 0.2 s, which can be witnessed from Figure 10A, whereas Figure 10B shows the result with an initial load of high
resistance value from 0.02 to 0.1 s, and then it is decreased onwards. On the other hand, the resistance value is kept low
initially then increased at instant 0.08 s and then again lowered at 0.16 s and its converse operation is shown in
Figure 10C,D, which is clear from the corresponding change in load current as depicted in the corresponding figures.
The voltage across capacitors C1, C2, and C3 with RL load (R = 80 Ω and L = 50 mH) is represented in Figure 11, it
signifies that the voltage across capacitors (C1 and C2) is limited to half of the input voltage source and the voltage
across C3 is limited to the value of input dc source. The simulation results, including load voltage and load current
along with voltage stress across capacitor C3 with resistive load (R = 80 Ω) and inductive load (R = 80 Ω and
L = 50 mH), are shown in Figure 12A,B.
To verify the performance of the proposed topology, experimental results are observed with an experimental setup
as shown in Figure 13. For the realization of the proposed topology, discrete components have been used. For the
switch, TOSHIBA IGBT GT50J325 has been used. For the dc-link C1 and C2, two capacitors of 2200 μF, and for floating
capacitor C3, a capacitor of 4700 μF has been used. NLCPWM has been used for gate pulse generation with an output

F I G U R E 1 2 Simulation results (load current amplified by a gain of 10 to make it visible) [Colour figure can be viewed at
wileyonlinelibrary.com]

FIGURE 13 Experimental setup [Colour figure can be viewed at wileyonlinelibrary.com]

12 KUMARI ET AL.

frequency of 50 Hz. The gate pulses are generated using the dSPACE 1104 controller and these low voltage gate pulses
are amplified and isolated using a gate driver circuit. The various components and parameters used are listed in
Table 4.
The proposed topology has been validated using steady-state and dynamic operating conditions. Figure 14A
displays the load voltage, current, and voltage of C3 with a resistive load. With the input voltage of 100 V, the

T A B L E 4 Specifications of the
Component's name Specification
experimental setup
Inductive load 50 mH
Resistive load 80 Ω
Capacitance values C 1, C 2 2200 μF
C3 4700 μF
Source voltage 100 V
Output frequency 50 Hz

F I G U R E 1 4 Experimental results of load voltage, load current and capacitor voltage with (A) resistive load (R = 80 Ω) and
(B) inductive load (R = 80 Ω, L = 50 mH) [Colour figure can be viewed at wileyonlinelibrary.com]
KUMARI ET AL. 13

peak output voltage has a magnitude of 200 with 50 V step voltage. The voltage of C3 is stable at 100 V, that is,
equal to the input voltage. Further, the waveforms with the resistive-inductive load are shown in Figure 14B. The
result for changing load conditions from resistive (R = 80 Ω) to inductive load (R = 80, L = 50 mH) is shown in
Figure 15A, while Figure 15B depicts the change of modulation index from 1.0 to 0.50. With the change of load,
the current waveform changes from the staircase to the sinusoidal due to the presence of inductance. The change
of modulation index reduces the number of levels, which reduced the output voltage magnitude. From all these
steady-state and dynamic operating conditions, it can be concluded that the voltage of C3 remains balanced at
100 V irrespective of loading conditions.
The experimental efficiency of the proposed topology has also been measured and is shown in Figure 16 along with
the power losses. As the low prototype has been developed in the lab, the maximum output power has been considered
as 250 W. A resistive load has been used for the measurement of efficiency.

F I G U R E 1 5 Experimental results of load voltage, load current and capacitor voltage with (A) with varying load condition initially
resistive load (R = 80 Ω) and then inductive load (R = 80 Ω, L = 50 mH), (B) change of modulation index [Colour figure can be viewed at
wileyonlinelibrary.com]
14 KUMARI ET AL.

F I G U R E 1 6 Plot of efficiency and power loss with respect to the

output power [Colour figure can be viewed at wileyonlinelibrary.
com]

7 | C ON C L U S I ON

This paper proposes an improved, nine-level switched-capacitor MLI structure. Compared to other nine-level topolo-
gies, it needs a single voltage source and low-rated capacitors. It has the voltage boosting feature, self-capacitor voltage
balancing capability. Additionally, the voltage stress across switches is also limited to the level of the input voltage
source. Simulation results with changing load conditions are represented along with the power loss analysis and effi-
ciency curve. To validate the operation of the proposed topology, experimental results are also incorporated which
shows the twice voltage gain with self-balancing of the capacitor voltages.

A C K N O WL E D G M E N T
The authors would like to thank the Ministry of Higher Education, Malaysia for the financial support under the Long
Term Research Grant Scheme (LRGS): LRGS/1/2019/UKM-UM/01/6/3.

ORCID
Marif Daula Siddique https://orcid.org/0000-0002-0799-500X
Adil Sarwar https://orcid.org/0000-0002-8614-6697
Saad Mekhilef https://orcid.org/0000-0001-8544-8995

R EF E RE N C E S
1. Sivakumar S, Sathik MJ, Manoj PS, Sundararajan G. An assessment on performance of DC-DC converters for renewable energy applica-
tions. Renew Sustain Energy Rev. 2016;58:1475-1485.
2. Bana PR, Panda KP, Naayagi RT, Siano P, Panda G. Recently developed reduced switch multilevel inverter for renewable energy integra-
tion and drives application: topologies, comprehensive analysis and comparative evaluation. IEEE Access. 2019;7:54888-54909. https://
doi.org/10.1109/ACCESS.2019.2913447
3. Anand V, Singh V. Implementation of cascaded asymmetrical multilevel inverter for renewable energy integration. Int J Circuit Theory
Appl. 2021. https://doi.org/10.1002/cta.2944
4. Jagabar Sathik M, Sandeep N, Almakhles D, Blaabjerg F. Improved “K” type seven-level switched capacitor inverter topology with Self-
voltage balancing. Int J Circuit Theory Appl. 2020;48(10):1800-1819. https://doi.org/10.1002/cta.2811
5. Liu Y, Luo FL. Multilevel inverter with the ability of self-voltage balancing. IEE Proc Electr Power Appl. 2006;153(1):105-115. https://doi.
org/10.1049/ip-epa:20050192
6. De S, Banerjee D, Siva Kumar K, Gopakumar K, Ramchand R, Patel C. Multilevel inverters for low-power application. IET Power Elec-
tron. 2011;4(4):384-392. https://doi.org/10.1049/iet-pel.2010.0027
7. Liu J, Cheng KWE, Ye Y. A cascaded multilevel inverter based on switched-capacitor for high-frequency AC power distribution system.
IEEE Trans Power Electron. 2014;29(8):4219-4230. https://doi.org/10.1109/TPEL.2013.2291514
8. Jagabar Sathik M, Prabaharan N, Ibrahim SAA, Vijaykumar K, Blaabjerg F. A new generalized switched diode multilevel inverter topol-
ogy with reduced switch count and voltage on switches. Int J Circuit Theory Appl. 2020;48(4):619-637. https://doi.org/10.1002/cta.2732
9. Velliangiri S, Ramasamy S, Ponnusamy P, M JS. Design of nine step switched capacitor multilevel inverter and its cascaded extension.
Int J Circuit Theory Appl. 2021. https://doi.org/10.1002/cta.2926
KUMARI ET AL. 15

10. Ye Y, Cheng KWE, Liu J, Ding K. A step-up switched-capacitor multilevel inverter with self-voltage balancing. IEEE Trans Ind Electron.
2014;61(12):6672-6680. https://doi.org/10.1109/TIE.2014.2314052
11. Barzegarkhoo R, Moradzadeh M, Zamiri E, Madadi Kojabadi H, Blaabjerg F. A New Boost Switched-Capacitor Multilevel Converter
with Reduced Circuit Devices. IEEE Trans Power Electron. 2018;33(8):6738-6754. https://doi.org/10.1109/TPEL.2017.2751419
12. Hosseinpour M, Seifi A, Rahimian MM. A bidirectional diode containing multilevel inverter topology with reduced switch count and
driver. Int J Circuit Theory Appl. 2020;48(10):1766-1785. https://doi.org/10.1002/cta.2810
13. Alishah RS, Hosseini SH, Babaei E, Sabahi M, Gharehpetian GB. New high step-up multilevel converter topology with self-voltage
balancing ability and its optimization analysis. IEEE Trans Ind Electron. 2017;64(9):7060-7070. https://doi.org/10.1109/TIE.2017.2688968
14. Taghvaie A, Adabi J, Rezanejad M. A self-balanced step-up multilevel inverter based on switched-capacitor structure. IEEE Trans Power
Electron. 2018;33(1):199-209. https://doi.org/10.1109/TPEL.2017.2669377
15. Sedaghati F, Majareh SHL. A multilevel inverter based on cascade connection of submultilevel units with reduced switch count. Int J
Circuit Theory Appl. 2019;47(7):1152-1172. https://doi.org/10.1002/cta.2638
16. Saeedian M, Adabi Firouzjaee ME, Hosseini SM, Adabi J, Pouresmaeil E. A novel step-up single source multilevel inverter: topology,
operating principle and modulation. IEEE Trans Power Electron. 2018;34(4):1-1, 3282. https://doi.org/10.1109/TPEL.2018.2848359
17. Liu J, Wu J, Zeng J. Symmetric/asymmetric hybrid multilevel inverters integrating switched-capacitor techniques. IEEE J Emerging Sel
Top Power Electron. 2018;6(3):1616-1626. https://doi.org/10.1109/jestpe.2018.2848675
18. Liu J, Lin W, Wu J, Zeng J. A novel nine-level quadruple boost inverter with inductive-load ability. IEEE Trans Power Electron. 2019;34
(5):4014-4018. https://doi.org/10.1109/TPEL.2018.2873188
19. Lee SS. Single-stage switched-capacitor module (S3CM) topology for cascaded multilevel inverter. IEEE Trans Power Electron. 2018;33
(10):8204-8207. https://doi.org/10.1109/TPEL.2018.2805685
20. Zamiri E, Vosoughi N, Hosseini SH, Barzegarkhoo R, Sabahi M. A new cascaded switched-capacitor multilevel inverter based on
improved series-parallel conversion with less number of components. IEEE Trans Ind Electron. 2016;63(6):3682-3694. https://doi.org/10.
1109/TIE.2016.2529563
21. Niu DC, Gao F, Wang P, Zhou K, Qin F, Ma Z. A nine-level t-type packed u-cell inverter. IEEE Trans Power Electron. 2019;35(2):1-1,
1175. https://doi.org/10.1109/TPEL.2019.2931523
22. Nakagawa Y, Koizumi H. A boost-type nine-level switched capacitor inverter. IEEE Trans Power Electron. 2019;34(7):6522-6532. https://
doi.org/10.1109/TPEL.2018.2876158
23. Sandeep N, Sathik J, Yaragatti U, Krishnasamy V. Switched-capacitor based quadruple boost nine-level inverter. IEEE Trans Power Elec-
tron. 2019;34(8):1-1, 7150. https://doi.org/10.1109/TPEL.2019.2898225
24. Khoun Jahan H, Abapour M. Switched-capacitor-based multilevel inverter for grid-connected photovoltaic application. IEEE Trans
Power Electron. 2020;1-1. https://doi.org/10.1109/tpel.2020.3035598
25. Rawa M, Siddique MD, Mekhilef S, et al. Dual input switched-capacitor-based single-phase hybrid boost multilevel inverter topology
with reduced number of components. IET Power Electron. 13(4):881-891. https://doi.org/10.1049/iet-pel.2019.0826
26. Memon MA, Siddique MD, Saad M, Mubin M. Asynchronous Particle Swarm Optimization-Genetic Algorithm (APSO-GA) based selec-
tive harmonic elimination in a cascaded H-bridge multilevel inverter. IEEE Trans Ind Electron. 2021;1-1. https://doi.org/10.1109/TIE.
2021.3060645
27. Panda KP, Panda G. Application of swarm optimisation-based modified algorithm for selective harmonic elimination in reduced switch
count multilevel inverter. IET Power Electron. 2018;11(8):1472-1482. https://doi.org/10.1049/iet-pel.2017.0697
28. Sharifzadeh M, Vahedi H, Portillo R, Franquelo LG, Al-Haddad K. Selective harmonic mitigation based self-elimination of triplen har-
monics for single-phase five-level inverters. IEEE Trans Power Electron. 2018;34(1):86-96. https://doi.org/10.1109/TPEL.2018.2812186
29. Yu K, Xiong B, Zhao J. A comprehensive study of space vector pulse-width modulation technique for three-phase Z-source inverters. Int
J Circuit Theory Appl. 2016;44(2):364-381. https://doi.org/10.1002/cta.2081

How to cite this article: Kumari M, Siddique MD, Sarwar A, Mekhilef S, Tariq M. A twice boost nine-level
switched-capacitor multilevel (2B-9L-SCMLI) inverter with self-voltage balancing capability. Int J Circ Theor
Appl. 2021;1–15. https://doi.org/10.1002/cta.3014