TPS54531

SLVSBI5B – MAY 2013 – REVISED OCTOBER 2023

TPS54531 5-A, 28-V Input, SWIFT™ Step-Down Converter With Eco-mode

1 Features RDS(on) high-side MOSFET. To increase efficiency

at light loads, a pulse skipping Eco-mode feature
• 3.5 to 28-V input voltage range
is automatically activated. Furthermore, the 1-μA
• Adjustable output voltage down to 0.8 V
shutdown supply current allows the device to be
• Integrated 80-mΩ high-side MOSFET supports up
used in battery powered applications. Current mode
to 5-A continuous output current
control with internal slope compensation simplifies
• High efficiency at light loads with a pulse skipping
the external compensation calculations and reduces
Eco-mode
component count while allowing the use of ceramic
• Fixed 570-kHz switching frequency
output capacitors. A resistor divider programs the
• Typical 1-μA shutdown quiescent current
hysteresis of the input undervoltage lockout. An
• Adjustable slow start limits inrush currents
overvoltage transient protection circuit limits voltage
• Programmable UVLO threshold
overshoots during startup and transient conditions.
• Overvoltage transient protection
A cycle-by-cycle current-limit scheme, frequency fold
• Cycle-by-cycle current-limit, frequency fold back,
back, and thermal shutdown protect the device and
and thermal shutdown protection
the load in the event of an overload condition. The
• Available in easy-to-use thermally enhanced
TPS54531 device is available in 8-pin SO PowerPAD
8-pin SO PowerPAD™ integrated circuit package
integrated circuit package that has been internally
• Use TPS56637 for higher efficiency in a smaller
optimized to improve thermal performance.
package
• Create a custom design using the TPS54531 with Package Information
the WEBENCH® Power Designer PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
TPS54531 DDA (SO PowerPAD, 8) 4.9 mm × 6 mm
2 Applications
• Consumer applications such as set-top boxes, (1) For all available packages, see the orderable addendum at
the end of the data sheet.
CPE equipment, LCD displays, peripherals, and (2) The package size (length × width) is a nominal value and
battery chargers includes pins, where applicable.
• Industrial and car audio power supplies
• 5-V, 12-V and 24-V distributed power systems
3 Description
The TPS54531 device is a 28-V, 5-A non-
synchronous buck converter that integrates a low
100
Ren1
EN VIN VIN 90
Ren2 CI 80
TPS54531 70 VIN = 12 V VIN = 24 V
Efficiency - %

CBOOT
BOOT 60
LO
VOUT 50
PH
SS 40
D1 CO RO1
COMP 30

CSS C1 20
C2 VSENSE 10
R3
GND RO2 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Current - A C007

Simplified Schematic TPS54531 Efficiency

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes..........................................12
2 Applications..................................................................... 1 8 Application and Implementation.................................. 13
3 Description.......................................................................1 8.1 Application Information............................................. 13
4 Revision History.............................................................. 2 8.2 Typical Application.................................................... 13
5 Pin Configuration and Functions...................................3 8.3 Power Supply Recommendations.............................23
6 Specifications.................................................................. 4 8.4 Layout....................................................................... 23
6.1 Absolute Maximum Ratings........................................ 4 9 Device and Documentation Support............................25
6.2 ESD Ratings............................................................... 4 9.1 Device Support......................................................... 25
6.3 Recommended Operating Conditions.........................4 9.2 Receiving Notification of Documentation Updates....25
6.4 Thermal Information....................................................5 9.3 Support Resources................................................... 25
6.5 Electrical Characteristics.............................................5 9.4 Trademarks............................................................... 25
6.6 Typical Characteristics................................................ 6 9.5 Electrostatic Discharge Caution................................25
7 Detailed Description........................................................8 9.6 Glossary....................................................................25
7.1 Overview..................................................................... 8 10 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram........................................... 9 Information.................................................................... 25
7.3 Feature Description.....................................................9

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2014) to Revision B (October 2023) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Added TPS56637 information in the Features .................................................................................................. 1
• Changed column title from BODY SIZE to PACKAGE SIZE in the Package Information table..........................1
• Updated trademark information.......................................................................................................................... 1
• Added WEBENCH support description in the Features section......................................................................... 1
• Moved storage temperature to the Absolute Maximum Ratings table................................................................ 4
• Changed table title from Handling Ratings to ESD Ratings ...............................................................................4
• Added WEBENCH design steps.......................................................................................................................14
• Added WEBENCH information in the Development Support section............................................................... 25

Changes from Revision * (May 2013) to Revision A (October 2014) Page

• Added the Handling Ratings table, Feature Description section, Device Functional Modes section, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
• Added equation for Iripple in the Inductor Selection section...............................................................................15

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5 Pin Configuration and Functions

BOOT 1 8 PH

VIN 2 PowerPAD
TM 7 GND
(Pin 9)
EN 3 6 COMP

SS 4 5 VSENSE

Figure 5-1. DDA Package, 8-Pin SO With PowerPAD™ Integrated Circuit Package Top View

Table 5-1. Pin Functions

PIN TYPE
(1) DESCRIPTION
NO. NAME
A 0.1-μF bootstrap capacitor is required between the BOOT and PH pins. If the voltage on this
1 BOOT O capacitor falls below the minimum requirement, the high-side MOSFET is forced to switch off until the
capacitor is refreshed.
2 VIN I This pin is the 3.5- to 28-V input supply voltage.
This pin is the enable pin. To disable, pull below 1.25 V. Float this pin to enable. Programming the
3 EN I
input undervoltage lockout with two resistors is recommended.
4 SS I This pin is slow-start pin. An external capacitor connected to this pin sets the output rise time.
5 VSENSE I This pin is the inverting node of the transconductance (gm) error amplifier.
This pin is the error-amplifier output and the input to the PWM comparator. Connect frequency
6 COMP O
compensation components to this pin.
7 GND — Ground pin
8 PH O The PH pin is the source of the internal high-side power MOSFET.
PowerPAD
9 integrated circuit — For proper operation, the GND pin must be connected to the exposed pad.
package

(1) I = input, O = output

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN –0.3 30
EN –0.3 6
BOOT 38
Input Voltage V
VSENSE –0.3 3
COMP –0.3 3
SS –0.3 3
BOOT-PH 8
Output Voltage PH –0.6 30 V
PH (10 ns transient from ground to negative peak) –5
EN 100 μA
BOOT 100 mA
Source Current
VSENSE 10 μA
PH Current Limit A
VIN Current Limit A
Sink Current COMP 100
μA
SS 200
Operating Junction Temperature –40 150 °C
Storage temperature range –65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

MIN MAX UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
–2 2
all pins(1)
V(ESD) Electrostatic discharge kV
Charged device model (CDM), per JEDEC specification
–1 1
JESD22-C101, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Operating Input Voltage on the VIN pin 3.5 28 V
TJ Operating junction temperature –40 150 °C

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6.4 Thermal Information

DDA
THERMAL METRIC(1) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 55
RθJC(top) Junction-to-case (top) thermal resistance 63.2
RθJB Junction-to-board thermal resistance 31.5
°C/W
ψJT Junction-to-top characterization parameter 14.9
ψJB Junction-to-board characterization parameter 31.4
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 3.5V to 28V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Internal undervoltage lockout threshold Rising and falling 3.5 V
Shutdown supply current EN = 0 V, VIN = 12 V, –40°C to 85°C 1 4 μA
Operating – non-switching supply current VSENSE = 0.85 V 110 190 μA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising and falling 1.25 1.35 V
Input current Enable threshold – 50 mV –1 μA
Input current Enable threshold + 50 mV –4 μA
VOLTAGE REFERENCE
Voltage reference 0.772 0.8 0.828 V
HIGH-SIDE MOSFET
BOOT-PH = 3 V, VIN = 3.5 V 115 200 mΩ
On resistance
BOOT-PH = 6 V, VIN = 12 V 80 150
ERROR AMPLIFIER
Error amplifier transconductance (gm) –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V 92 μmhos
Error amplifier DC gain(1) VSENSE = 0.8 V 800 V/V
Error amplifier unity gain bandwidth(1) 5 pF capacitance from COMP to GND pins 2.7 MHz
Error amplifier source/sink current V(COMP) = 1 V, 100-mV overdrive ±7 μA
Switch current to COMP transconductance(1) VIN = 12 V 20 A/V
SWITCHING FREQUENCY
Switching Frequency VIN = 12 V, 25°C 456 570 684 kHz
Minimum controllable on time VIN = 12 V, 25°C 105 130 ns
Maximum controllable duty ratio(1) BOOT-PH = 6 V 90% 93%
PULSE SKIPPING Eco-mode
Pulse skipping Eco-mode switch current threshold 160 mA
CURRENT LIMIT
Current-limit threshold VIN = 12 V 6.3 10.5 A
THERMAL SHUTDOWN
Thermal Shutdown 165 °C
SLOW START (SS PIN)
Charge current V(SS) = 0.4 V 2 μA

(1) Specified by design

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6.6 Typical Characteristics

120 4
EN = 0V

110

ISD - Shutdown Current - µA

Rdson - On Resistance - mΩ

3 TJ = 150°C
100

90 2
TJ = 40°C

80
1 TJ = 25°C
VIN = 12 V
70

0
60 3 8 13 18 23 28
–50 –25 0 25 50 75 100 125 150
TJ - Junction Temperature - °C VIN - Input Voltage - V

Figure 6-1. ON Resistance vs Junction Temperature Figure 6-2. Shutdown Quiescent Current vs Input Voltage

590 0.824

VIN = 12 V 0.818 VIN = 12 V

FSW - Oscillator Frequency - kHz

580 Vref - Voltage Reference - V 0.812

0.806

570 0.800

0.794

560 0.788

0.782

550 0.776
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 6-3. Switching Frequency vs Junction Temperature Figure 6-4. Voltage Reference vs Junction Temperature
140 7.5
Dmin - Minimum Controllable Duty Ratio - %
Tminon - Minimum Controllable On Time - ns

7.0
130

6.5

120
6.0

110
5.5

VIN = 12 V VIN = 12 V

100 5.0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C

Figure 6-5. Minimum Controllable ON Time vs Junction Figure 6-6. Minimum Controllable Duty Ratio vs Junction
Temperature Temperature

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6.6 Typical Characteristics (continued)

2.1 12
VIN = 12 V
11
ISS - SS Charge Current - µA

Current Limit Threshold (A)

10

9
2
8

7
TJ = ±40ƒC
6 TJ = 25ƒC
TJ = 150ƒC
1.9 5
–50 –25 0 25 50 75 100 125 150 3 8 13 18 23 28
TJ - Junction Temperature - °C
Input Voltage (V) C014

Figure 6-7. SS Charge Current vs Junction Temperature Figure 6-8. Current-Limit Threshold vs Input Voltage

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7 Detailed Description
7.1 Overview
The TPS54531 device is a 28-V, 5-A, step-down (buck) converter with an integrated high-side n-channel
MOSFET. To improve performance during line and load transients, the device implements a constant-frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The TPS54531 device has a preset switching frequency of 570 kHz.
The TPS54531 device requires a minimum input voltage of 3.5 V for normal operation. The EN pin has an
internal pullup current source that can be used to adjust the input-voltage undervoltage lockout (UVLO) with two
external resistors. In addition, the pullup current provides a default condition when the EN pin is floating for the
device to operate. The operating current is 110 μA (typical) when not switching and under no load. When the
device is disabled, the supply current is 1 μA (typical).
The integrated 80-mΩ high-side MOSFET allows for high-efficiency power-supply designs with continuous
output currents up to 5 A.
The TPS54531 device reduces the external component count by integrating the boot recharge diode. The bias
voltage for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The
boot capacitor voltage is monitored by an UVLO circuit and turns the high-side MOSFET off when the voltage
falls below a preset threshold of 2.1 V (typical). The output voltage can be stepped down to as low as the
reference voltage.
By adding an external capacitor, the slow-start time of the TPS54531 device can be adjustable which enables
flexible output filter selection.
To improve the efficiency at light load conditions, the TPS54531 device enters a special pulse skipping Eco-
mode when the peak inductor current drops below 160 mA (typical).
The frequency foldback reduces the switching frequency during start-up and overcurrent conditions to help
control the inductor current. The thermal shutdown provides the additional protection under fault conditions.

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7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Fixed-Frequency PWM Control
The TPS54531 device uses a fixed-frequency, peak-current mode control. The internal switching frequency of
the TPS54531 device is fixed at 570 kHz.
7.3.2 Voltage Reference (Vref)
The voltage reference system produces a ±2% initial accuracy voltage reference (±3.5% over temperature) by
scaling the output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.8 V.
7.3.3 Bootstrap Voltage (BOOT)
The TPS54531 device has an integrated boot regulator and requires a 0.1-μF ceramic capacitor between the
BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. A ceramic capacitor with
an X7R- or X5R-grade dielectric is recommended because of the stable characteristics over temperature and
voltage. To improve drop out, the TPS54531 device is designed to operate at 100% duty cycle as long as the
BOOT-to-PH pin voltage is greater than 2.1 V (typical).
7.3.4 Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)
The EN pin has an internal pullup current-source that provides the default condition of the TPS54531 device
while operating when the EN pin floats.
The TPS54531 device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. Using
an external VIN UVLO to add at least 500-mV hysteresis is recommended unless the VIN voltage is greater than
(VOUT + 2 V). To adjust the VIN UVLO with hysteresis, use the external circuitry connected to the EN pin as

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shown in Figure 7-1. When the EN pin voltage exceeds 1.25 V, an additional 3 μA of hysteresis is added. Use
Equation 1 and Equation 2 to calculate the resistor values required for the desired VIN UVLO threshold voltages.
The VSTOP must always be greater than 3.5 V.

TPS54531

VIN

Ren1 1 mA 3 mA

EN +
Ren2 1.25 V –

Figure 7-1. Adjustable Input Undervoltage Lockout

V − VSTOP
Ren1 = START
3μA (1)

where
• VSTART is the input start threshold voltage
• VSTOP is the input stop threshold voltage

V
EN
Ren2 = V (2)
START − VEN + 1μA
Ren1

where
• VEN is the enable threshold voltage of 1.25 V
The external start and stop voltages are approximate. The actual start and stop voltages can vary.
7.3.5 Programmable Slow Start Using SS Pin
Programming the slow-start time externally is highly recommended because no slow-start time is implemented
internally. The TPS54531 device effectively uses the lower voltage of the internal voltage reference or the SS pin
voltage as the reference voltage of the power supply that is fed into the error amplifier and regulates the output
accordingly. A capacitor (CSS) on the SS pin to ground implements a slow-start time. The TPS54531 device
has an internal pullup current source of 2 μA that charges the external slow-start capacitor. Use Equation 3 to
calculate the slow-start time (10% to 90%).

C nF × VREF V
TSS ms = SS (3)
ISS μA

where
• VREF = 0.8 V
• ISS = 2 μA
The slow-start time must be set between 1 ms to 10 ms to ensure good startup behavior. The value slow-start
capacitor must not exceed 27 nF.
During normal operation, the TPS54531 device stops switching if the input voltage drops below the VIN UVLO
threshold, the EN pin is pulled below 1.25 V, or a thermal shutdown event occurs.

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7.3.6 Error Amplifier

The TPS54531 device has a transconductance amplifier for the error amplifier. The error amplifier compares
the VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier.
The transconductance of the error amplifier is 92 μA/V during normal operation. Frequency compensation
components are connected between the COMP pin and ground.
7.3.7 Slope Compensation
To prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the
TPS54531 device adds a built-in slope compensation which is a compensating ramp to the switch-current signal.
7.3.8 Current-Mode Compensation Design
The device is able to work with various types of output capacitors with appropriate compensation designs. For
designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended when
performing the stability analysis because the actual ceramic capacitance drops considerably from the nominal
value when the applied voltage increases. For the detailed guidelines, see the Section 8.2.2 section.
7.3.9 Overcurrent Protection and Frequency Shift
The TPS54531 device implements current mode control that uses the COMP pin voltage to turn off the high-side
MOSFET on a cycle-by-cycle basis. During each cycle the switch current and the COMP pin voltage are
compared. When the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off.
During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP
pin high, causing the switch current to increase. The COMP pin has a maximum clamp internally, which limits the
output current.
The TPS54531 device provides robust protection during short circuits. Overcurrent runaway is possible in the
output inductor during a short circuit at the output. The TPS54531 device solves this issue by increasing the off
time during short-circuit conditions by lowering the switching frequency. The switching frequency is divided by
1, 2, 4, and 8 as the voltage ramps from 0 V to 0.8 V on VSENSE pin. The relationship between the switching
frequency and the VSENSE pin voltage is listed in Table 7-1.
Table 7-1. Switching Frequency Conditions
SWITCHING FREQUENCY VSENSE PIN VOLTAGE
570 kHz VSENSE ≥ 0.6 V
570 kHz / 2 0.6 V > VSENSE ≥ 0.4 V
570 kHz / 4 0.4 V > VSENSE ≥ 0.2 V
570 kHz / 8 0.2 V > VSENSE

7.3.10 Overvoltage Transient Protection

The TPS54531 device incorporates an overvoltage transient-protection (OVTP) circuit to minimize output voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes
an overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin
voltage goes above 109% × Vref, the high-side MOSFET is forced off. When the VSENSE pin voltage falls below
107% × Vref, the high-side MOSFET is enabled again.
7.3.11 Thermal Shutdown
The device implements an internal thermal shutdown to protect the device if the junction temperature exceeds
165°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the
thermal trip threshold. When the die temperature decreases below 165°C, the device reinitiates the power-up
sequence.

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7.4 Device Functional Modes

7.4.1 Eco-mode
The TPS54531 is designed to operate in pulse skipping Eco-mode at light load currents to boost light load
efficiency. When the peak inductor current is lower than 160 mA (typical), the COMP pin voltage falls to 0.5 V
(typical) and the device enters Eco-mode . When the device is in Eco-mode, the COMP pin voltage is clamped at
0.5-V internally which prevents the high-side integrated MOSFET from switching. The peak inductor current must
rise above 160 mA for the COMP pin voltage to rise above 0.5 V and exit Eco-mode. Because the integrated
current comparator catches the peak inductor current only, the average load current entering Eco-mode varies
with the applications and external output filters.
7.4.2 Operation With VIN < 3.5 V
The device is recommended to operate with input voltages above 3.5 V. The typical VIN UVLO threshold is not
specified and the device can operate at input voltages down to the UVLO voltage. At input voltages below the
actual UVLO voltage, the device does not switch. If the EN pin is externally pulled up or left floating, the device
becomes active when the VIN pin passes the UVLO threshold. Switching begins when the slow-start sequence
is initiated.
7.4.3 Operation With EN Control
The enable threshold voltage is 1.25 V (typical). With the EN pin is held below that voltage the device is disabled
and switching is inhibited even if the VIN pin is above the UVLO threshold. The IC quiescent current is reduced
in this state. If the EN voltage increases above the threshold while the VIN pin is above the UVLO threshold, the
device becomes active. Switching is enabled, and the slow-start sequence is initiated.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The TPS54531 device is typically used as a step-down converter, which converts a voltage from 3.5 V to 28 V to
a lower voltage. WEBENCH® software is available to aid in the design and analysis of circuits.
For additional design needs, see the following devices:
TPS54231 TPS54232 TPS54233 TPS54531 TPS54332
I(max) 2A 2A 2A 5A 3.5 A
Input voltage range 3.5 to 28 V 3.5 to 28 V 3.5 to 28 V 3.5 to 28 V 3.5 to 28 V
Switching frequency (typical) 570 kHz 1000 kHz 285 kHz 570 kHz 1000 kHz
Switch current limit (minimum) 2.3 A 2.3 A 2.3 A 5.5 A 4.2 A
8SO PowerPAD 8SO PowerPAD
Pin and package 8SOIC 8SOIC 8SOIC integrated circuit integrated circuit
package package

8.2 Typical Application

L1 4.7 uH VOUT 5V, 5A
VOUT
C4
0.1µF
U1 D1 C8 C9 C10
TPS54531 R4
CDBC540-G
47µF 47µF open
0.55V 51.1
1 8
BOOT PH

VIN 8-28VOLTS
2 7
VIN VIN GND

C1 C2 C3 R1 3 6
EN COMP
665k
4.7µF 4.7µF 0.01µF C11
C6 R5
4 5
SS VSNS
2200pF 10.2K open
9 PWR PAD C7
C5 R3
R2 22pF
130k 0.01µF
37.4k R6

1.96k

Figure 8-1. Typical Application Schematic

8.2.1 Design Requirements

For this design example, use the values listed in Table 8-1 as the input parameters
Table 8-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 8 to 28 V
Output voltage 5V
Transient response, 2.5-A load step ΔVOUT = ±5%
Input ripple voltage 400 mV
Output ripple voltage 30 mV
Output current rating 5A
Operating Frequency 570 kHz

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8.2.2 Detailed Design Procedure

The following design procedure can be used to select component values for the TPS54531 device. Alternately,
the WEBENCH software can be used to generate a complete design. The WEBENCH software uses an iterative
design procedure and accesses a comprehensive database of components when generating a design. This
section presents a simplified discussion of the design process.
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the WEBENCH Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, users are able to:
• Run electrical simulations to see important waveforms and circuit performance,
• Run thermal simulations to understand the thermal performance of your board,
• Export your customized schematic and layout into popular CAD formats,
• Print PDF reports for the design, and share your design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Switching Frequency
The switching frequency for the TPS54531 is fixed at 570 kHz.
8.2.2.3 Output Voltage Set Point
The output voltage of the TPS54531 device is externally adjustable using a resistor divider network. As shown in
Figure 8-1, this divider network is comprised of R5 and R6. The relationship of the output voltage to the resistor
divider is given by Equation 4 and Equation 5:

R5 × V
REF
R6 = V (4)
OUT − VREF

VOUT = VREF × R5
R6 + 1 (5)

Select a value of R5 to be approximately 10 kΩ. Slightly increasing or decreasing the value of R5 can result in
closer output-voltage matching when using standard value resistors. In this design, R5 = 10.2 kΩ and R6 = 1.96
kΩ, resulting in a 4.96 V output voltage. The 51.1-Ω resistor, R4, is provided as a convenient location to break
the control loop for stability testing.
8.2.2.4 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) can be adjusted using the external voltage divider network of R1 and R2. R1
is connected between the VIN and EN pins of the TPS54531 device and R2 is connected between the EN and
GND pins. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the design example, the minimum input voltage is 8
V. Therefore the start voltage threshold is set to 7 V with 2-V hysteresis. Use Equation 1 and Equation 2 to
calculate the values for the upper and lower resistor values of R1 and R2.
8.2.2.5 Input Capacitors
The TPS54531 device requires an input decoupling capacitor and, depending on the application, a bulk input
capacitor. The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R
or X7R is recommended. The voltage rating must be greater than the maximum input voltage. A smaller value
can be used as long as all other requirements are met; however 10 μF has been shown to work well in a wide
variety of circuits. Additionally, some bulk capacitance can be required, especially if the TPS54531 circuit is not

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located within about 2 inches from the input voltage source. The value for this capacitor is not critical but must
be rated to handle the maximum input voltage including ripple voltage, and must filter the output so that input
ripple voltage is acceptable. For this design two 4.7-μF capacitors are used for the input decoupling capacitor.
The capacitors are X7R dielectric rated for 50 V. The equivalent series resistance (ESR) is approximately 2 mΩ
and the current rating is 3 A. Additionally, a small 0.01 μF capacitor is included for high frequency filtering.
Use Equation 6 to calculate the input ripple voltage.

IOUT MAX × 0.25

∆ VIN = CBULK × FSW + IOUT MAX × ESRMAX (6)

where
• IOUT(MAX) is the maximum load current
• CBULK is the bulk capacitor value
• FSW is the switching frequency
• ESRMAX is the maximum series resistance of the bulk capacitor
The maximum RMS ripple current must also be checked. For worst case conditions, use Equation 7 to calculate
the maximum-RMS input ripple current, ICIN(RMS).

IOUT MAX
ICIN RMS = 2 (7)

In this case, the input ripple voltage is 243 mV and the RMS ripple current is 2.5 A.

Note
The actual input voltage ripple is greatly affected by parasitics associated with the layout and the
output impedance of the voltage source.

The actual input voltage ripple for this circuit is listed in Table 8-1 and is larger than the calculated value.
This measured value is still below the specified input limit of 300 mV. The maximum voltage across the input
capacitors is VIN(MAX) + ΔVIN / 2. The selected bulk and bypass capacitors are each rated for 50 V and the ripple
current capacity is greater than 3 A, both providing ample margin. The maximum ratings for voltage and current
must not be exceeded under any circumstance.
8.2.2.6 Output Filter Components
Two components must be selected for the output filter, LOUT and COUT. Because the TPS54531 is an externally
compensated device, a wide range of filter component types and values can be supported.
8.2.2.6.1 Inductor Selection
To calculate the minimum value of the output inductor, use Equation 8

VOUT × VIN MAX − VOUT

LMIN = V (8)
IN MAX × KIND × IOUT × FSW

where
• KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output
current
In general, this value is at the discretion of the designer; however, the following guidelines can be used. For
designs using low-ESR output capacitors such as ceramics, a value as high as KIND = 0.3 can be used. When
using higher ESR output capacitors, KIND = 0.2 yields better results.
For this design example, use KIND = 0.3 and the minimum inductor value is calculated as 4.8 μH. For this design,
a close, standard value was chosen: 4.7 μH.

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For the output filter inductor, do not exceed the RMS current and saturation current ratings. Use Equation 9 to
calculate the inductor ripple current (IRIPPLE).

VOUT × VIN MAX − VOUT

IRIPPLE = V (9)
IN MAX × LOUT × FSW × 0.8

Use Equation 10 to calculate the RMS inductor current.

2
2 1 VOUT × VIN MAX − VOUT
IL RMS = IOUT MAX + 12 × V (10)
IN MAX × LOUT × FSW × 0.8

Use Equation 11 to calculate the peak inductor current.

VOUT × VIN MAX − VOUT

IL PK = IOUT MAX + 1.6 × V (11)
IN MAX × LOUT × FSW

For this design, the RMS inductor current is 5.03 A and the peak inductor current is 5.96 A. The selected
inductor is a Wurth 4.7 μH. This inductor has a saturation current rating of 19 A and an RMS current rating of
7 A, which meets these requirements. Smaller or larger inductor values can be used depending on the amount
of ripple current the designer wants to allow, so long as the other design requirements are met. Larger value
inductors have lower AC current and result in lower output voltage ripple, while smaller inductor values increase
AC current and output voltage ripple. In general, inductor values for use with the TPS54531 device are in the
range of 1 μH to 47 μH.
8.2.2.6.2 Capacitor Selection
Selecting the value of the output capacitor is based on three primary considerations. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance must be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor must supply
the load with current when the regulator can not. This situation occurs if desired hold-up times occur for the
regulator where the output capacitor must hold the output voltage above a certain level for a specified amount
of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output
current if a large, fast increase occurs in the current needs of the load, such as a transition from no load to
full load. The regulator usually requires two or more clock cycles for the control loop to respond to the change
in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must
be sized to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a
tolerable amount of drop in the output voltage. Use Equation 12 to calculate minimum output capacitance (CO)
required in this case.

2 × ∆I
CO > F × ∆OUT VOUT (12)
SW

where
• ΔIOUT is the change in output current
• FSW is the switching frequency of the regulator
• ΔVOUT is the allowable change in the output voltage
For this example, the transient load response is specified as a 5% change in VOUT for a load step of 2.5 A.
For this example, ΔIOUT = 2.5 A and ΔVOUT = 0.05 x 5 = 0.25 V. Using these values results in a minimum
capacitance of 35 μF. This value does not consider the ESR of the output capacitor in the output voltage change.
For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.

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Use Equation 13 to calculate the minimum output capacitance needed to meet the output voltage ripple
specification. In this case, the maximum output voltage ripple is 30 mV. Under this requirement Equation 13,
yields 14 µF.

CO > 8 × 1F × V 1
(13)
SW OUTRIPPLE
IRIPPLE

where
• FSW is the switching frequency
• VOUTRIPPLE is the maximum allowable output voltage ripple
• IRIPPLE is the inductor ripple current
Use Equation 14 to calculate the maximum ESR an output capacitor can have to meet the output-voltage ripple
specification. Equation 14 indicates the ESR must be less than 15.6 mΩ. In this case, the ESR of the ceramic
capacitor is much smaller than 15.6 mΩ.

V
RESR < OUTRIPPLE
I (14)
RIPPLE

Additional capacitance deratings for aging, temperature, and DC bias must be considered which increases
this minimum value. For this example, two 47-μF 10-V X5R ceramic capacitors with 3 mΩ of ESR are used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (root mean square) value of the maximum ripple current. Use Equation 15 to
calculate the RMS ripple current that the output capacitor must support. For this application, Equation 15 yields
554 mA.

VOUT × VIN MAX − VOUT

ICOUT RMS = 1 × V (15)
12 IN MAX × LOUT × FSW × NC

8.2.2.7 Compensation Components

Several possible methods exist to design closed loop compensation for DC/DC converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at –20 dB/decade above the modulator pole frequency. The power stage phase is
0 degrees at low frequencies and begins to fall one decade below the modulator pole frequency reaching a
minimum of –90 degrees one decade above the modulator pole frequency. Use Equation 16 to calculate the
modulator pole frequency.

IOUT MAX
FP_MOD = 2 × π × V (16)
OUT × COUT

For the TPS54531 device, most circuits have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics deviate from the ideal approximations. The phase
loss of the power stage now approaches –180 degrees, making compensation more difficult. The power
stage transfer function can be solved but requires a tedious calculation. Use the PSpice model to accurately
model the power-stage gain and phase so that a reliable compensation circuit can be designed. Alternately, a
direct measurement of the power stage characteristics can be used. That is the technique used in this design
procedure. For this design, the calculate values are as follows:
L1 = 4.7 µH
C8 and C9 = 47 µF (each)
ESR = 3 mΩ
Figure 8-2 shows the power stage characteristics.

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60 180
Gain
40 Power Stage 120
Gain = 5.1 dB
@ 20 kHz

Phase - Degrees
20 60

Gain - dB
0 0

-20 -60
Phase
-40 -120

-60 -180
10 100 1000 10000 100000 1000000
Frequency - Hz C011

Figure 8-2. Power Stage Gain and Phase Characteristics

For this design, the intended crossover frequency is 20 kHz. From the power stage gain and phase plots, the
gain at 20 kHz is 5.1 dB and the phase is about –100 degrees. For 60 degrees of phase margin, additional
phase boost from a feed-forward capacitor in parallel with the upper resistor of the voltage set point divider is not
needed. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at
crossover. Use Equation 17 to calculate the required value of R3.

−GPWRSTG
V
R3 = 10 gm20 × VOUT (17)
EA REF

To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 20 kHz.
Use Equation 18 to calculate the required value for C6.

1
C6 = FCO (18)
2 × π × R3 × 10

To maximize phase gain the high frequency pole is placed one decade above the crossover frequency of 20 kHz.
The pole can also be useful to offset the ESR of aluminum electrolytic output capacitors. Use Equation 19 to
calculate the value for C7.

C7 = 2 × π × R 1× 10 × F (19)
3 CO

For this design, the calculated values are as follows:

R3 = 37.4 kΩ
C6 = 2200 pF
C7 = 22 pF
8.2.2.8 Bootstrap Capacitor
Every TPS54531 design requires a bootstrap capacitor, C4. The bootstrap capacitor value must be 0.1 μF. The
bootstrap capacitor is located between the PH and BOOT pins. The bootstrap capacitor must be a high-quality
ceramic type with X7R or X5R grade dielectric for temperature stability.
8.2.2.9 Catch Diode
The TPS54531 device sis designed to operate using an external catch diode between the PH and GND pins.
The selected diode must meet the absolute maximum ratings for the application. The reverse voltage must
be higher than the maximum voltage at the PH pin, which is VIN(MAX) + 0.5 V. Peak current must be greater
than IO(MAX) plus on half the peak-to-peak inductor current. The forward-voltage drop must be small for higher
efficiencies. The catch diode conduction time is (typically) longer than the high-side FET on time, so attention

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paid to diode parameters can make a marked improvement in overall efficiency. Additionally, check that the
selected device is capable of dissipating the power losses. For this design, a CDBC540-G was selected, with a
reverse voltage of 40 V, forward current of 5 A, and a forward-voltage drop of 0.55 V.
8.2.2.10 Slow-Start Capacitor
The slow-start capacitor determines the minimum amount of time required for the output voltage to reach the
nominal programmed value during power up which is useful if a load requires a controlled voltage slew rate. The
slow-start capacitor is also used if the output capacitance is very large and requires large amounts of current to
quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor
can make the TPS54531 device reach the current limit. Excessive current draw from the input power supply can
cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. Use
Equation 3 to calculate the value of the slow-start capacitor. For the example circuit, the slow-start time is not too
critical because the output capacitor value is 2 × 47 μF which does not require much current to charge to 5 V.
The example circuit has the slow-start time set to an arbitrary value of 4 ms which requires a 10-nF capacitor.
For the TPS54531 device, ISS is 2 µA and Vref is 0.8 V.
8.2.2.11 Output Voltage Limitations
Because of the internal design of the TPS54531 device, any give voltage has both upper and lower output
voltage limits for any given input voltage. The upper limit of the output-voltage set point is constrained by the
maximum duty cycle of 91% and is calculated with Equation 20. The equation assumes the maximum ON
resistance for the internal high-side FET.

VO MAX = 0.91 × VIN MIN − IO MAX × RDS ON MAX + VD − IO MAX × RL − VD (20)

where
• VIN(MIN) = Minimum input voltage
• IO(MAX) = Maximum load current
• VD = Catch diode forward voltage
• RL = Output inductor series resistance
The lower limit is constrained by the minimum controllable on time which can be as high as 130 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by Equation
21.

VO MIN = 0.089 × VIN MAX − IO MIN × RDS ON MIN + VD − IO MIN × RL − VD (21)

where
• VIN(MAX) = Maximum input voltage
• IO(MIN) = Minimum load current
• VD = Catch diode forward voltage
• RL = Output inductor series resistance
This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device must be carefully
checked to ensure proper functionality.
8.2.2.12 Power Dissipation Estimate
The following formulas show how to estimate the device power dissipation under continuous-conduction mode
(CCM) operations. These formulas must not be used if the device is working in the discontinuous-conduction
mode (DCM) or pulse-skipping Eco-mode.
The device power dissipation includes:
1. Conduction loss:

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Pcon = IOUT 2 × RDS(on) × VOUT / VIN

• where
• IOUT is the output current (A)
• RDS(on) is the on-resistance of the high-side MOSFET (Ω)
• VOUT is the output voltage (V)
• VIN is the input voltage (V)
2. Switching loss:
Psw = 0.5 × 10–9 × VIN 2 × IOUT × ƒSW

• where
• ƒSW is the switching frequency (Hz)
3. Gate charge loss:
Pgc = 22.8 × 10-9 × ƒSW
4. Quiescent current loss:
Pq = 0.11 × 10-3 × VIN

Therefore:

Ptot = Pcon + Psw + Pgc + Pq

where
• Ptot is the total device power dissipation (W)
For given TA:

TJ = TA + Rth × Ptot

where
• TJ is the junction temperature (°C)
• TA is the ambient temperature (°C)
• Rth is the thermal resistance of the package (°C/W)
For given TJMAX = 150°C:

TAMAX = TJMAX– Rth × Ptot

where
• TJMAX is maximum junction temperature (°C)
• TAMAX is maximum ambient temperature (°C)

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8.2.3 Application Curves

100 100
90 90 VIN = 12 V

80 80
70 VIN = 12 V 70
VIN = 24 V
Efficiency - %

Efficiency - %
60 60
50 50 VIN = 24 V
40 40
30 30
20 20
10 10
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.001 0.01 0.1 1 10
Output Current - A C007 Output Current - A C008

Figure 8-3. Efficiency Figure 8-4. Low-Current Efficiency

0.20 0.1

0.15 0.08
0.06
0.10 VIN = 12 V
Load Regulation - %

Line Regulation - %
0.04 IOUT = 2.5 A
0.05 0.02
0.00 0

-0.05 -0.02

VIN = 24 V -0.04
-0.10
-0.06
-0.15 -0.08
-0.20 -0.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 8 10 12 14 16 18 20 22 24 26 28
Output Current - A C009 Input Voltage - V C010

Figure 8-5. Load Regulation Figure 8-6. Line Regulation

60 180

40 120
VOUT = 200 mV/div (ac coupled) Phase

Phase - Degrees
20 60
Gain - dB

0 0

IOUT = 1 A/div -20 Gain -60

-40 -120

1.25 A to 3.75 A load step, -60 -180

slew rate = 500 mA / µsec 10 100 1000 10000 100000 1000000
Frequency - Hz C011

Figure 8-8. Loop Response

Time = 200 µs/div

Figure 8-7. Transient Response

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VOUT = 20 mV/div (ac coupled) VOUT = 20 mV/div (ac coupled)

PH = 5 V/div PH = 5 V/div

Time = 1 µs/div Time = 500 µs/div

Figure 8-9. Full-Load Output Ripple Figure 8-10. Eco-mode Output Ripple

VIN = 200 mV/div (ac coupled)

VIN = 10 V/div

EN = 2 V/div

PH = 5 V/div
SS = 2 V/div

VOUT = 2 V/div

Time = 1 µs/div Time = 2 ms/div

Figure 8-11. Full-Load Input Ripple Figure 8-12. Startup Relative to VIN

VIN = 10 V/div VIN = 10 V/div

EN = 2 V/div

EN = 2 V/div

SS = 2 V/div

SS = 2 V/div
VOUT = 2 V/div

VOUT = 2 V/div

Time = 2 ms/div Time = 5 ms/div

Figure 8-13. Startup Relative to Enable Figure 8-14. Shut Down Relative to VIN

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VIN = 10 V/div

EN = 2 V/div

SS = 2 V/div

VOUT = 2 V/div

Time = 5 ms/div
Figure 8-15. Shut Down Relative to EN

8.3 Power Supply Recommendations

The device is designed to operate from an input-voltage supply range between 3.5 V and 28 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter additional bulk
capacitance can be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value
of 100 μF is a typical choice.
8.4 Layout
8.4.1 Layout Guidelines
The VIN pin must be bypassed to ground with a low-ESR ceramic bypass capacitor. Care must be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch
diode. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the
optimum placement is closest to the VIN pins and the source of the anode of the catch diode. Figure 8-16 shows
a PCB layout example. The GND pin must be tied to the PCB ground plane at the pin of the device. The PH
pin must be routed to the cathode of the catch diode and to the output inductor. Because the PH connection
is the switching node, the catch diode and output inductor must be located very close to the PH pins, and the
area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load,
the exposed thermal pad must be soldered directly to the top-side ground area under the device. Use thermal
vias to connect the top-side ground area to an internal or bottom-layer ground plane. The total copper area must
provide adequate heat dissipation. Additional vias adjacent to the device can be used to improve heat transfer
to the internal or bottom-layer ground plane . The additional external components can be placed approximately
as shown. Obtaining acceptable performance with alternate layout schemes can be possible, however this layout
has been shown to produce good results and is intended as a guideline.

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8.4.2 Layout Example

OUTPUT Vout
TOPSIDE FILTER Feedback Trace
CAPACITOR
GROUND
AREA
Route BOOT CAPACITOR CATCH OUTPUT
trace on other layer to provide DIODE INDUCTOR
wide path for topside ground
PH
INPUT
BYPASS
CAPACITOR BOOT
BOOT PH CAPACITOR

VIN GND
Vin
EN COMP

UVLO
RESISTOR SS VSENSE
DIVIDER
COMPENSATION RESISTOR
SLOW START NETWORK DIVIDER
CAPACITOR

EXPOSED
THERMAL PAD

Thermal VIA Signal VIA

Figure 8-16. TPS54531DDA Board Layout

8.4.3 Electromagnetic Interference (EMI) Considerations

As EMI becomes a rising concern in more and more applications, the internal design of the TPS54531 device
includes features to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage
ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used
to lower the parasitics effects.
To achieve the best EMI performance, external component selection and board layout are equally important.
Follow the steps listed in the Section 8.2.2 section to prevent potential EMI issues.

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9 Device and Documentation Support

9.1 Device Support
9.1.1 Development Support
9.1.1.1 Custom Design With WEBENCH® Tools
Create a custom design with the TPS54531 using the WEBENCH® Power Designer
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer gives a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
SWIFT™, PowerPAD™, and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS54531DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 54531 Samples

TPS54531DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 54531 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 7-Nov-2023

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Dec-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS54531DDA DDA HSOIC 8 75 517 7.87 635 4.25
TPS54531DDA DDA HSOIC 8 75 507 8 3940 4.32

Pack Materials-Page 1
 GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4202561/G
 PACKAGE OUTLINE
DDA0008B SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8
A
PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.4 0.25
9 GAGE PLANE
2.8

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.71 TYPICAL
2.11

4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
(2.71) SOLDER MASK
DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)

(3.4)
SYMM 9 SOLDER MASK
(1.3)
TYP OPENING

(4.9)
NOTE 9
6X (1.27)

4 5
(R0.05) TYP
SYMM METAL COVERED
( 0.2) TYP BY SOLDER MASK
VIA
(1.3) TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-8

4214849/A 08/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55) (R0.05) TYP
1
8

8X (0.6)

(3.4)
SYMM 9 BASED ON
0.125 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED
SYMM SEE TABLE FOR
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.4)
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.03 X 3.80
0.125 2.71 X 3.40 (SHOWN)
0.150 2.47 X 3.10
0.175 2.29 X 2.87

4214849/A 08/2016

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
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