TPS5430

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5.5-V to 36-V, 3-A STEP-DOWN SWIFT™ CONVERTER

FEATURES APPLICATIONS
• Wide Input Voltage Range: 5.5 V to 36 V • Consumer: Set-top Box, DVD, LCD Displays
• Up to 3-A Continuous (4-A Peak) Output • Industrial and Car Audio Power Supplies
Current • Battery Chargers, High Power LED Supply
• High Efficiency up to 95% Enabled by 110-mΩ • 12V/24V Distributed Power Systems
Integrated MOSFET Switch
• Wide Output Voltage Range: Adjustable Down DESCRIPTION
to 1.22 V with 1.5% Initial Accuracy As a member of the SWIFT™ family of DC/DC
• Internal Compensation Minimizes External regulators, the TPS5430 is a high-output-current
Parts Count PWM converter that integrates a low resistance high
side N-channel MOSFET. Included on the substrate
• Fixed 500 kHz Switching Frequency for Small with the listed features are a high performance
Filter Size voltage error amplifier that provides tight voltage
• Improved Line Regulation and Transient regulation accuracy under transient conditions; an
Response by Input Voltage Feed Forward under-voltage-lockout circuit to prevent start-up until
• System Protected by Over Current Limiting the input voltage reaches 5.5V; an internally set
slow-start circuit to limit inrush currents; and a voltage
and Thermal Shutdown
feed-forward circuit to improve the transient
• –40°C to 125°C Operating Junction response. Other features include an active high
Temperature Range enable, over current protection and thermal
• Available in Small Thermally Enhanced 8-Pin shutdown. To reduce design complexity and external
SOIC PowerPAD™ Package component count, the TPS5430 feedback loop is
internally compensated.
• For SWIFT Documentation, Application Notes
and Design Software, See the TI Website at The TPS5430 device is available in a thermally
www.ti.com/swift enhanced, easy to use 8-pin SOIC PowerPAD™
package. TI provides evaluation modules and the
SWIFT™ Designer software tool to aid in quickly
achieving high-performance power supply designs to
meet aggressive equipment development cycles.

100
SIMPLIFIED SCHEMATIC
95

VIN VOUT 90
VIN PH
85
TPS5430
Efficiency − %

80
NC BOOT
75

NC 70

65
ENA VSENSE
60 VI = 12 V,
GND
V0 = 5 V,
55 fs = 500 kHz

50
0 0.5 1 1.5 2 2.5 3 3.5
I − Output Current − A
O

Efficiency vs Output Current

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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SLVS632 – JANUARY 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION
TJ OUTPUT VOLTAGE PACKAGE PART NUMBER
–40°C to 125°C Adjustable to 1.22 V Thermally Enhanced SOIC (DDA) (1) TPS5430DDA

(1) The DDA package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS5430DDAR). See applications section
of data sheet for PowerPAD™ drawing and layout information.

ABSOLUTE MAXIMUM RATINGS

(1) (2)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
VIN –0.3 to 38
ENA –0.3 to 7
VSENSE –0.3 to 3
VI Input voltage range BOOT –0.3 to 48 V
BOOT-PH 10
PH (steady-state) –0.6 to 38
PH (transient < 10 ns) –1.2
IO Source current PH Internally Limited
IO Leakage current PH 10 µA
TJ Operating virtual junction temperature range –40 to 125 °C
TSTG Storage temperature –65 to 150 °C
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds 300 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

DISSIPATION RATINGS (1) (2)

PACKAGE THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
8 Pin DDA (2-layer board with solder) (3) 33°C/W
8 Pin DDA (4-layer board with solder) (4) 26°C/W

(1) Maximum power dissipation may be limited by overcurrent protection.

(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where
distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125°C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more
information.
(3) Test board conditions:
a. 3 in x 3 in, 2 layers, thickness: 0.062 inch.
b. 2 oz. copper traces located on the top and bottom of the PCB.
c. 6 thermal vias in the PowerPAD area under the device package.
(4) Test board conditions:
a. 3 in x 3 in, 4 layers, thickness: 0.062 inch.
b. 2 oz. copper traces located on the top and bottom of the PCB.
c. 2 oz. copper ground planes on the 2 internal layers.
d. 6 thermal vias in the PowerPAD area under the device package.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT
VIN Input voltage range 5.5 36 V
TJ Operating junction temperature –40 125 °C

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ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 5.5 V to 36.0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN Input voltage range 5.5 36 V
VSENSE = 2 V, Not switching, PH pin
3 4.4 mA
IQ Quiescent current open
Shutdown, ENA = 0 V 18 50 µA
UNDER VOLTAGE LOCK OUT (UVLO)
Start threshold voltage, UVLO 5.3 5.5 V
Hysteresis voltage, UVLO 330 mV
VOLTAGE REFERENCE
TJ = 25°C 1.202 1.221 1.239
Voltage reference accuracy V
Io = 0 A – 3 A 1.196 1.221 1.245
OSCILLATOR
Internally set free-running frequency 400 500 600 kHz
Minimum controllable on time 150 200 ns
Maximum duty cycle 87 89 %
ENABLE (ENA PIN)
Start threshold voltage, ENA 1.3 V
Stop threshold voltage, ENA 0.5 V
Hysteresis voltage, ENA 450 mV
Internal slow-start time (0~100%) 6.6 8 10 ms
CURRENT LIMIT
Current limit 4.0 5.0 6.0 A
Current limit hiccup time 13 16 20 ms
THERMAL SHUTDOWN
Thermal shutdown trip point 135 162 °C
Thermal shutdown hysteresis 14 °C
OUTPUT MOSFET
VIN = 5.5 V 150
RDS-ON High side power MOSFET switch mΩ
VIN = 10 V – 36 V 110 230

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PIN ASSIGNMENTS
DDA PACKAGE
(TOP VIEW)

BOOT 1 8 PH

NC 2 PowerPAD 7 VIN
(Pin 9)
NC 3 6 GND

VSENSE 4 5 ENA

TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME NO.
BOOT 1 Boost capacitor for the high-side FET gate driver. Connect 0.01 µF low ESR capacitor from BOOT pin to PH pin.
NC 2, 3 Not connected internally.
VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider.
ENA 5 On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.
GND 6 Ground. Connect to PowerPAD.
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR ceramic
VIN 7
capacitor.
PH 8 Source of the high side power MOSFET. Connected to external inductor and diode.
PowerPAD 9 GND pin must be connected to the exposed pad for proper operation.

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TYPICAL CHARACTERISTICS

OSCILLATOR FREQUENCY NON-SWITCHING QUIESCENT CURRENT

vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
530 3.5

520
f − Oscillator Frequency − kHz

I Q − Quiescent Current − mA
3.25
510

500
3
490

480
2.75

470

460 2.5
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
T − Junction Temperature − °C TJ − Junction Temperature − °C

Figure 1. Figure 2.

SHUTDOWN QUIESCENT CURRENT VOLTAGE REFERENCE

vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE
25 1.230
ENA = 0 V
−µ A

VREF - Voltage Reference - V

20 T J = 125°C 1.225
I SD −Shutdown Current

15 T J = 27°C 1.220

T J = –40°C
10 1.215

5 1.210
0 5 10 15 20 25 30 35 40 -50 -25 0 25 50 75 100 125
V I −Input V oltage −V TJ - Junction Temperature - °C

Figure 3. Figure 4.

ON RESISTANCE INTERNAL SLOW START TIME

vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
180 9
V I = 12 V
170
TSS − Internal Slow Start Time − ms
DS(on) −On Resistance −mΩ

160
8.5
150

140
8
130

120

110 7.5
r

100

90
7
80 −50 −25 0 25 50 75 100 125
−50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C
T J −Junction Temperature − °C

Figure 5. Figure 6.

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TYPICAL CHARACTERISTICS (continued)

MINIMUM CONTROLLABLE ON TIME MINIMUM CONTROLLABLE DUTY RATIO

vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
180 8
Minimum Controllable On Time − ns

170
7.75

Minimum Duty Ratio - %

160

150 7.50

140
7.25

130

7
120 -50 -25 0 25 50 75 100 125
−50 −25 0 25 50 75 100 125 TJ - Junction Temperature - °C
TJ − Junction Temperature − °C

Figure 7. Figure 8.

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APPLICATION INFORMATION

FUNCTIONAL BLOCK DIAGRAM

VIN

VIN

1.221 V Bandgap VREF SHDN Boot

UVLO Slow Start Regulator BOOT
Reference
HICCUP
5 µA
ENA ENABLE SHDN SHDN
VSENSE
Z1

Thermal
SHDN Error
Protection SHDN Z2
Amplifier

Ramp
NC VIN
Generator Feed Forward
Gain = 25

NC PWM HICCUP
SHDN
Comparator

GND Overcurrent
SHDN Oscillator Protection

SHDN
Gate Drive
Control
POWERPAD Gate
Driver
SHDN
TPS5430

BOOT PH

VOUT

DETAILED DESCRIPTION

Oscillator Frequency
The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switching
frequency allows less output inductance for the same output ripple requirement resulting in a smaller output
inductor.

Voltage Reference
The voltage reference system produces a precision reference signal by scaling the output of a temperature
stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of
1.221 V at room temperature.

Enable (ENA) and Internal Slow Start

The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold
voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled
below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin
to ground or to any voltage less than 0.5 V will disable the regulator and activate the shutdown mode. The
quiescent current of the TPS5430 in shutdown mode is typically 18 µA.
The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application
requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit
the start-up inrush current, an internal slow start circuit is used to ramp up the reference voltage from 0 V to its
final value linearly. The internal slow start time is 8ms typically.

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APPLICATION INFORMATION (continued)

Undervoltage Lockout (UVLO)
The TPS5430 incorporates an under voltage lockout circuit to keep the device disabled when VIN (the input
voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive until VIN
exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, device start-up
begins. The device operates until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the
UVLO comparator is 330 mV.

Boost Capacitor (BOOT)

Connect a 0.01 µF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.

Output Feedback (VSENSE) and Internal Compensation

The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage
reference 1.221 V.
The TPS5430 implements internal compensation to simplify the regulator design. Since the TPS5430 uses
voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. Refer to Internal Compensation Network in the applications
section for more details.

Voltage Feed Forward

The internal voltage feed forward provides a constant DC power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain, i.e.
Feed Forward Gain  VIN
Ramp
pk
pk (1)
The typical feed forward gain of TPS5430 is 25.

Pulse-Width-Modulation (PWM) Control

The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback
voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier and
compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by the
PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty cycle.
Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET.

Overcurrent Protection
Overcurrent protection is implemented by sensing the drain-to-source voltage across the high-side MOSFET.
The drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent protection is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent protection scheme is called cycle-by-cycle current
limiting.
If the sensed current continues to increase during cycle-by-cycle current limiting, the hiccup mode overcurrent
protection will be triggered instead of cycle-by-cycle current limiting. During hiccup mode overcurrent protection,
the voltage reference is grounded and the high-side MOSFET is turned off for the hiccup time. Once the hiccup
time duration is complete, the regulator restarts under control of the slow start circuit.

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APPLICATION INFORMATION (continued)

Thermal Shutdown
The TPS5430 protects itself from overheating with an internal thermal shutdown circuit. If the junction
temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side
MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction
temperature drops 14°C below the thermal shutdown trip point.

PCB Layout
Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area
formed by the bypass capacitor connections, the VIN pin, and the TPS5430 ground pin. The best way to do this
is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass
capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 10 uF ceramic
with a X5R or X7R dielectric.
There should be a ground area on the top layer directly underneath the IC, with an exposed area for connection
to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the
ground side of the input and output filter capacitors as well. The GND pin should be tied to the PCB ground by
connecting it to the ground area under the device as shown below.
The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is
the switching node, the inductor should be located very close to the PH pin and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device to
minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as
shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component
placements and connections shown work well, but other connection routings may also be effective.
Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the
loop formed by the PH pin, Lout, Cout and GND as small as is practical.
Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not
route this trace too close to the PH trace. Due to the size of the IC package and the device pin-out, the trace
may need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if a
trace under the output capacitor is not desired.
If the grounding scheme shown is utilized, use a via connection to a different layer to route to the ENA pin.

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APPLICATION INFORMATION (continued)

PH
CATCH
DIODE
BOOT
CAPACITOR
INPUT INPUT
BYPASS BULK
BOOT PH CAPACITOR FILTER
OUTPUT
INDUCTOR
NC VIN
Vin

NC GND

RESISTOR VSENSE ENA

DIVIDER

VOUT OUTPUT
FILTER TOPSIDE GROUND AREA
CAPACITOR

Route feedback
VIA to Ground Plane
trace under output
filter capacitor or on Signal VIA
other layer

Figure 9. Design Layout

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APPLICATION INFORMATION (continued)

0.110
0.220

0.080
0.050

0.026
0.050
0.118

0.013 DIA 4 PL 0.040

0.098

All dimensions in inches

Figure 10. TPS5430 Land Pattern

Application Circuits
Figure 11 shows the schematic for a typical TPS5430 application. The TPS5430 can provide up to 3-A output
current at a nominal output voltage of 5.0 V. For proper thermal performance the exposed PowerPAD
underneath the device must be soldered down to the printed circuit board.
U1
TPS5430DDA C2 L1
10.8 - 19.8 V 7 0.01 mF 15 mH
VIN VIN 1 5V
5 BOOT VOUT
EN ENA
C1 2 8
NC PH D1 + C3
10 mF 3 R1
NC 4 B340A 220 mF 10 kW
6 VSNS
GND
PwPd
9
R2
3.24 kW

Figure 11. Application Circuit, 12-V to 5.0-V

Design Procedure
The following design procedure can be used to select component values for the TPS5430. Alternately, the
SWIFT Designer Software may be used to generate a complete design. The SWIFT Designer Software uses an
iterative design procedure and accesses a comprehensive database of components when generating a design.
This section presents a simplified discussion of the design process.
To begin the design process a few parameters must be decided upon. The designer needs to know the following:

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APPLICATION INFORMATION (continued)

• Input voltage range
• Output voltage
• Input ripple voltage
• Output ripple voltage
• Output current rating
• Operating frequency

Design Parameters
For this design example, use the following as the input parameters:
DESIGN PARAMETER (1) EXAMPLE VALUE
Input voltage range 10.8 V to 19.8 V
Output voltage 5.0 V
Input ripple voltage 300 mV
Output ripple voltage 30 mV
Output current rating 3A
Operating frequency 500 kHz

(1) As an additional constraint, the design is set up to be small size and low component height.

Switching Frequency
The switching frequency for the TPS5430 is internally set to 500 kHz. It is not possible to adjust the switching
frequency.

Input Capacitors
The TPS5430 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
The recommended value for the decoupling capacitor, C1, is 10 µF. A high quality ceramic type X5R or X7R is
required. For some applications a smaller value decoupling capacitor may be used, so long as the input voltage
and current ripple ratings are not exceeded. The voltage rating must be greater than the maximum input voltage,
including ripple.
This input ripple voltage can be approximated by Equation 2 :
I OUT(MAX)
0.25

VIN 
C BULK
ƒ sw

 I OUT(MAX)
ESR MAX 
(2)
Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CIN is the input capacitor value and
ESRMAX is the maximum series resistance of the input capacitor.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be
approximated by Equation 3 :
I
OUT(MAX)
I

CIN 2 (3)
In this case the input ripple voltage would be 156 mV and the RMS ripple current would be 1.5 A. The maximum
voltage across the input capacitors would be VIN max plus delta VIN/2. The chosen input decoupling capacitor is
rated for 25 V and the ripple current capacity is greater than 3 A, providing ample margin. It is very important that
the maximum ratings for voltage and current are not exceeded under any circumstance.
Additionally some bulk capacitance may be needed, especially if the TPS5430 circuit is not located within about
2 inches from the input voltage source. The value for this capacitor is not critical but it also should be rated to
handle the maximum input voltage including ripple voltage and should filter the output so that input ripple voltage
is acceptable.

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Output Filter Componts

Two components need to be selected for the output filter, L1 and C2. Since the TPS5430 is an internally
compensated device, a limited range of filter component types and values can be supported.

Inductor Selection
To calculate the minimum value of the output inductor, use Equation 4:

OUT(MAX)
V
V
IN(MAX)
 V
OUT
 
L 
MIN V
K
I
F
IN(max) IND OUT SW (4)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
Three things need to be considered when determining the amount of ripple current in the inductor: the peak to
peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current
and the amount of ripple current determines at what point the circuit will become discontinuous. For designs
using the TPS5430, KIND of 0.2 to 0.3 yields good results. Low output ripple voltages can be obtained when
paired with the proper output capacitor, the peak switch current will be well below the current limit set point and
relatively low load currents can be sourced before dicontinuous operation.
For this design example use KIND = 0.2 and the minimum inductor value is calculated to be 12.5µH. The next
highest standard value is 15 µH, which is used in this design.
For the output filter inductor it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 5:
2

I
L(RMS)
  I2 
1
OUT(MAX) 12

 V
V
OUT
IN(MAX)

L


V IN(MAX)  V

OUT

F
SW
OUT

0.8


(5)
and the peak inductor current can be determined with Equation 6:
V
OUT


V IN(MAX)  V
OUT

I L(PK)  I 
OUT(MAX) 1.6
V IN(MAX)
L
F
OUT SW (6)
For this design, the RMS inductor current is 3.003 A, and the peak inductor current is 3.31 A. The chosen
inductor is a Sumida CDRH104R-150 15µH. It has a saturation current rating of 3.4 A and a RMS current rating
of 3.6 A, easily meeting these requirements. A lesser rated inductor could be used, however this device was
chosen because of its low profile component height. In general, inductor values for use with the TPS5430 are in
the range of 10 µH to 100 µH.

Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because along with the inductor ripple current it determines the amount of output ripple voltage. The actual value
of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the
desired closed loop crossover frequency of the design and LC corner frequency of the output filter. Due to the
design of the internal compensation, it is desirable to keep the closed loop crossover frequency in the range 3
kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this design
example, it is assumed that the intended closed loop crossover frequency will be between 2590 Hz and 24 kHz
and also below the ESR zero of the output capacitor. Under these conditions the closed loop crossover
frequency will be related to the LC corner frequency by:
2
f LC
f CO

85 VOUT (7)

And the desired output capacitor value for the output filter to:

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C OUT  1
3357
L OUT
f CO
V OUT
(8)
For a desired crossover of 18 kHz and a 15-µH inductor, the calculated value for the output capacitor is 220 µF.
The capacitor type shold be chosen so that the ESR zero is above the loop crossover. The maximum ESR
should be: (Add new equation)
ESR MAX  1
2

C OUT
f CO
(9)

The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data sheet will result in an acceptable output
ripple voltage:

ESRMAX
VOUT
VIN(MAX)  V OUT 

V p−p(MAX) 
NC
VIN(MAX)
LOUT
F SW
(10)
Where:
∆ VP-P is the desired peak-to-peak output ripple.
NC is the number of parallel output capacitors.
FSW is the switching frequency.
For this design example, a single 220-µF output capacitor is chosen for C3. The calculated RMS ripple current is
143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo
Poscap 10TPB220M, rated at 10 V with a maximum ESR of 40 mΩ and a ripple current rating of 3.0 A. An
additional small 0.1-µF ceramic bypass capacitor may also used, but is not included in this design.
The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero
when the ESR is at a minimum should not be too far above the internal compensation poles at 24 and 54 kHz.
The selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one
half the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 11:

 
VOUT
VIN(MAX)  V OUT 
ICOUT(RMS)  1
 
12 V
L
F
N
IN(MAX) OUT SW C

(11)
Where:
NC is the number of output capacitors in parallel.
FSW is the switching frequency.
Other capacitor types can be used with the TPS5430, depending on the needs of the application.

Output Voltage Setpoint

The output voltage of the TPS5430 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin.
Calculate the R2 resistor value for the output voltage of 5.0 V using Equation 12:
R2  R1
1.221
V  1.221
OUT (12)
For any TPS5430 design, start with an R1 value of 10 kΩ. R2 is then 3.24 kΩ.

Boot Capacitor
The boot capacitor should be 0.01 µF.

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SLVS632 – JANUARY 2006

Catch Diode
The TPS5430 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the
peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note
that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage
of 40 V, forward current of 3 A, and a forward voltage drop of 0.5V.

Additional Circuits
Figure 12 shows an application circuit utilizing a wide input voltage range. The design parameters are simillar to
those given for the design example, with a larger value output inductor and a lower closed loop crosover
frequency.
U1
TPS5430DDA C2 L1
12–35 V 7 0.01 mF 22 mH 5V
VIN VIN 1
5 BOOT VOUT
EN ENA
C1 2 8
NC PH + C3
10 mF 3 D1
NC 4 220 mF R1
6 10 kW
GND VSNS
PwPd SBL845
9
R2
3.24 kW

Figure 12. 12-35 V Input to 5 V Output Application Circuit

ADVANCED INFORMATION

Output Voltage Limitations

Due to the internal design of the TPS5430, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87%
and is given by:
V OUTMAX  0.87
VINMIN  I OMAX
0.230  VD  I OMAX
RL  VD
(13)
Where
VINMIN = minimum input voltage
IOMAX = maximum load current
VD = catch diode forward voltage.
RL= output inductor series resistance.
This equation assumes maximum on resistance for the internal high side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 200nsec. The
approximate minimum output voltage for a given input voltage and minimum load current is given by:
V OUTMIN  0.12
VINMAX  I OMIN
0.110  VD  I OMIN
RL  VD
(14)
Where
VINMAX = maximum input voltage
IOMIN = minimum load current
VD = catch diode forward voltage.
RL= output inductor series resistance.

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TPS5430

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SLVS632 – JANUARY 2006

This equation assumes nominal on resistance for the high side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be
carefully checked to assure proper functionality.

Internal Compensation Network

The design equations given in the example circuit can be used to generate circuits using the TPS5430. These
designs are based on certain assumptions and will tend to always select output capacitors within a limited range
of ESR values. If a different capacitor type is desired, it may be posssible to to fit one to the internal
compensation of the TPS5430. Equation 15 gives the nominal frequency response of the internal voltage-mode
type III compensation network:

1 s  

1 s 
2

Fz1 2

Fz2
H(s) 
 s  

1 s  

1 s  

1 s 
2

Fp0 2

Fp1 2

Fp2 2

Fp3 (15)
Where
Fp0 = 2165 Hz, Fz1 = 2170 Hz, Fz2 = 2590 Hz
Fp1 = 24 kHz, Fp2 = 54 kHz, Fp3 = 440 kHz
Fp3 represents the non-ideal parasitics effect.
Using this information along with the desired output voltage, feed forward gain and output filter characteristics,the
closed loop transfer function can be derived.

Thermal Calculations
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working at light loads in the discontinuous conduction mode.
Conduction Loss: Pcon=Io2× Rds,on × VOUT/VIN
Switching Loss: Psw = VIN × IOUT × 0.01
Quiescent Current Loss: Pq = VIN × 0.01
Total Loss: Ptot = Pcon + Psw + Pq
Given TA => Estimated Junction Temperature: TJ = TA + Rth × Ptot
Given TJMAX = 125°C => Estimated Maximum Ambient Temperature: TAMAX = TJMAX– Rth x Ptot

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 TPS5430

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SLVS632 – JANUARY 2006

PERFORMANCE GRAPHS
The performance graphs in Figures 12 - 18 are applicable to the circuit in Figure 10. Ta = 25 °C. unless
otherwise specified.

100 0.3

VI = 10.8 V 0.2
95 VI = 12 V
VI = 15 V

Output Regulation - %
0.1
Efficiency - %

90

VI = 19.8 V 0
VI = 18 V
85
-0.1

80
-0.2

75 -0.3
0 0.5 1 1.5 2 2.5 3
0 0.5 1 1.5 2 2.5 3 3.5
IO - Output Current - A IO - Output Current - A

Figure 13. Efficiency vs. Output Current Figure 14. Output Regulation % vs. Output Current

0.1
VIN = 100 mV/Div (AC Coupled)
0.08

0.06

0.04 IO = 3 A IO = 1.5 A
Input Regulation - %

0.02

0 PH = 5 V/Div

-0.02
IO = 0 A
-0.04

-0.06

-0.08
-0.1
10.8 13.8 16.8 19.8 t -Time - 500 ns/Div
VI - Input Voltage - V

Figure 15. Input Regulation % vs. Input Voltage Figure 16. Input Voltage Ripple and PH Node, Io = 3 A.

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SLVS632 – JANUARY 2006

VOUT = 20 mV/Div (AC Coupled) VOUT = 50 mV/Div (AC Coupled)

PH = 5 V/Div IOUT = 1 A /Div

t - Time = 500 ns/Div t - Time = 200 ms/Div

Figure 17. Output Voltage Ripple and PH Node, Io = 3 A Figure 18. Transient Response, Io Step 0.75 to 2.25 A.

VIN = 5 V/Div

VOUT = 2 V/Div

t - Time = 2 ms/Div
Figure 19. Startup Waveform, Vin and Vout.

18
 PACKAGE OPTION ADDENDUM
www.ti.com 10-Feb-2006

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TPS5430DDA ACTIVE SO DDA 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
TPS5430DDAG4 ACTIVE SO DDA 8 75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
TPS5430DDAR ACTIVE SO DDA 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
TPS5430DDARG4 ACTIVE SO DDA 8 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Power no Sb/Br)
PAD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

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to Customer on an annual basis.

Addendum-Page 1
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