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3.1 Bit Logic Instructions

Bit logic Instructions are also called as relay logic instruction as they can execute commands which can
replace the function of a relay logic circuit.
The normally open contact and normally close contact of a relay logic circuit can be replaced by bit logic
instructions. In programming, they are called as Scan for“0” and Scan for “1”.
This chapter discusses the following bit logic instruction:
And Operation (A)
OR Operation (O)
Exclusive OR Operation (X)
And Not Operation (AN)
OR Not Operation (ON)
Exclusive –Not Operation (XN)

And Operation:
AND operation is nothing but one or more than one NO/NC contact connected in series. AND operation
checks whether the state of the addressed bit is "1"or “0” and Ands the test result with the RLO. You can
use AND (A) instruction to check the signal state for a scan for zero or one. If the normally open relay
contact (I 0.0 = 0) is open, the check result is ‘0’, if it is closed the result is ‘1’.In AND operation all the
inputs has to be high to activate the output coil.
Format of AND Instruction: A (op-code) I (operand identifier) 0.0 (address)
The below figure shows an example with all three representation (i.e. LAD / FBD / STL) that uses an AND
instruction to program two normally open contacts in series.

Ladder Program FBD Program STL Program Relay Logic cct.

I 0.0 I 0.1 Q 4.0 I 0.0

A I 0.0 I 0.0
I 0.1 & Q 4.0
A I 0.1
= I 0.1

= Q 4.0 Q 4.0

The AND instruction can also be used directly to check the status word bits for 0 and 1 value directly by
use of their addresses:
Example : A OV, A >0, A <>0 , A OS, A UO , A BR , A ==0 etc.

OR Operation:
OR operation is nothing but one or more than one NO/NC contact connected in parallel. OR operation
checks whether the state of the addressed bit is "1"or “0” and ORs the test result with the RLO. You can
use an OR ( O ) instruction to check the signal state of a normally open contact. If the normally open relay

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contact (I 0.0 =0)is open the check result is ‘0’, if it is closed the result is ‘1’. In OR operation any one of the
input will activate the output.
Format of OR Instruction: O (op-code) I (operand identifier) 0.0 (address)
The below figure shows an example with all three representation (i.e. LAD / FBD / STL) that uses an OR
instruction to program two normally open contacts in parallel.

Ladder ProgramFBD Program STL Program Relay Logic cct.

I 0.0 Q 4.0 I 0.0 I 0.1

I 0.0 O I 0.0
1
Q 4.0 O I 0.1
I 0.1 I 0.1
Q 4.0
=
= Q 4.0

The OR instruction can also be used directly to check the following status word bits by their addresses:
Example: O OV, O >0, O <>0, O OS, O UO , O BR , O ==0 etc.

And Not, Or not Operation:

You can use an And Not or OR Not instruction to check the signal state of a normally closed relay contact.
If a normally closed contact is closed ( I 0.0 = 0 ) the check result is ‘1’ , if it is open the result is ‘0’
Format of ON and AN Instructions: ON or AN (op-code) I (operand identifier) 0.0 ( address )
The below figure shows an example with all three representation (i.e. LAD / FBD / STL) that uses an OR
Not & And Not instructions to program one normally closed contact.

Ladder Program FBD Program STL Program Relay Logic cct.

I 0.1
I 0.0 1
Q 4.0
I 0.0 Q 4.0 ON I 0.0
= = Q 4.0 Q 4.0

OR OR

AN I 0.0
I 0.0 & = Q 4.0
Q 4.0

The OR Not, And Not instructions can also be used directly to check the following status word bits by their
addresses:
Example : 1. ON OV, ON >0, ON <>0, ON OS, ON UO, ON BR, ON ==0 etc.
2. AN OV, AN >0, AN <>0 , AN OS, AN UO , AN BR , AN ==0 etc

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XOR & XOR NOT Functions:

Exclusive OR function links two binary states with one another and returns an ‘RLO’ of ‘1’, when the two
states are not same. And returns an ‘RLO’ of ‘0’ when two states are same. Exclusive OR Not function
returns exactly opposite ‘RLO’ as that of XOR.
Format of Exclusive OR and Exclusive OR NOT: X or XN (op-code) I (operand identifier) 0.0 ( address )
The below figure shows an example with all three representation (i.e. LAD / FBD / STL) that uses an X and
XN instructions to program one normally closed contact.

L a d d er P r o g ra m S T L P r o g ra m R e l a y L o g i c c ir c u i t .

I 0.0 Q 4.0 X I 0 .0
I 0.0
X I 0 .1
I 0 .1
= Q 4 .0
I 0 .1
O R O R

I 0.0 Q 4.0 X N I 0 .0
Q 4 .0
X N I 0 .1
I 0 .1
= Q 4 .0

The X and XN instructions can also be used directly to check the following status word bits by their
addresses.
Example: 1. X OV, X >0, X <>0 , X OS, X UO , X BR , X ==0 etc.
2. XN OV, XN >0, XN <>0 , XN OS, XN UO , XN BR , XN ==0 etc

Processing Of Nesting Expression:

You can use the AND (A), OR (O) and Exclusive Or (X) instructions and their negated forms AN, ON, XN
to perform Boolean logic operations on portions of logic string that enclosed in parentheses. If there is
some operation inside the parenthesis means the program will perform the operation inside the
parentheses before performing the logic operation indicated with parentheses.
Example: A(
O I 0.0
O I 0.1
) ……..
The nesting of expression with the help of parentheses is possible only in STL method of programming. In
other two methods you don’t require it, it is achieved by series and parallel connections of NO/NC contacts
in ladder and by using AND, OR operations in FBD. You can program a nesting expression in a nesting
expression. The nesting depth is seven; i.e. you may begin a nesting expression seven times without
terminating first one. Within a nesting expression, you can program any statements used in STL
programming method of representation.

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And before Or:

Example:

The O function performs a logical OR instruction on AND functions according to the rule: AND before OR.

Or Before And:
Example:

Assign:
Example:

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= ---( ) (Output Coil) works like a coil in a relay logic diagram. If there is power flow to the coil (RLO = 1),
the bit at location <address> is set to "1". If there is no power flow to the coil (RLO = 0), the bit at location
<address> is set to "0". An output coil can only be placed at the right end of a ladder rung. Multiple output
elements (max. 16) are possible (see example). A negated output can be created by using the ---|NOT|---
(invert power flow) element.

RS: Reset-Set Flip Flop:

RS (Reset-Set Flip-Flop) is reset if the signal state is "1" at the R input, and "0" at the S input. Otherwise, if
the signal state is "0" at the R input and "1" at the S input, the flip-flop is set. If the RLO is "1" at both
inputs, the order is of primary importance. The RS flip-flop executes first the reset instruction then the set
Instruction at the specified <address> so that this address remains set for the remainder of program
scanning. The S (Set) and R (Reset) instructions are executed only when the RLO is "1". RLO "0" has no
effect on these instructions and the address specified in the instruction remains unchanged.
Example:

If the signal state is "1" at input I0.0 and "0" at I0.1, memory bit M0.0 is reset and output Q4.0 is "0".
Otherwise, if the signal state at input I0.0 is "0" and at I0.1 is "1", memory bit M0.0 is set and output Q4.0 is
"1". If both signal states are "0", nothing is changed. If both signal states are "1", the set instruction
dominates because of the order; M0.0 is set and Q4.0 is "1".

SR: Set-Reset Flip Flop:

SR (Set-Reset Flip-Flop) is set if the signal state is "1" at the S input, and "0" at the R input. Otherwise, if
the signal state is "0" at the S input and "1" at the R input, the flip-flop is reset. If the RLO is "1" at both
inputs, the order is of primary importance. The SR flip-flop executes first the set instruction then the reset
instruction at the specified <address>, so that this address remains reset for the remainder of program
scanning. The S (Set) and R (Reset) instructions are executed only when the RLO is "1". RLO "0" has no
effect on these instructions and the address specified in the instruction remains unchanged.

If the signal state is "1" at input I0.0 and "0" at I0.1, memory bit M0.0 is set and output Q4.0 is "1".
Otherwise, if the signal state at input I0.0 is "0" and at I0.1 is "1", memory bit M0.0 is reset and output Q4.0
is "0". If both signal states are "0", nothing is changed. If both signal states are "1", the reset instruction
dominates because of the order; M0.0 is reset and Q4.0 is "0".
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Reset & Set Coil:

---( R ) Reset Coil:
---( R ) (Reset Coil) is executed only if the RLO of the preceding instructions is "1" (power flows to the coil).
If power flows to the coil (RLO is "1"), the specified <address> of the element is reset to "0". A RLO of "0"
(no power flow to the coil) has no effect and the state of the element’s specified address remains
unchanged. The <address> may also be a timer (T no.) whose timer value is reset to "0" or a counter (C
no.) whose counter value is reset to "0".
Example

---( S ) Set Coil:

---( S ) (Set Coil) is executed only if the RLO of the preceding instructions is "1" (power flows to the coil). If
the RLO is "1" the specified <address> of the element is set to "1".
An RLO = 0 has no effect and the current state of the element’s specified address remains unchanged.

The signal state of output Q4.0 is "1" if one of the following conditions exists: The signal state is "1" at
inputs I0.0 and I0.1 Or the signal state is "0" at input I0.2. If the RLO is "0", the signal state of output Q4.0
remains unchanged.

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FP: Edge Positive

FP <Bit> (Positive RLO edge) detects a rising edge when the RLO transitions from "0" to "1" and indicates
this by RLO = 1. During each program scan cycle, the Signal State of the RLO bit is compared with that
obtained in the previous cycle to see if there has been a state change. The previous RLO State must be
stored in the edge flag address (<Bit>) to make the comparison. If there is a difference between current
and previous RLO "0" state (detection of rising edge), the RLO bit will be "1" after this instruction.
Definition

Example: If the programmable logic controller detects a positive edge at contact I 1.0, it energizes the coil
at Q 4.0 for one OB1 scans cycle.

FN: Edge Negative:

FN <Bit> (Negative RLO edge) detects a falling edge when the RLO transitions from "1" to "0", and
indicates this by RLO = 1. During each program scan cycle, the Signal State of the RLO bit is compared
with that obtained in the previous cycle to see if there has been a state change. The previous RLO State
must be stored in the edge flag address (<Bit>) to make the comparison. If there is a difference between
current and previous RLO "1" state (detection of falling edge), the RLO bit will be "1" after this instruction.
Example: If the programmable logic controller detects a negative edge at contact I 1.0, it energizes the coil
at Q 4.0 for one OB1 scans cycle.

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Instructions with Status Bits:

Instruction Meaning Example
SET Set RLO to "1" SET //RLO-1
CLR Set RLO to "0" CLR //RLO-0
NOT Invert RLO NOT;
SAVE Save RLO in binary result
A BR Check binary result

| | | | | | (S A V E )

BR Q 4 .2 Q 5 .0
| | | | ( )

Change RLO: With STEP7 there are a number of instructions that affect the RLO. With SET you set the
result of logic operation to "1", with CLR to "0". Parallel to this, the status bit STA is also set to "1" or to
"0". Both instructions are executed independent of conditions. SET and CLR also reset the status bits OR
and /FC, that is, a new check string begins afterwards. The NOT negates the RLO.
BR Bit: The BR bit represents an internal bit memory, in which the RLO can be saved before an RLO
changing instruction. This is so that the RLO is then available for the resumption of the
interrupted bit string. If you write a function block or a function and want to call it in LAD, you have
to manage the BR bit. The BR bit corresponds to the enable output (ENO) for the LAD box.
Setting and Resetting BR: With SAVE you save the RLO in the binary result (register). SAVE transmits
the signal state from the RLO to the status bit BR. SAVE is executed independent of any conditions and
does not affect any further status bits.

RLO Concept:

Example 1 Example 2 Example 3

Result of Check

Result of Check

Result of Check
Result of Logic

Result of Logic

Result of Logic
Signal State

Signal State

Signal State
First Check

First Check

First Check
Operation

Operation

Operation

:
:
= M 3.4

A I 1.0 0 0 0 1 1 1 1 1 1 1 1 1

AN I 1.1 0 1 0 1 1 0 0 1 0 1 1 1

A M 4.0 0 0 0 1 1 1 0 1 1 1 1 1

= Q 8.0 0 0 0 0 1 0

= Q 8.1 0 0 0 0 1 0

A I 2.0 0 0 0 1 1 1 1 1 0 0 0 1

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Signal State: A logic operation is made up of a series of instructions to check the states of signals (inputs
(I), outputs (Q), bit memories (M), timers (T), counters (C) or data bits (D) ) and instructions to set Q,M,T,C
or D.
Result of Check: When the program is executed, the result of check is obtained. If the check condition is
fulfilled, the result of check is “1”. If it is not fulfilled, the result of check is “0”.
First Check: The result of the first check is stored as the result of logic operation (RLO).
Result of Logic: When the next check instructions are executed, the result of logic operation is gated with
the result of check and a new RLO is obtained. When the last check instruction in a logic operation has
been executed, the RLO remains the same. A number of instructions using the same RLO can follow.

Normally Open and Normally Closed Contacts (sensor):

Process Interpretation in PLC program

The The sensor Voltage Signal Check for Check for

sensor is ... present state signal state “1” signal state “0”
is a ... at at
input? input Symbol / Result of Symbol / Result of
Instruction check Instruction check

NO activated
contact 1 LAD: “Yes“ LAD: “No”
Yes
1 0
“NO contact” “NC contact”

not No
activated 0 “No” “Yes”
0 1
FBD: FBD:

NC activated & &

No 0 “No” “Yes”
contact
0 1

not STL: STL:

activated Yes 1 “Yes” “No”
A I x.y 1 AN I x.y 0

Process: The use of normally open or normally closed contacts for the sensors in a controlled process
depends on the safety regulations for the process.Normally closed contacts are always used for limit
switches and safety switches, so that dangerous conditions do not arise if a wire break occurs in the
sensor circuit. Normally closed contacts are also used for switching off machinery for the same reason.
Symbols: In LAD, a symbol with the name "NO contact" is used for checking for signal state "1" and a
symbol with the name "NC contact" to check for signal state "0". It makes no difference whether the
process signal “1” is supplied by an activated NO contact or a non-activated NC contact.
Example: The result of check for the "NO contact" symbol is "1" if an NC contact in the machine is not
activated.

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Task : In all three examples the light should be on when S1 is activated and S2 is not activated!

Hardware

S1 S2 S1 S2 S1 S2

II1.0
1.0 II1.1
1.1 II1.0
1.0 II1.1
1.1. II1.0
1.0 II1.1
1.1
Programmable controller Programmable controller Programmable controller
Q 4.0 Q 4.0 Q 4.0

Light Light Light

Software
I 1.0 I 1.1 Q 4.0 I 1.0 I 1.1 Q 4.0 I 1.0 I 1.1 Q 4.0
LAD

I 1.0 & I 1.0 & I 1.0 &

FDB
I 1.1 Q 4.0 I 1.1 Q 4.0 I 1.1 Q 4.0

.A I 1.0 A I 1.0 .AN I 1.0

STL AN I 1.1 A. I 1.1 A I 1.1
= Q 4.0 = Q 4.0 = Q 4.0

Note ! The terms "NO contact" and "NC contact" have different meanings depending on whether they are
used in the process hardware context or as symbols in the software.

3.2 Data Types

Data types are used to specify the size and format of your program’s data elements. There are three
categories of data types.
Elementary Data Types
Complex Data Types
Parameter Types
For your program to work properly, each instruction must be assigned an address of the correct data
type. After data is processed, the output data have a certain data type that can vary from the data type
for the input data. If you want the output of one instruction to be the input for another, and the data
types are incompatible, you must insert a data type conversion function between them.
Data types must be also be assigned to variables in variable declaration tables and to
symbolic names in symbol tables in an S7 program so you can:
Program block calls with passed parameters
Create data blocks
Use symbolic addressing

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Elementary Data Type :

The data type having less than 32 bit size are called Elementary data type, They are possible with
constants as well as variables with different memory areas.

BOOL, BYTE, WORD, D WORD, CHAR: Variables of the data type BOOL consist of one bit, variables of
data types Byte, Word, DWord are sequences of 8, 16 & 32 bits respectively. The individual bits are not
evaluted in these data types. Special forms of these data types are the BCD numbers and the count value
used in conjunction with the count function & the data type CHAR, which represents a character in ASCII.

S5TIME: Variables of the data type S5TIME are required for specifying timer values in timer functions (S5
Timer functions). You specify the time in hours, minutes, seconds or milliseconds. You can enter the timer
values with an underline (1h_4m) or without an underline (1h4m). Functions FC 33 and FC40 from the
library convert S5TIME to TIME format and TIME to S5TIME format.

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Data Type INT (16-Bit Integers): An integer has a sign that indicates whether it is a positive or negative
integer. The space that an integer (16 bits) occupies in the memory is one word. The following table shows
the range of an integer (16 bits).
Format: Integer (16 bits ), Range: -32768 to 32768
The following figure shows the integer +44 as a binary number:

15 12 11 8 7 4 3 0
0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0

Sign Decimal Values : 32 + 8+ 4 = 44

Data Type DINT (32-Bit Integers): A double integer has a sign that indicates whether it is a positive or
negative integer. The space that a double integer occupies in the memory is two words. The following
table shows the range of a double integer.
Format: Integer (32 bits), Range: –2 147 483 648 to +2 147 483 647
The following figure shows the integer –500 000 as a binary number. In the binary system, the negative
form of an integer is represented as the twos complement of the positive integer. You obtain the twos
complement of an integer by reversing the signal states of all bits and then adding +1 to the result.

31 24 23 16 15 8 7 0
11111111 11111000 01011110 11100000

Sign
Decim al Value

Data Type REAL (Floating-Point Numbers): This type of number representation has the advantage of
being able to represent both very large and very small values within a limited space. With the limited
number of bits for the mantissa and exponent, a wide range of numbers can be covered. The
disadvantage is in the limited accuracy of calculations. For example, when forming the sum of two
numbers, the exponents must be matched by shifting the mantissa (hence floating decimal point) since
only numbers with the same exponent can be added. Floating-point numbers in STEP 7 conform to the
basic format, single width, described in the ANSI/IEEE standard 754–1985, IEEE Standard for Binary
Floating-Point Arithmetic.They consist of the following components:
The sign S
The exponent e = E + bias, increased by a constant (bias = +127)
The fractional part of the mantissa m. The whole number part of the mantissa is not stored with the
rest, because it is always equal to 1 within the valid number range.

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The three components together occupy one double word (32 bits):

Representation format of a REAL number (IEEE FP 32 bit binary format):

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2-1 2-23
S Exponent: e = 8 Bit
Mantissa: f (23 Bits)

Using the three components S, e, and f, the value of a number represented in this form is defined by the
formula:

Representation of a normalized REAL number:

S x (1.f) x 2 (e-127) S = Sign bit, (0 corresponds to +, 1 corresponds to -)
f = 23 bit Mantissa with MSB = 2 -1 and LSB =2 -23
e = binary integer exponent (0 < e < 255)

Examples :

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Data Type Time, Date and Time_Of_Day:

Size Format Range and Number Notation Example

Type and
in Options (lowest to highest value)
Description
Bits

TIME (IEC 32 IEC time in T#24D_20H_31M_23S_648MS L T#0D_1H_1M_0S_0MS

time) steps of 1 ms, to L
integer signed T#24D_20H_31M_23S_647MS TIME#0D_1H_1M_0S_0MS

DATE (IEC 16 IEC date in D#1990-1-1 to L D#1996-3-15

date) steps of 1 day D#2168-12-31 L DATE#1996-3-15
TIME_OF_DAY 32 Time in steps of TOD#0:0:0.0 to L TOD#1:10:3.3
(Time) 1 ms TOD#23:59:59.999 L TIME_OF_DAY#1:10:3.3

3.3 Load and Transfer Operation

The Load (L) and Transfer (T) instructions enable you to program an interchange of information between
input or output modules and memory areas, or between memory areas. The CPU executes these
instructions in each scan cycle as unconditional instructions; that is, they are not affected by the result of
logic operation of a statement.

Load Operations :
Accumulator 1

Load Function

PII PIQ Data from DB. Peripheral Inputs

Bit Memory Status Word DB length & No.

Timers Address Constants &

& Counters Registers Pointers

L Stack

Load operation brings the contents of different memory areas (as shown in the above figure) into the
accumulator 1.

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Transfer Operations :
Accumulator 1

Transfer Function

PII PIQ Data Locations Peripheral

in Data Block. Outputs
Bit Memory Status Word

L Stack Address
Registers

Transfer operation transfers the contents of accumulator 1 to the different memory areas (as shown in the
above figure).

Accessing of PII Memory Area using Load Operation:

PII
7 6 5 4 3 2 1 0
Reading Bit by Bit into the “RLO” ( A I 0.2 ) I
Byte 0
0
0
Higher – Order Word Lower – Order Word L IB 10 Byte10
Word
00 00 Word
00 10
Higher Byte Lower Byte Higher Byte 0
Lower Byte
0 0 0 Byte16
L IW 16
Byte Byte Byte Byte Byte17
00 00 16 6
7
0 0
L ID 20 Byte20
20 Byte21
0Byte22
1Byte23
2
31 16 15 0 3
1 6 5
Format Of Load Operation: L <address>
Address can be PII, PIQ, Periphery Input, DB Area, Bit Memory Area, Constants, Timers, Counters With
data type as Byte, Word or Double Word. Example: L IW 4, L MW 12, L DB1.DBW0 etc.

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Transferring PIQ Memory Area using Transfer Operation:

PIQ
7 6 5 4 3 2 1 0
Assignment of the “RLO” ( = Q 0.2 )
Byte 0
0
0
Higher – Order Word Lower – Order Word T QB10 Byte10
Word
00 00 Word00
Higher Byte Lower Byte Higher Byte 0
Lower Byte
0 0 0 Byte16
T QW16
Byte Byte Byte Byte Byte17
00 00 6
7
0 0
T QD20 Byte20
Byte21
0Byte22
1Byte23
2
31 16 15 0 3
1 6 5
Format Of Transfer Operation: T <address>
Address can be PII, PIQ, Periphery Output, DB Area, and Bit Memory Area with data type as Byte, Word
or Double Word. Example: T QW 4, T MW 12, T DB1.DBW0 etc.

Load and Transfer Operation :

DI PII PIQ DQ
L IW 0 T QW 0
I 0.0 Q 0.0
I 0.1 Q 0.1
I 0.2 Q 0.2
I 0.3 Q 0.3
I 0.4 Q 0.4
I 0.5
Accumulator 1 Q 0.5
I 0.6 Q 0.6
I 0.7 Q 0.7
Previous
I 1.0
Contents Of Q 1.0
I 1.1
Accumulator 1 Q 1.1
I 1.2 Q 1.2
I 1.3 Q 1.3
I 1.4
Accumulator 2 Q 1.4
I 1.5 Q 1.5
I 1.6 Q 1.6
I 1.7 Q 1.7
LOST

Load operation brings the memory area into the accumulator 1, previous contents of accumulator 1 gets
transferred to the accumulator 2. And the accumulator 2 gets lost.

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Points to Note:
The Load & Transfer functions are not dependent on “RLO” or the status bits
When a byte is loaded, its contents are written right-justified into Accumulator 1.
The remaining bytes in Accumulators are padded with “0”.
The multiple load and transfer operations are possible.
Examples on Load instuctions:
STL Explanation
L DBB12 Load data byte DBB12 into ACCU 1-L-L.
L DIW15 Load instance data word DIW15 into ACCU 1-L.
L LD252 Load local data double word LD252 ACCU 1.
L P# I 8.7 Load the pointer into ACCU 1.
L “OTTO” Load the parameter "OTTO" into ACCU 1.
L P# ANNA Load the pointer to the specified parameter in ACCU 1.
(This instruction loads the relative address offset of the specified parameter. To calculate the absolute
offset in the instance data block in multiple instance FBs, the contents of the AR2 register must be added
to this value)

Examples on Transfer instructions:

STL Explanation
T QB10 Transfers contents of ACCU 1-L-L to output byte QB10.
T MW14 Transfers contents of ACCU 1-L to memory word MW14.
T DBD2 Transfers contents of ACCU 1 to data double word DBD2.

Some more Load and Transfer instructions are as follows:

L STW Load Status Word into ACCU 1
LAR1 AR2 Load Address Register 1 from Address Register 2
LAR1 <D> Load Address Register 1 with Double Integer (32-Bit Pointer)
LAR1 Load Address Register 1 from ACCU 1
LAR2 <D> Load Address Register 2 with Double Integer (32-Bit Pointer)
LAR2 Load Address Register 2 from ACCU 1

T STW Transfer ACCU 1 into Status Word

TAR1 AR2 Transfer Address Register 1 to Address Register 2
TAR1 <D> Transfer Address Register 1 to Destination (32-Bit Pointer)
TAR2 <D> Transfer Address Register 2 to Destination (32-Bit Pointer)
TAR1 Transfer Address Register 1 to ACCU 1
TAR2 Transfer Address Register 2 to ACCU 1
CAR Exchange Address Register 1 with Address Register 2

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3.4 Comparision Instructions

ACCU1 and ACCU2 are compared according to the type of comparison you choose:
== ACCU1 is equal to ACCU2
<> ACCU1 is not equal to ACCU2
> ACCU1 is greater than ACCU2
< ACCU1 is less than ACCU2
>= ACCU1 is greater than or equal to ACCU2
<= ACCU1 is less than or equal to ACCU2
You can use comparison instructions to compare the following pairs of numerical values:
I Compare integers (on the basis of 16 bit fixed-point number)
D Compare Double integers (on the basis of 32 bit fixed-point number)
R Compare floating-point numbers (on 32 bit real number basis = IEEE floating-point numbers).
NOTE: If the comparison is true, the RLO of the function is "1"otherwise it remains “0”. The status word
bits CC 1 and CC 0 indicate the relations ‘’less’’, ‘’equal’’, or ‘’greater’’.

Compare Integer (16-Bit):

The Compare Integer (16-bit) instructions compare the contents of ACCU 2-L with the contents of
ACCU 1-L The contents of ACCU 2-L and ACCU 1-L are interpreted as 16-bit integer numbers. The
result of the comparison is indicated by the RLO and the setting of the relevant status word bits. RLO =
1 indicates that the result of the comparison is true; RLO = 0 indicates that the result of the comparison
is false. The status word bits CC 1 and CC 0 indicate the relations ‘’less,’’ ‘’equal,’’ or ‘’greater.’’
The values at inputs IN1 and IN2 are compared for conformity with the specified condition:
== I IN1 is equal to IN2
<> I IN1 is not equal to IN2
>I IN1 is greater than IN2
<I IN1 is less than IN2
>= I IN1 is greater than or equal to IN2
<= I IN1 is less than or equal to IN2.
Example (STL )
L MW10 //Load contents of MW10 (16-bit integer).
L IW24 //Load contents of IW24 (16-bit integer).
>I //Compare if ACCU 2-L(MW10)is greater(>)than ACCU1- L (IW24).
= M 2.0 //RLO = 1 if MW10 > IW24.

Compare Double Integer (32-Bit):

The Compare Double Integer (32-bit) instructions compare the contents of ACCU 2 with the contents of
ACCU 1 .The contents of ACCU 2 and ACCU 1 are interpreted as 32-bit integer numbers. The result of
the comparison is indicated by the RLO and the setting of the relevant status word bits. RLO = 1

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indicates that the result of the comparison is true; RLO = 0 indicates that the result of the comparison is
false. The status word bits CC 1 and CC 0 indicate the relations ‘’less,’’ ‘’equal,’’or ‘’greater.”
The values at inputs IN1 and IN2 are compared for conformity with the specified condition:
== D IN1 is equal to IN2
<> D IN1 is not equal to IN2
>D IN1 is greater than IN2
<D IN1 is less than IN2
>= D IN1 is greater than or equal to IN2
<= D IN1 is less than or equal to IN2.
Example (STL)
L MD10 //Load contents of MD10 (double integer, 32 bits).
L ID24 //Load contents of ID24 (double integer, 32 bits).
>D //Compare if ACCU 2 (MD10) is greater (>) than ACCU 1 (ID24).
= M 2.0 //RLO = 1 if MD10 > ID24

Compare Floating-Point Number (32-Bit):

The Compare Floating Point Number (32-bit, IEEE-FP) instructions compare the contents of ACCU 2
with the contents of ACCU 1. The contents of ACCU 1 and ACCU 2 are interpreted as floating-point
numbers (32-bit, IEEE-FP). The result of the comparison is indicated by the RLO and the setting of the
relevant status word bits. RLO = 1 indicates that the result of the comparison is true; RLO = 0 indicates
that the result of the comparison is false. The status word bits CC 1 and CC 0 indicate the relations
‘’less,” ‘’equal,” or ‘’greater.”
The values at inputs IN1 and IN2 are compared for conformity with the specified condition:
== R IN1 is equal to IN2
<> R IN1 is not equal to IN2
>R IN1 is greater than IN2
<R IN1 is less than IN2
>= R IN1 is greater than or equal to IN2
<= R IN1 is less than or equal to IN2
Example(STL)
L MD10 //Load contents of MD10 (floating-point number).
L 1.359E+02 //Load the constant 1.359E+02.
>R //Compare if ACCU 2(MD10)is greater(>)than ACCU1(1.359- E+02).
= M 2.0 //RLO = 1 if MD10 > 1.359E+02

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Comparision Operation:
LAD FBD STL

M0.0 CMP ==I Q 9.7 CMP ==I A M0.0

A(
L I W0
I W0 IN1
L I W2
I W0 IN1
==I
I W2 IN2 I W2 IN2 )
&
Q9.7
= Q9.7
=
M0.0

3.5 Integer Math Instructions

The math operations combine contents of ACCU1 and 2. The result is stored in ACCU1. The contents of
ACCU2 remain unchanged. In the case of CPUs with four accumulators, the contents of ACCU3 is copied
into ACCU2 and the contents of ACCU4 into ACCU3.The old contents of ACCU4 remains unchanged.
Using integer math, you can carry out the following operations with two integer numbers (16 and 32 bits):
ADD_I Add Integer ( +I )
SUB_I Subtract Integer ( -I )
MUL_I Multiply Integer ( * I )
DIV_I Divide Integer ( /I )
ADD_DI Add Double Integer ( +D )
SUB_DI Subtract Double Integer ( -D )
MUL_DI Multiply Double Integer ( *D )
DIV_DI Divide Double Integer ( /D )
Add Integer Constant (16, 32 Bit) (+ )
MOD_DI Return Fraction Double Integer ( MOD )
The integer math instructions influence the following bits in the Status word: CC1 and CC0, OV and OS.
The following tables show the Signal State of the bits in the status word for the results of instructions with
Integers (16 and 32 bits):
Valid Range for the Result CC 1 CC 0 OV OS
0 (zero) 0 0 0 *
16 bits: -32 768 <= result < 0 (negative number) &
32 bits: -2 147 483 648 <=result < 0 (negative number) 0 1 0 *
16 bits: 32 767 >= result > 0 (positive number) &
32 bits: 2 147 483 647 >= result > 0 (positive number) 1 0 0 *
(The OS bit is not affected by the result of the instruction.)

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Meaning of different inputs and outputs in Ladder logic representation:

EN ENO
IN1
IN2 O UT

EN The instruction is executed if RLO is =1 at Enable input EN.

ENO If the result is outside the permissible range for the data type concerned, overflow bits
OV=“Overflow” and OS=“Stored Overflow” are set and Enable output ENO=0.
This Prevents subsequent operations dependent on ENO from being executed.
IN1,IN2 The value at IN1 is read in as the first address and the value at IN2 as the second.
OUT The result of the mathematical operation is stored at the address at output.

Addition: (+I and +D):

+I (add 16-bit integer numbers): adds the contents of ACCU 1-L to the contents of ACCU 2-L and stores
the result in ACCU 1-L. The contents of ACCU 1-L and ACCU 2-L are interpreted as 16-bit integer
numbers. The instruction is executed without regard to, and without affecting, the RLO.
+D (add 32-bit integer numbers): adds the contents of ACCU 1 to the contents of ACCU 2 and stores the
result in ACCU 1. The contents of ACCU 1 and ACCU 2 are interpreted as 32-bit integer numbers. The
instruction is executed without regard to, and without affecting, the RLO.
Example 1:
L IW10 //Load the value of IW10 into ACCU1-L.
L MW14 //Load contents of ACCU1-L into ACCU2-L. Load value of MW14 into ACCU1-L.
+I //Add ACCU2-L and ACCU1-L; store the result in ACCU1-L.
T DB1.DBW20 //The contents of ACCU 1 (result) are transferred to DBW20 of DB1.
Example 2:
L ID10 // Load the value of ID10 into ACCU 1.
L MD14 //Load the contents of ACCU 1 to ACCU 2. Load the value of MD14 into ACCU 1.
+D // Add ACCU 2 and ACCU 1; store the result in ACCU 1.
T DB1.DBD25 //The contents of ACCU 1 (result) are transferred to DBD25 of DB1.

Subtraction: (- D and – I):

-I (subtract 16-bit integer numbers) subtracts the contents of ACCU 1-L from the contents of ACCU 2-L
and stores the result in ACCU 1-L. The contents of ACCU 1-L and ACCU 2-L are interpreted as 16-bit
integer numbers. The instruction is executed without regard to, and without affecting the RLO.
-D (subtract 32-bit integer numbers) subtracts the contents of ACCU 1 from the contents of ACCU 2 and
stores the result in ACCU 1. The contents of ACCU 1 and ACCU 2 are interpreted as 32-bit integer
numbers. The instruction is executed without regard to, and without affecting, the RLO. The status word
bits CC 1, CC 0, OS, and OV are set as a function of the result of the instruction.
Example 1:
L IW10 // Load the value of IW10 into ACCU 1-L.
L MW14 // Load contents of ACCU1-L into ACCU2-L & Load value of MW14 into ACCU1-L.

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-I //Subtract ACCU 1-L from ACCU 2-L; store the result in ACCU 1-L.
T DB1.DBW25 //The contents of ACCU 1-L(result) are transferred to DBW25 of DB1.
Example 2:
L ID10 //Load the value of ID10 into ACCU 1.
L MD14 // Load the contents of ACCU1 into ACCU2. Load the value of MD14 into ACCU1.
-D // Subtract ACCU 1 from ACCU 2; store the result in ACCU 1.
T DB1.DBD25 //The contents of ACCU 1 (result) are transferred to DBD25 of DB1.

Multiply: (*I and *D):

*I (multiply 16-bit integers) multiplies the contents of ACCU2-L by the contents of ACCU1-L.The contents
of ACCU1-L and ACCU2-L are interpreted as 16-bit integer numbers. The result is stored in accumulator 1
as a 32-bit integer number. If the status word bits are OV1=1 and OS=1, the result is outside the range of
a 16-bit integer number. The instruction is executed without regard to, and without affecting, the RLO.
*D (multiply 32-bit integer numbers) multiplies the contents of ACCU2 by the contents of ACCU1. The
contents of ACCU1 and ACCU2 are interpreted as 32-bit integer numbers. The result is stored in ACCU1
as a 32-bit integer number. If the status word bits are OV1=1 and OS=1, the result is outside the range of
a 32-bit integer number. The instruction is executed without regard to, and without affecting, the RLO.
Example 1:
L IW10 //Load the value of IW10 into ACCU 1-L.
L MW14 //Load contents of ACCU1-L into ACCU2-L & contents of MW14 into ACCU1-L.
*I //Multiply ACCU 2-L and ACCU 1-L, store result in ACCU 1.
T DB1.DBD25 //The contents of ACCU 1 (result) are transferred to DBW25 in DB1.
Example 2:
L ID10 //Load the value of ID10 into ACCU 1.
L MD14 // Load contents of ACCU 1 into ACCU 2. Load contents of MD14 into ACCU 1.
*D //Multiply ACCU 2 and ACCU 1; store the result in ACCU 1.
T DB1.DBD25 //The contents of ACCU 1 (result) are transferred to DBD25 in DB1.

Divide : ( /I and /D ):
/I (divide 16-bit integer numbers) divide the contents of ACCU2-L by the contents of ACCU1-L. The
contents of ACCU1-L and ACCU2-L are interpreted as 16-bit integer numbers. The result is stored in
ACCU1 and consists of two 16-bit integer numbers, the quotient & the remainder. The quotient is stored in
ACCU1-L & the remainder in ACCU1-H. The instruction is executed without regard to, and without
affecting, the RLO.
/D (divide 32-bit integer numbers) divides the contents of ACCU2 by the contents of ACCU1. The contents
of ACCU1 and ACCU2 are interpreted as 32-bit integer numbers. The result of the instruction is stored in
ACCU1. The result gives only the quotient and not the remainder. (The instruction MOD can be used to
get the remainder). The instruction is executed without regard to, and without affecting, the RLO.
Example 1:
L IW10 // Load the value of IW10 into ACCU 1-L.
L MW14 // Load contents of ACCU1-L into ACCU2-L & value of MW14 into ACCU 1-L.

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/I //Divide ACCU 2-L by ACCU 1-L; store the result in ACCU 1: ACCU 1-L: quotient,
ACCU 1-H: remainder
T MD20 // The contents of ACCU 1 (result) are transferred to MD20.
Example (13 divided by 4)
Contents of ACCU 2-L before instruction (IW10): "13"
Contents of ACCU 1-L before instruction (MW14): "4"
Instruction /I (ACCU 2-L / ACCU 1-L): "13/4"
Contents of ACCU 1-L after instruction (quotient): "3"
Contents of ACCU 1-H after instruction (remainder): "1"

Example 2:
L ID10 // Load the value of ID10 into ACCU 1.
L MD14 //Load the contents of ACCU 1 into ACCU 2. Load the value of MD14 into ACCU
1.
/D //Divide ACCU 2 by ACCU 1; store the result (quotient) in ACCU 1.
T MD20 //The contents of ACCU 1 (result) are transferred to MD20.
Example (13 divided by 4)
Contents of ACCU 2 before instruction (ID10): "13"
Contents of ACCU 1 before instruction (MD14): "4"
Instruction /D (ACCU 2 / ACCU 1): "13/4"
Contents of ACCU 1 after instruction (quotient): "3"

Add Integer Constant (16, 32-Bit):

+ <integer constant>: adds the integer constant to the contents of ACCU1 and stores the result in
ACCU1. The instruction is executed without regard to, and without affecting, the status word bits.The
contents of accumulator 2 remain unchanged for CPUs with two ACCUs.
+ <16-bit integer constant>: Adds a 16-bit integer constant (in the range of -32768 to +32767) to the
contents of ACCU 1-L and stores the result in ACCU 1-L. The contents of accumulator 2 remain
unchanged for CPUs with two ACCUs.
+ <32-bit integer constant>: Adds a 32-bit integer constant (in the range of -2,147,483,648 to
2,147,483,647) to the contents of ACCU 1 and stores the result in ACCU 1. The contents of accumulator 2
remain unchanged for CPUs with two ACCUs.
Example 1:
L IW12
L IW14
+ 100 //Add ACCU 1-L and 100; store the result in ACCU 1-L.
>I //If ACCU 2 > ACCU 1, or IW12 > (IW14 + 100)
JC NEXT //then conditional jump to jump label NEXT.
Example 2:
L MD20
L MD24
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+D //Add ACCU 1and ACCU 2; store the result in ACCU 1.

+ L#-200 //Add ACCU 1 and -200; store the result in ACCU 1.
T MD28

Division Remainder Double Integer (MOD):

MOD (remainder of the division of 32-bit integer numbers) divides the contents of ACCU 2 by the contents
of ACCU 1. The contents of ACCU 1 and ACCU 2 are interpreted as 32-bit integer numbers. The result of
the instruction is stored in accumulator 1. The result gives only the division remainder, and not the
quotient. (The instruction /D can be used to get the quotient.)
The instruction is executed without regard to, and without affecting, the RLO.
Example 1:
L ID10 //Load the value of ID10 into ACCU 1.
L MD14 //Load the contents of ACCU1 into ACCU2. Load the value of MD14 into ACCU1
MOD //Divide ACCU 2 by ACCU 1, store the result (remainder) in ACCU 1.
T MD20 // The contents of ACCU 1 (result) are transferred to MD20.
Example (13 divided by 4 )
Contents of ACCU 2 before instruction (ID10): "13"
Contents of ACCU 1 before instruction (MD14): "4"
Instruction MOD (ACCU 2 / ACCU 1): "13/4"
Contents of ACCU 1 after instruction (remainder): "1"

3.6 Floating-Point Math Instructions

The math instructions combine the contents of accumulators 1 and 2. The result is stored in accumulator
1. The old contents of accumulator 1 are shifted to accumulator 2. The contents of accumulator 2 remain
unchanged. The IEEE 32-bit floating-point numbers belong to the data type called REAL. You can use the
floating-point math instructions to perform the following math instructions using two 32-bit IEEE floating-
point numbers:
+R Add ACCU 1 and ACCU
-R Subtract ACCU 1 from ACCU 2
*R Multiply ACCU 1 and ACCU 2
/R Divide ACCU 2 by ACCU 1

Using floating-point math, you can carry out the following operations with one 32- bit IEEE floating-point
number:
ABS Absolute Value
SQR Generate the Square
SQRT Generate the Square Root
EXP Generate the Exponential Value
LN Generate the Natural Logarithm
SIN Generate the Sine of Angles

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COS Generate the Cosine of Angles

TAN Generate the Tangent of Angles
ASIN Generate the Arc Sine
ACOS Generate the Arc Cosine
ATAN Generate the Arc Tangent
Floating–point instructions affect the following bits in the status word: CC 1 and CC 0, OV and OS.The
following tables show the Signal State of the bits in the status word for the results of instructions with
floating-point numbers (32 bits):
Valid Area for a Result CC 1 CC 0 OV OS
+0, -0 (zero) 0 0 0 *
-3.402823E+38 < result < -1.175494E-38 (negative number) 0 1 0 *
+1.175494E-38 < result < 3.402824E+38 (positive number) 1 0 0 *

Addition: (+R):
+R (add 32-bit IEEE floating-point numbers) adds the contents of accumulator 1 to the contents of
accumulator 2 and stores the result in accumulator 1. The contents of accumulator 1 and accumulator 2
are interpreted as 32-bit IEEE floating-point numbers. The instruction is executed without regard to, and
without affecting, the RLO. The contents of accumulator 2 remain unchanged for CPUs with two ACCUs.
Example 1:
OPN DB10
L ID10 //Load the value of ID10 into ACCU 1.
L MD14 //Load the value of ACCU 1 into ACCU 2. Load the value of MD14 into ACCU 1.
+R //Add ACCU 2 and ACCU 1; store the result in ACCU 1.
T DBD25 //The content of ACCU 1 (result) is transferred to DBD25 in DB10.

Subtraction: (-R):
-R (subtract 32-bit IEEE floating-point numbers) subtracts the contents of accumulator 1 from the contents
of accumulator 2 and stores the result in accumulator 1. The contents of accumulator 1 and accumulator 2
are interpreted as 32-bit IEEE floating-point numbers. The result is stored in accumulator 1. The instruction
is executed without regard to, and without affecting, the RLO.
Example 1:
OPN DB10
L ID10 // Load the value of ID10 into ACCU 1.
L MD14 //Load the value of ACCU 1 into ACCU 2. Load the value of MD14 into ACCU 1.
-R //Subtract ACCU 1 from ACCU 2; store the result in ACCU 1.
T DBD25 //The content of ACCU 1 (result) is transferred to DBD25 in DB10.

Multiply: (*R):
*R (multiply 32-bit IEEE floating-point numbers) multiplies the contents of accumulator 2 by the contents of
accumulator 1. The contents of accumulator 1and accumulator 2 are interpreted as 32-bit IEEE floating-

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point numbers. The result is stored in accumulator 1 as a 32-bit IEEE floating-point number. The
instruction is executed without regard to, and without affecting, the RLO.
Example 1:
OPN DB10
L ID10 //Load the value of ID10 into ACCU 1.
L MD14 //Load the value of ACCU 1 into ACCU 2. Load the value of MD14 into ACCU 1.
*R //Multiply ACCU 2 and ACCU 1; store the result in ACCU 1.
T DBD25 //The content of ACCU 1 (result) is transferred to DBD25 in DB10.

Divide: ( /R ):
/R (divide 32-bit IEEE floating-point numbers) divides the contents of accumulator 2 by the contents of
accumulator 1. The contents of accumulator 1 and accumulator 2 are interpreted as 32-bit IEEE floating-
point numbers. The instruction is executed without regard to, and without affecting, the RLO.
Example 1:
OPN DB10
L ID10 // Load the value of ID10 into ACCU 1.
L MD14 // Load the contents of ACCU 1 into ACCU2. Load the value of MD14 into ACCU1.
/R //Divide ACCU 2 by ACCU 1; store the result in ACCU 1.
T DBD20 // The content of ACCU 1 (result) is transferred to DBD20 in DB10.

Absolute Value of a Floating-Point Number:

ABS (absolute value of a 32-bit IEEE FP) produces the absolute value of a floating-point number (32-bit
IEEE floating-point number) in ACCU 1. The result is stored in accumulator 1. The instruction is executed
without regard to, and without affecting, the status bits.
Example 1:
L ID8 //Load value into ACCU 1 (example: ID8 = -1.5E+02).
ABS // Form the absolute value; store the result in ACCU 1.
T MD10 //Transfer result to MD10 (example: result = 1.5E+02).

Square of a Floating-Point Number:

SQR (generate the square of an IEEE-FP 32-bit floating-point number) calculates the square of a floating-
point number (32-bit, IEEE-FP) in ACCU 1. The result is stored in accumulator 1. The instruction
influences the CC 1, CC 0, OV, and OS status word bits.
Example 1:
OPN DB17 //Open data block DB17.
L DBD0 //The value from DBD0 is loaded into ACCU1.
(This value must be in the floating-point format.)
SQR //Calculate the square of the floating-point number (32-bit, IEEE-FP) in ACCU 1.
Store the result in ACCU 1.
AN OV //Scan the OV bit in the status word for "0."
JC OK // If no error occurred during the SQR instruction, jump to the OK

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jump label.
... (The reaction to an error that occurred happens here.)
OK: T DBD4 // Transfer the result from ACCU 1 to data double word DBD4.

Square Root of a Floating-Point Number:

SQRT (generate the square root of a 32-bit, IEEE-FP floating-point number) calculates the square root of a
floating-point number (32-bit, IEEE-FP) in ACCU 1. The result is stored in accumulator 1. The input value
must be greater than or equal to zero. The result is then positive. Only exception the square root of -0 is -
0. The instruction influences the CC 1, CC 0, OV, and OS status word bits.
Example 1:
L MD10 //The value from memory double word MD10 is loaded into ACCU 1.
(This value must be in the floating-point format.)
SQRT //Calculate the square root of the floating-point number (32-bit, IEEE-FP) in
ACCU1. Store the result in ACCU 1.
AN OV //Scan the OV bit in the status word for "0."
JC OK // If no error occurred during the SQRT instruction, jump to the OK
jump label.
... (The reaction to an error that occurred happens here.)
OK: T MD20 // Transfer the result from ACCU 1 to memory double word MD20.

Exponential Value of a Floating-Point Number:

EXP (generate the exponential value of a floating-point number, 32-bit, IEEE-FP) calculates the
exponential value (exponential value for base e) of a floating-point number (32-bit, IEEE-FP) in ACCU 1.
The result is stored in accumulator 1. The instruction influences the CC 1, CC 0, OV, and OS status word
bits.
Example 1:
L MD10 // The value from memory double word MD10 is loaded into ACCU 1.
//(This value must be in the floating-point format.)
EXP //Calculate the exponential value of the floating-point number (32- bit,
IEEE-FP) in ACCU 1 at base e. Store the result in ACCU 1.
AN OV // Scan the OV bit in the status word for "0."
JC OK //If no error occurred during the EXP instruction, jump to the OK jump label.
... (The reaction to an error that occurred happens here.)
OK: T MD20 //Transfer the result from ACCU 1 to memory double word MD20.

Natural Logarithm of a Floating-Point Number:

LN (generate the natural logarithm of an IEEE-FP 32-bit floating-point number) calculates the natural
logarithm (logarithm to base e) of a floating-point number (32-bit, IEEE-FP) in ACCU 1. The result is stored
in accumulator 1. The input value must be greater than zero. The instruction influences the CC 1, CC 0,
UO,and OV status word bits.

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Example 1:
L MD10 // The value from memory double word MD10 is loaded into ACCU 1.
(This value must be in the floating-point format.)
LN //Calculate the natural logarithm of the floating-point number(32-bit, IEEE-FP) in
ACCU 1. Store the result in ACCU 1.
AN OV //Scan the OV bit in the status word for "0."
JC OK // If no error occurred during the instruction, jump to the OK jump label.
... //(The reaction to an error that occurred happens here.)
OK: T MD20 //Transfer the result from ACCU 1 to memory double word MD20.

Trigonometric Functions and Their Inverse Functions:

Trigonometric functions:
SIN Sine
COS Cosine
TAN Tangent
Arc functions:
ASIN Arc sine
ACOS Arc cosine
ATAN Arc tangent
Trigonometric Functions:
The trigonometric functions expect an angle in radian measure as a REAL number in ACCU1.For the
angle input (00 ... 3600), you must, if necessary, perform a conversion to degree measure (0 ... 2 pi, with
pi=3.141593). During function execution, for values smaller than 0 or larger than 2pi, A multiple of 2pi is
automatically added or subtracted until the value lies between 0 and 2pi (Automatic modulo-2pi
calculation).

Arc Functions
The arc functions are the inverse functions of the respective trigonometric functions. They expect a REAL
number in a specific value range in ACCU1 and return an angle in radian measure:
Function Permitted definition range Value range
ASIN -1 to +1 - pi/2 to + pi/2
ACOS -1 to +1 0 to pi
ATAN entire range - pi/2 to + pi/2
With an overrange of the permitted definition range, the arc functions return an invalid REAL
Number and set the status bits CC0, CC1, OV and OS to "1".

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3.7 Conversion Instructions:

The Conversion Instructions read the contents specified in the input parameter IN as and convert this
value or invert the sign bit. The output parameter OUT provides the result.

N um ber C o n v e rs io n
e n te re d in B C D 0 8 1 5 B C D -> In te g e r
U s e r p ro g ra m w ith
in te g e r m a th
o p e ra tio n s
N um ber C o n v e rs io n
d is p la y e d 0 2 4 8 B C D < -In te g e r
in B C D

Example: A user program is to perform mathematical functions using values entered with push wheel
buttons and display the result on a digital display. Mathematical functions cannot be performed in BCD
format, so the format must be changed.
Conversion Instructions:
The instruction set of the S7-300/400 supports a multitude of conversion facilities. The instructions all have
the same format:
EN, ENO: If RLO is =1 at Enable input EN, the conversion is performed. Enable output ENO always has
the same signal state as EN. If this is not the case, it is clearly indicated in the corresponding
instructions.
IN: When EN=1, the value at IN is read into the conversion instruction.
OUT: The result of the conversion is stored at the address at the OUT output.

The following conversion instructions are available:

BCD_I BCD to Integer ( BTI )
I_BCD Integer to BCD ( ITB )
BCD_DI BCD to Double Integer ( BTD )
I_DINT Integer to Double Integer ( ITD )
DI_BCD Double Integer to BCD ( DTB )
DI_REAL Double Integer to Floating-Point ( DTR )
INV_I Ones Complement Integer ( INVI )
INV_DI Ones Complement Double Integer ( INVD )
NEG_I Twos Complement Integer ( NEGI )
NEG_DI Twos Complement Double Integer ( NEGD )
NEG_R Negate Floating-Point Number ( NEGR )
ROUND Round to Double Integer ( RND )
TRUNC Truncate Double Integer Part ( TRUNC )
CEIL Ceiling ( RND+ )
FLOOR Floor ( RND - )
CAW Change Byte Sequence in ACCU 1-L (16-Bit)
CAD Change Byte Sequence in ACCU 1 (32-Bit)

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BCD to Integer (16-Bit) ( BTI ):

BTI (decimal to binary conversion of a 3-digit BCD number) interprets the contents of ACCU 1- L as a
three-digit binary coded decimal number (BCD) and converts it to a 16-bit integer. The result is stored in
the low word of accumulator 1. The high word of accumulator 1 and accumulator 2 remain unchanged.
BCD number in ACCU 1-L: The permissible value range for the BCD number is from "-999" to "+999". Bit
0 to bit 11 are interpreted as the value and bit 15 as the sign (0 = positive, 1= negative) of the BCD
number. Bit 12 to bit 14 are not used in the conversion. If a decimal (4 bits) of the BCD number is in the
invalid range of 10 to 15, a BCDF error occurs during attempted conversion. In general, the CPU will go
into STOP. However, you may design another error response by programming OB121 to handle this
synchronous programming error.
Example 1:
L MW10 // Load the BCD number into ACCU 1-L.
BTI //Convert from BCD to integer; store result in ACCU 1-L.
T MW20 //Transfer result (integer number) to MW20.

Integer (16-Bit) to BCD ( ITB ):

ITB (binary to decimal conversion of a 16-bit integer number) interprets the contents of ACCU 1- L as a
16-bit integer and converts it to a three-digit binary coded decimal number (BCD). The result is stored in
the low word of accumulator 1. Bit 0 to bit 11 contain the value of the BCD number. Bit 12 to bit 15 are set
to the state of the sign (0000 = positive, 1111= negative) of the BCD number. The high word of
accumulator 1 and accumulator 2 remain unchanged. The BCD number can be in the range of "-999" to
"+999." If the number is out of the permissible range, then the status bits OV and OS are set to 1. The
instruction is executed without regard to, and without affecting, the RLO.
Example 1:
L MW10 // Load the integer number into ACCU 1-L.
ITB // Convert from integer to BCD (16-bit); store result in ACCU 1-L.
T MW20 //Transfer result (BCD number) to MW20.

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BCD to Integer (32-Bit) ( BTD ):

BTD (decimal to binary conversion of a 7-digit BCD number) interprets the contents of ACCU 1 as a seven
digit binary coded decimal number (BCD) and converts it to a 32-bit double integer. The result is stored in
accumulator 1. Accumulator 2 remains unchanged.
BCD number in ACCU 1: The permissible value range for the BCD number is from "-9,999,999" to
"+9,999,999". Bit 0 to bit 27 are interpreted as the value and bit 31 as the sign (0 = positive, 1= negative)
of the BCD number. Bit 28 to bit 30 are not used in the conversion. If any decimal digit (a 4-bit tetrad of the
BCD coding) is in the invalid range of 10 to 15, a BCDF error occurs during attempted conversion. In
general, the CPU will go into STOP. However, you may design another error response by programming
OB121 to handle this synchronous programming error.
Example 1:
L MD10 //Load the BCD number into ACCU 1.
BTD //Convert from BCD to integer; store result in ACCU 1.
T MD20 //Transfer result (double integer number) to MD20.

Integer (16 Bit) to Double Integer (32-Bit) ( ITD ):

ITD (conversion of a 16-bit integer number to a 32-bit integer number) interprets the contents of ACCU 1-L
as a 16-bit integer and converts it to a 32-bit double integer. The result is stored in accumulator 1.
Accumulator 2 remains unchanged.
Example 1:
L MW12 // Load the integer number into ACCU 1.
ITD //Convert from int.(16-bit) to double int. (32-bit);store result in ACCU 1.
T MD20 //Transfer result (double integer) to MD20.
Example: MW12 = "-10" (Integer, 16-bit)

Double Integer (32-Bit) to BCD ( DTB ):

DTB (binary to decimal conversion of a 32-bit integer number) interprets the content of ACCU 1 as a 32-bit
double integer and converts it to a seven-digit binary coded decimal number (BCD).The result is stored in
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accumulator 1. Bit 0 to bit 27 contain the value of the BCD number. Bit 28 to bit 31 are set to the state of
the sign of the BCD number (0000 = positive, 1111 = negative). Accumulator 2 remains unchanged.
The BCD number can be in the range of "-9,999,999" to "+9,999,999". If the number is out of the
permissible range, then the status bits OV and OS are set to 1.
Example 1:
L MD10 // Load the 32-bit integer into ACCU 1.
DTB //Convert from integer (32-bit) to BCD, store result in ACCU 1.
T MD20 //Transfer result (BCD number) to MD20.

Double Integer (32-Bit) to Floating-Point (32-Bit IEEE-FP) ( DTR ):

DTR (conversion of a 32-bit integer number to a 32-bit IEEE floating point number) interprets the content
of ACCU 1 as a 32-bit double integer and converts it to a 32-bit IEEE floating point number. If necessary,
the instruction rounds the result. (A 32-bit integer has a higher accuracy than a 32-bit floating point
number). The result is stored in accumulator 1.
Example 1:
L MD10 //Load the 32-bit integer into ACCU 1.
DTR // Convert from double integer to floating point (32-bit IEEE FP); store result in
ACCU 1.
T MD20 //Transfer result (BCD number) to MD20.

Ones Complement Integer (16-Bit) ( INVI ):

INVI (ones complement integer) forms the ones complement of the 16-bit value in ACCU 1-L. Forming the
ones complement inverts the value bit by bit, that is, zeros replace ones and ones replace zeros. The
result is stored in the low word of accumulator 1.
Example 1:
L IW8 // Load value into ACCU 1-L.
INVI //Form ones complement 16-bit.
T MW10 //Transfer result to MW10.

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Ones Complement Double Integer (32-Bit) ( INVD ):

INVD (ones complement double integer) forms the ones complement of the 32-bit value in ACCU 1.
Forming the ones complement inverts the value bit by bit, that is, zeros replace ones, and ones replace
zeros. The result is stored in accumulator 1.
Example 1:
L ID8 // Load value into ACCU 1.
INVD //Form ones complement (32-bit).
T MD10 //Transfer result to MD10.

Twos Complement Integer (16-Bit) ( NEGI ):

NEGI (twos complement integer) forms the twos complement of the 16-bit value in ACCU1-L. Forming the
twos complement inverts the value bit by bit, i.e. zeros replace ones and ones replace zeros; then a "1" is
added. The result is stored in the low word of ACCU1. The twos complement instruction is equivalent to
multiplication by "-1." The status bits CC 1, CC 0, OS, and OV are set as a function of the result of the
operation.
Example 1:
L IW8 //Load value into ACCU 1-L.
NEGI // Form twos complement 16-bit.
T MW10 //Transfer result to MW10.

Twos Complement Double Integer (32-Bit) ( NEGD ):

NEGD (twos complement double integer) forms the twos complement of the 32-bit value in ACCU 1.
Forming the twos complement inverts the value bit by bit, that is, zeros replace ones and ones replace
zeros; then a "1" is added. The result is stored in accumulator 1. The twos complement instruction is
equivalent to a multiplication by "-1" The instruction is executed without regard to, and without affecting,
the RLO. The status bits CC 1, CC 0, OS, and OV are set as a function of the result of the operation.

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Example 1:
L ID8 // Load value into ACCU 1.
NEGD //Generate twos complement (32-bit).
T MD10 //Transfer result to MD10.

Negate Floating-Point Number (32-Bit, IEEE-FP) ( NEGR ):

NEGR (negate 32-bit IEEE floating-point number) negates the floating-point number (32-bit, IEEE-FP) in
ACCU1. The instruction inverts the state of bit 31 in ACCU1(sign of the mantissa). The result is stored in
accumulator 1.
Example 1:
L ID8 //Load value into ACCU 1 (example: ID 8 = 1.5E+02).
NEGR //Negate floating-point number (32-bit,IEEE-FP); stores the result in ACCU1.
T MD10 //Transfer result to MD10 (example: result = -1.5E+02).

Change Byte Sequence in ACCU 1-L (16-Bit) ( CAW ):

CAW reverses the sequence of bytes in ACCU 1-L. The result is stored in the low word of accumulator 1.
The high word of accumulator 1 and accumulator 2 remain unchanged.
Example 1:
L MW10 //Load the value of MW10 into ACCU 1.
CAW //Reverse the sequence of bytes in ACCU 1-L.
T MW20 //Transfer the result to MW20.

Change Byte Sequence in ACCU 1 (32-Bit) ( CAD ):

CAD reverses the sequence of bytes in ACCU 1. The result is stored in accumulator 1. Accumulator 2
remains unchanged.
Example 1:
L MD10 //Load the value of MD10 into ACCU 1.
CAD // Reverse the sequence of bytes in ACCU 1.
T MD20 //Transfer the results to MD20.

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Round (RND):
RND (conversion of a 32-bit IEEE floating-point number to 32-bit integer) interprets the contents of ACCU
1 as a 32-bit IEEE floating-point number (32-bit, IEEE-FP). The instruction converts the 32-bit IEEE
floating-point number to a 32-bit integer (double integer) and rounds the result to the nearest whole
number. If the fractional part of the converted number is midway between an even and an odd result, the
instruction chooses the even result. If the number is out of the permissible range, then the status bits OV
and OS are set to 1. The result is stored in accumulator 1. Conversion is not performed and an overflow
indicated in the event of a fault (utilization of a NaN or a floating-point number that cannot be represented
as a 32-bit integer number).
Example 1:
L MD10 //Load the floating-point number into ACCU 1-L.
RND //Convert the floating-point number (32-bit, IEEE-FP) into an integer (32-bit) and
round off the result.
T MD20 //Transfer result (double integer number) to MD20.

Truncate (TRUNC):
TRUNC (conversion of a 32-bit IEEE floating-point number to 32-bit integer) inter-prets the contents of
ACCU1 as a 32-bit IEEE floating-point number. The instruction converts the 32- bit IEEE floating-point
number to a 32-bit integer (double integer). The result is the whole number part of the floating-point
number to be converted (IEEE rounding mode "round to zero"). If the number is out of the permissible
range, then the status bits OV and OS are set to 1. The result is stored in accumulator 1. Conversion is not
performed and an overflow indicated in the event of a fault (utilization of a NaN or a floating-point number
that cannot be represented as a 32-bit integer number).
Example 1:
L MD10 // Load the floating-point number into ACCU 1-L.
TRUNC //Convert the floating-point number (32-bit, IEEE-FP) to an integer (32-bit) and
round result. Store the result in ACCU 1.
T MD20 // Transfer result (double integer number) to MD20.

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Round to Upper Double Integer ( RND+ ):

RND+ (conversion of a 32-bit IEEE floating-point number to 32-bit integer) inter-prets the contents of
ACCU 1 as a 32-bit IEEE floating-point number. The instruction converts the 32-bit IEEE floating-point
number to a 32-bit integer (double integer) and rounds the result to the smallest whole number greater
than or equal to the floating-point number that is converted (IEEE rounding mode "round to +infinity"). If the
number is out of the permissible range, then the status bits OV and OS are set to 1.The result is stored in
accumulator 1. Conversion is not performed and an overflow is indicated in the event of a fault (utilization
of a NaN or a floating-point number that cannot be represented as a 32-bit integer number.)
Example 1:
L MD10 // Load the floating-point number (32-bit, IEEE-FP) into ACCU 1-L.
RND+ //Convert the floating-point number (32-bit, IEEE-FP) to an integer (32-bit) and
round result. Store output in ACCU 1.
T MD20 //Transfer result (double integer number) to MD20.

Round to Lower Double Integer ( RND- ):

RND- (conversion of a 32-bit IEEE floating-point number to 32-bit integer) inter-prets the contents of ACCU
1 as 32-bit IEEE floating-point number. The instruction converts the 32-bit IEEE floating-point number to a
32-bit integer (double integer) and rounds the result to the largest whole number less than or equal to the
floating-point number that is converted (IEEE rounding mode "round to -infinity"). If the number is out of the
permissible range, then the status bits OV and OS are set to 1. The result is stored in accumulator 1.
Example 1:
L MD10 //Load the floating-point number into ACCU 1-L.
RND- //Convert the floating-point number (32-bit, IEEE-FP) to an integer
(32-bit) and round result. Store result in ACCU 1.
T MD20 // Transfer result (double integer number) to MD20.

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3.8 Timer Functions:

Timer functions are used to implement timing sequences. For example waiting and monitoring times,
measuring of time intervals, generation of pulses.The timer functions are stored in system memory of
the CPU. The following timer types are available:
Pulse Timer
Extended Pulse Timer
On delay Timer
Retentive On_Delay Timer
Off_Delay Timer
Timers have an area reserved for them in the memory of your CPU. This memory area reserves one
16-bit word for each timer address. The ladder logic instruction set supports 256 timers. Please refer to
your CPU’s technical information to establish the number of timer words available. The following
functions have access to the timer memory area:
Timer instructions
Updating of timer words by means of clock timing.
This function of your CPU in the RUN mode decrements a given time value by one unit at the interval
designated by the time base until the time value is equal to zero.
For any timer there are three inputs and three outputs as shown in the below figure.

Time Value: Bits 0 through 9 of the timer word contain the time value in binary code. The time value
specifies a number of units. Time updating decrements the time value by one unit at an interval designated
by the time base. Decrementing continues until the time value is equal to zero. You can load a time value
into the low word of accumulator 1 in binary, hexadecimal, or binary coded decimal (BCD) format.
You can pre-load a time value using either of the following formats:
W#16#wxyz
Where w = the time base (that is, the time interval or resolution)
Where xyz = the time value in binary coded decimal format
S5T#aH_bM_cS_dMS
Where H = hours, M = minutes, S = seconds, and MS = milliseconds; a, b, c, d are defined
by the user.
The time base is selected automatically, and the value is rounded to the next lower number
with that time base.
The maximum time value that you can enter is 9,990 seconds, or 2H_46M_30S.

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Time Base: Bits 12 and 13 of the timer word contain the time base in binary code. The time base
defines the interval at which the time value is decrement by one unit. The smallest time base is 10 ms;
the largest is 10 s.
Time Base Binary Code for the Time Base
10 ms 00
100 ms 01
1s 10
10 s 11
Values that exceed 2h46m30s are not accepted. A value whose resolution is too high for the range
limits (for example, 2h10ms) is truncated down to a valid resolution. The general format for S5TIME has
limits to range and resolution as shown below:
Resolution Range
0.01 second 10MS to 9S_990MS
0.1 second 100MS to 1M_39S_900MS
1 second 1S to 16M_39S
10 seconds 10S to 2H_46M_30S

Bit Configuration in the ACCU1: When a timer is started, the contents of ACCU1 are used as the time
value. Bits 0 through 11 of the ACCU1-L hold the time value in binary coded decimal format (BCD formats:
each set of four bits contains the binary code for one decimal value). Bits 12 and 13 hold the time base in
binary code. The following figure shows the contents of the timer cell loaded with timer value 127 and a
time base of 1 second:

S5TIME Data Type for Time Value:

Data Type Length (bits) Format Format Examples
S5time 16 bits s5t#_h__m__s__ms s5t#10ms, s5t#2H30m45s

Choosing the right Timer: This overview is intended to help you choose the right timer for your timing
job.

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FR Enable Timer (Free):

When the RLO transitions from "0" to "1", FR <timer> clears the edge-detecting flag that is used for
starting the addressed timer. A change in the RLO bit from 0 to 1 in front of an enable instruction (FR)
enables a timer. Timer enable is not required to start a timer, nor is it required for normal timer
instruction. An enable is used only to re-trigger a running timer, that is, to restart a timer. The restarting
is possible only when the start instruction continues to be processed with RLO = 1.

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Tim ers: Tim e Form ats for S5 Tim ers in STEP 7

10 2 10 1 10 0

Format for time specifications X X

Time base Time value (BCD code)

Timer cell in system data memory X X X X

Time base Time value (Binary number)

ACC U contents after “L T...” X X X X X X

Time value (Binary number)

10 2 10 1 10 0

ACC U contents after “LC T...” X X

Time base Time value (BCD code)

Time Specifications:
Fixed time values specified as time constants (e.g.: S5T#100ms, S5T#35s, S5T#5m2s200ms,
S5T#2h2m2s50ms).
Time values to be changed by the machine operator using pushwheel buttons.
Process or recipe-dependent time values in memory words or data words.

Timer Cell: A special area of memory is reserved for timers in your CPU. This area contains a 16-bit word
for each timer address. bits 0 to 9 of the timer word contain the time value in binary code. When the timer
is updated, the time value is decremented by one unit at the interval defined by the time base.

L / BI: The address at the “BI” output contains the time value in the form of a 10-digit binary number
(without time base!).

LC / BCD: The address at the “BCD” output contains both the time value as a 3-digit BCD number (12bits)
and the time format (bits 12 and 13).

Note: IEC-compliant timers can also be implemented in STEP7. The system function blocks need to be
used for implementing IEC timers.

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Pulse Timer: S_PULSE (Pulse S5 Timer) starts the specified timer if there is a positive edge at the start
(S) input. A signal change is always necessary in order to enable a timer. The timer runs as long as the
signal state at input S is "1", the longest period, however, is the time value specified by input TV. The
signal state at output Q is "1" as long as the timer is running. If there is a change from "1" to "0" at the S
input before the time interval has elapsed the timer will be stopped. In this case the signal state at output Q
is "0". The timer is reset when the timer reset (R) input changes from "0" to "1" while the timer is running.
The current time and the time base are also set to zero. Logic "1" at the timer's R input has no effect if the
timer is not running. The current time value can be scanned at the outputs BI and BCD. The time value at
BI is binary coded, at BCD it is BCD coded. The current time value is the initial TV value minus the time
elapsed since the timer was started.

Program in LAD, FBD and STL:

LAD FBD STL

T4 T4 A I 0.7
I 0.7 S_PULSE Q8.5 S_PULSE L S5T#35s
S Q I 0.7 S BI MW0 SP T4
S5T#35s BI MW0 A I 0.5
TV S5T#35s TV BCD QW12
I 0.5 Q8.5 R T4
R BCD QW12 I 0.5 R = L T4
Q
T MW0
LC T4
T QW12
A T4
= Q8.5

If the signal state of input I0.7 changes from "0" to "1" (positive edge in RLO), the timer T4 will be
started. The timer will continue to run for the specified time of thirty five seconds (35 s) as long as I0.7
is "1". If the Signal State of I0.7 changes from "1" to "0" before the timer has expired the timer will be
stopped. If the Signal State of input I0.5 changes from "0" to "1" while the timer is running, the time is
reset. The output Q8.5 is logic "1" as long as the timer is running and "0" if the time has elapsed or
was reset.

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Extended Pulse Timer: S_PEXT (Extended Pulse Timer) starts the specified timer if there is a positive
edge at the start (S) input. A signal change is always necessary in order to enable a timer. The timer
runs for the preset time interval specified at input TV even if the signal state at the S input changes to
"0" before the time interval has elapsed. The signal state at output Q is "1" as long as the timer is
running. The timer will be restarted ("re-triggered") with the preset time value if the signal state at input
S changes from "0" to "1" while the timer is running. The timer is reset if the reset (R) input changes
from "0" to "1" while the timer is running. The current time and the time base are set to zero. The
current time value can be scanned at the outputs BI and BCD. The time value at BI is binary coded, at
BCD is BCD coded. The current time value is the initial TV value minus the time elapsed since the timer
was started.

Program in LAD, FBD and STL:

LAD FBD STL

T4 T4 A I 0.7
I 0.7 S_PEXT Q8.5 S_PEXT L S5T#35s
S Q MW0 SE T4
I 0.7 S BI
S5T#35s TV BI MW0 A I 0.5
S5T#35s TV BCD QW12
I 0.5 A8.5 R T4
R BCD QW12 I 0.5 R L T4
Q =
T MW0
LC T4
T QW12
A T4
= Q8.5

If the signal state of input I0.7 changes from "0" to "1" (positive edge in RLO), the timer T4 will be
started. The timer will continue to run for the specified time of thirty five seconds (35 s) even if I0.7 is
"0". If the Signal State of input I0.5 changes from "0" to "1" while the timer is running, the timer is reset.
The output Q8.5 is logic "1" as long as the timer is running and "0" if the time has elapsed or was
reset. Also the output Q8.5 does not depend on the Input I0.7.

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On-Delay Timer: S_ODT (On-Delay S5 Timer) starts the specified timer if there is a positive edge at
the start (S) input. A signal change is always necessary in order to enable a timer. The timer runs for
the time interval specified at input TV as long as the Signal State at input S is positive. The signal state
at output Q is "1" when the timer has elapsed without error and the signal state at the S input is still "1".
When the Signal State at input S changes from "1" to "0" while the timer is running, the timer is stopped.
In this case the signal state of output Q is "0". The timer is reset if the reset (R) input changes from "0"
to "1" while the timer is running. The current time and the time base are set to zero. The signal state at
output Q is then "0". The timer is also reset if there is a logic "1" at the R input while the timer is not
running and the RLO at input S is "1". The current time value can be scanned at the outputs BI and
BCD. The time value at BI is binary coded, at BCD is BCD coded. The current time value is the initial
TV value minus the time elapsed since the timer was started.

Program in LAD, FBD and STL:

LAD FBD STL

T4 T4
I 0.7 S_ODT Q8.5 S_ODT A I 0.7
S Q I 0.7 S BI MW0 L S5T#35s
S5T#35s TV BI MW0 S5T#35s QW12
SD T4
TV BCD
I 0.5 Q8.5 A I 0.5
R BCD QW12 I 0.5 R Q = R T4
L T4
T MW0
LC T4
T QW12
A T4
= Q8.5

If the signal state of input I0.7 changes from "0" to "1" (positive edge in RLO), the timer T4 will be
started. The timer will continue to run for the specified time of thirty five seconds (35 s) as long as if I0.7
is "1". If the Signal State of input I0.5 changes from "0" to "1" while the timer is running, the timer is
reset. The output Q8.5 is logic "1" only when timer is elasped and "0" if the input I0.7 is “0”.

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Retentive On-Delay S5 Timer: S_ODTS (Retentive On-Delay S5 Timer) starts the specified timer if
there is a positive edge at the start (S) input. A signal change is always necessary in order to enable a
timer. The timer runs for the time interval specified at input TV even if the signal state at input S changes
to "0" before the time interval has elapsed. The signal state at output Q is "1" when the timer has
elapsed without regard to the signal state at input S. The timer will be restarted (re-triggered) with the
specified time if the signal state at input S changes from "0" to "1" while the timer is running. The timer is
reset if the reset (R) input changes from "0" to "1" without regard to the RLO at the S input. The signal
state at output Q is then "0". The current time value can be scanned at the outputs BI and BCD. The
time value at BI is binary coded, at BCD it is BCD coded. The current time value is the initial TV value
minus the time elapsed since the timer was started.

Program in LAD,FBD and STL:

LAD FBD STL

T4 T4 A I 0.7
I 0.7 S_ODTS Q8.5 S_ODTS L S5T#35s
S Q I 0.7 S BI MW0 SS T4
S5T#35s BI MW0 A I 0.5
TV S5T#35s TV BCD QW12
I 0.5 Q8.5 R T4
R BCD QW12 I 0.5 R Q = L T4
T MW0
LC T4
T QW12
A T4
= Q8.5

If the signal state of I0.7 changes from "0" to "1" (positive edge in RLO), the timer T4 will be started.
The timer runs without regard to a signal change at I0.7 from "1" to "0". If the signal state at I0.7
changes from "0" to "1" before the timer has expired, the timer will be re-triggered. The output Q8.5 will
be "1" if the timer elapsed. If the signal state of input I0.5 changes from "0" to "1", the time will be reset
irrespective of the RLO at S.

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Off-Delay Timer: S_OFFDT (Off-Delay S5 Timer) starts the specified timer if there is a negative edge
at the start (S) input. A signal change is always necessary in order to enable a timer. The signal state at
output Q is "1" if the signal state at the S input is "1" or while the timer is running. The timer is reset
when the signal state at input S goes from "0" to "1" while the timer is running. The timer is not restarted
until the signal state at input S changes again from "1" to "0".The timer is reset when the reset (R) input
changes from "0" to "1" while the timer is running.The current time value can be scanned at the outputs
BI and BCD. The time value at BI is binary coded, at BCD it is BCD coded. The current time value is the
initial TV value minus the time elapsed since the timer was started.

Program in LAD, FBD and STL:

LAD FBD STL

T4 T4 A I 0.7
I 0.7 S_OFFDT Q8.5 S_OFFDT L S5T#35s
S Q I 0.7 S BI MW0 SF T4
S5T#35s BI MW0 A I 0.5
TV S5T#35s TV BCD QW12
I 0.5 Q8.5 R T4
R BCD QW12 I 0.5 R Q = L T4
T MW0
LC T4
T QW12
A T4
= Q8.5

If the signal state of I0.7 changes from "1" to "0" (negative edge in RLO), the timer T4 will be started.
The timer runs without regard to a signal change at I0.7. If the signal state at I0.7 changes from "0" to
"1" before the timer has expired, the timer will be re-triggered. The output Q8.5 will be "1" as soon as
I0.7 is “1” & resets only when timer is elapsed. If the signal state of input I0.5 changes from "0" to "1",
the time will be reset & output becomes zero.

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Bit Instruction for Timer: All timer functions can also be started with simple bit instructions. The
similarities and differences between this method and the timer functions discussed so far are as follows:
Similarities:
Start conditions at the "S" input
Specification of the time value
Reset conditions at the “R” input
Signal response at output “Q”
Differences (for LAD and FBD):
It is not possible to check the current time value (there are no BI and BCD outputs).
Example:

LAD FBD STL

Network 1:
T4
I 0.0 T4 I 0.0 & SD A I 0.0
SD L S5T#5s
S5T#5s TV SD T4
S5T#5s

Network 2:

T4 Q 8.0 Q 8.0
A T4
T4 & =
= Q 8.0

Network 3:
T4
I 0.1 T4 A I 0.1
R I 0.1 & R R T4

3.9 Counter Functions:

Counters have an area reserved for them in the memory of your CPU. This memory area reserves one 16-
bit word for each counter address. The ladder logic instruction set supports 256 counters. The counter
instructions are the only functions that have access to the counter memory area.

Bit Configuration in the Counter:

You provide a counter with a preset value by entering a number from 0 to 999, for example 127, in the
following format: C#127. The C# stands for binary coded decimal format (BCD format: each set of four bits
contains the binary code for one decimal value). Bits 0 through 11 of the counter contain the count value in
binary coded decimal format. The following figure shows the contents of the counter after you have loaded
the count value 127, and the contents of the counter cell after the counter has been set.

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Count Value: Bits 0 through 9 of the counter word contain the count value in binary code. The count value
is moved to the counter word when a counter is set. The range of the count value is 0 to 999. You can vary
the count value within this range by using the following counter instructions:
S_CUD Up-Down Counter
S_CD Down Counter
S_CU Up Counter
---( SC ) Set Counter Coil
---( CU ) Up Counter Coil
---( CD ) Down Counter Coil

Counters in STEP 7:

LA D FBD STL

A I0 .4
C5 C5
CU C5
S _C U D S _C U D
I 0.4 Q 8.3 A I0 .5
CU Q
Q I 0.4 CU CD C5
A I0 .3
I 0.5
L C #2 0
CD I 0.5 CD
S C5
I 0.3 A I0 .7
S I 0.3 S CV MW 4 R C5
L C5
C #2 0 PV CV MW 4 C #2 0 PV C V_ BC D QW 12 T MW4
Q 8 .3 LC C5
I 0.7
R CV _B C D QW 12 I 0.7 R Q
Q = T Q W 12
A C5
= Q 8.3

Counter Value: A 16-bit word is reserved for each counter in the system data memory. This is used for
storing the counter value for the counter (0...999) in binary code.

Count Up: When the RLO at the "CU" input changes from "0" to "1" the current counter reading is
incremented by 1 (upper limit = 999).

Count Down: When the RLO at the "CD" input changes from "0" to "1" the current counter reading is
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decremented by 1 (lower limit = 0).

Set Counter: When the RLO at the "S" input changes from "0" to "1" the counter is set to the value
at the "CV" input.

Reset Counter:When RLO = 1 the counter is set to zero. If the Reset condition is fulfilled, the counter
cannot be set and counting is not possible.

PV:The preset value (0...999) is specified in BCD at the "PV" input. It is as a constant (C#...) in BCD
format via a data interface.

CV / CV_BCD: The counter value can be loaded as a binary number or BCD number into the accumulator
and transferred from there to other addresses.

Q: The signal state of the counter can be checked at output "Q":

Count = 0 Q=0
Count >< 0 Q=1

Types of Counter:
S_CU = Up counter (counts up only)
S_CD = Down counter (counts down only)
S_CUD = Up/Down counter.

CU

CD

5
4
3
Count
2
1
0

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Notes: If the counter reaches the value 999 during up counting, or the value 0 during down counting, then
the count remains unchanged even in the case of further counting pulses.If up counting and down
counting is lined up at the same time, the count remains the same.

Counters: Bit Instructions:

LA D FBD STL

N etw ork 1: C5
I 0 .0 SC
I 0.0 C5
A I 0 .0
SC L C#20
C # 20 CV
C#20 S C5
N etw ork 2:
C5
I 0.1 C5
I 0 .1 CU A I 0 .1
CU
CU C5

N etw ork 3:
I 0.2 C5 C5
A I 0 .2
CD I 0 .2 CD CD C5

N etw ork 4:
C5 Q 4.0 Q 4.0
A C5
C5 = = Q 4 .0

Bit Instructions: All counter functions can also operate with simple bit instructions. The similarities and
differences between this method and the counter functions discussed so far are as follows:
Similarities:
Setting conditions at the "SC" input
Specification of the counter value
RLO change at the "CU" input
RLO change at the "CD" input
Differences:
It is not possible to check the current counter value (there are no BI and BCD outputs).
There is no binary output Q in the graphical representation.

Note: IEC-compliant counters can also be implemented in STEP 7. The use of system function blocks for
implementing IEC counters is dealt with in an advanced programming course.

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