Chapter 11

Input-Output
Organization
Input-Output Organization
 Important Terms
Peripherals

ASCII (American Standard Code for Information Interchange) Alphanumeric Characters

Isolated IO
ISOLATED VERSUS MEMORY MAPPED I/O

Many computers use one common bus to transfer information between

memory or I/O and the CPU.

The distinction between a memory transfer and I/O transfer is made

through separate read and write lines.

The CPU specifies whether the address on the address lines is for a
memory word or for an interface register by enabling one of two possible
read or write lines.

The I/O read and I/O writes control lines are enabled during an I/O transfer.
The memory read and memory write control lines are enabled during a
memory transfer.

This configuration isolates all I/O interface addresses from the address
assigned to memory and is referred to as the isolated I/O method for
assigning addresses in a common bus.
ISOLATED I/O
In the isolated I/O configuration, the CPU has distinct input and output
instructions and each of these instructions are associated with the
address of an interface register.

When the CPU fetches and decodes the operation code of an input or
output instruction, it places the address associated with the instruction
into the common address lines.

At the same time, it enables the I/O read (for input) or I/O write (for output)
control line.
This informs the external components that are attached to the common
bus that the address in the address lines is for an interface register and
not for a memory word.

When the CPU is fetching an instruction or an operand from memory, it

places the memory address on the address lines and enables the
memory read or memory write control lines. This informs the external
components that the address is for a memory word and not for an I/O
interface.
MEMORY MAPPED I/O
The isolated I/O method isolates memory and I/O addresses so that memory
address values are not affected by interface address assignment since each has
its own address space.
The memory mapped I/O uses the same address space for both memory and I/O.

This is the case in computers that employ only one set of read and write signals
and do not distinguish between memory and I/O addresses.
The computer treats an interface register as being part of the memory system.
The assigned addresses for interface registers cannot be used for memory
words, which reduce the memory address( range available).
In memory mapped I/O organization, there are no specific inputs or output
instructions. The CPU can manipulate I/O data residing in interface registers with
the same instructions that are used to manipulate memory words.
Typically, a segment of the total address space is reserved for interface registers,
but in general, they can be located at any address as long as there is not also a
memory word that responds to the same address.
It allows the computer to use the same instructions for either input-output
transfers or for memory transfers.
There are two ways can be used to achieve that

1-Strobe
2-Handshaking
PROGRAM-CONTROLLED I/O
Read status register

Check flag bit

Input Device to CPU

=0
Flag
Data bus Interface I/O bus

=1
Address bus Data register

CPU
Data valid I/O Read data register
I/O read device

Status
I/O write F
register Data accepted
Transfer data to memory

F = Flag bit

Operation no
complete ?

• Continuous CPU involvement yes

• CPU slowed down to I/O speed Continue

• Simple with
program
• Least hardware
INTERRUPT-INITIATED I/O
- Polling takes valuable CPU time
- Open communication only when some data has to be passed -> Interrupt.
- I/O interface, instead of the CPU, monitors the I/O device
- When the interface determines that the I/O device is ready for data
transfer, it generates an Interrupt Request to the CPU.
- Upon detecting an interrupt, CPU stops momentarily the task it is doing,
branches to the service routine to process the data transfer, and then
returns to the task it was performing.

THE INTERRUPT MAY BE:

1) Non-vectored : fixed branch address
2) Vectored : interrupt source supplies the branch address (interrupt
vector)
Software Considerations
• I/O routines
– software routines for controlling peripherals and for transfer of data
between the processor and peripherals
• I/O routines for standard peripherals are provided by the manufacturer
(Device driver, OS or BIOS)
• I/O routines are usually included within the operating system
• I/O routines are usually available as operating system procedures ( OS
or BIOS function call).

Priority Interrupt
• Identify the source of the interrupt when several sources will request
service simultaneously
• Determine which condition is to be serviced first when two or more
requests arrive simultaneously
• Techniques used:
– 1) Software : Polling
– 2) Hardware : Daisy chain, Parallel priority
 PRIORITY INTERRUPT

Priority Interrupt by Software (Polling)

- Priority is established by the order of polling the devices(interrupt sources)
- Flexible since it is established by software
- Low cost since it needs a very little hardware
- Very slow

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts all the interrupt requests to
determine the highest priority request
-Fast since identification of the highest priority interrupt request is identified by
the hardware
- Fast since each interrupt source has its own interrupt vector to access
directly to its own service routine
Daisy-Chaining Priority
Daisy-Chaining

Processor data bus

VAD 1 VAD 2 VAD 3

“1” Device 1 “1” Device 2 “0” Device 3

To next
PI PO PI PO PI PO
Device

Interrupt request
INT
CPU
Interrupt acknowledge
INTACK
 One stage of the daisy-chain priority arrangement

VAD

INTACK Priority in
PI Enable
Vector address

INT Priority out

RF PO
Interrupt S Q
request
from device PI RF PO Enable
R
 0 0 0 0
Delay  0 1 0 0
Open-collector  1 0 1 0
inverter Interrupt request to CPU  1 1 1 1

 No interrupt request
 Invalid : interrupt request, but no acknowledge
 No interrupt request : Pass to other device (other device requested interrupt )
 Interrupt request
 Interrupt
register
VAD
disk 0 to CPU
I0
y
x
Printer 1
I1
Priority 0
encoder
0
Reade 2
I2
r 0
0
Keyboard 3
I3
0
0

Enable
IEN IST

Interrupt Enable F/F (IEN) :

set or cleared by the program.
0

Interrupt Status F/F (IST) : Interrupt

1 to CPU
set or cleared by the encoder
output
2 INTACK
from CPU

Mask
register
Software Routines
Initial Operation of ISR

1) Clear lower-level mask register bit

2) Clear interrupt status bit IST
3) Save contents of processor registers
4) Set interrupt enable bit IEN
5) Proceed with service routine

Final Operation of ISR

1) Clear interrupt enable bit IEN

2) Restore contents of processor registers
3) Clear the bit in the interrupt register
belonging to the source that has been serviced
4) Set lower-level priority bits in the mask register
5) Restore return address into PC and set IEN
DIRECT MEMORY ACCESS (DMA)

The transfer of data between a fast storage device such as magnetic

disk and memory is often limited by the speed of the CPU.

Removing the CPU from the path and letting the peripheral device
manage the memory buses directly would improve the speed of
transfer.

This transfer technique is called direct memory access (DMA).

During DMA transfer, the CPU is idle and has no control of the memory
buses. A DMA controller takes over the buses to manage the transfer
directly between the I/O device and memory.
CPU bus signals for DMA transfer

There are two modes of transfer:

Burst transfer and cycle stealing
Block Diagram of DMA Controller
DMA Transfer in a Computer System
Block diagram of a computer with I/O processor