PIC12F629/675

Memory Programming Specification

This document includes the FIGURE 1-1: 8-PIN DIAGRAM FOR
programming specifications for the PIC12F629
following devices: PDIP, SOIC, DFN-S
• PIC12F629
VDD 1 8 VSS

PIC12F629/675
• PIC12F675
GP5/T1CK/OSC1/ GP0/CIN+/
CLKIN 2 7 ICSPDAT
GP4/T1G/OSC2/ GP1/CIN-/VREF/
1.0 PROGRAMMING THE CLKOUT 3 6 ICSPCLK
PIC12F629/675 GP3/MCLR/VPP 4 5
GP2/COUT/
T0CK/INT
The PIC12F629/675 is programmed using a serial
method. The Serial mode will allow the PIC12F629/675
to be programmed while in the user’s system. This FIGURE 1-2: Pin Diagram
allows for increased design flexibility. This
SSOP
programming specification applies to PIC12F629/675
devices in all packages.
VDD •1 20 VSS

rfPIC12F675F/H/K
GP5/T1CKI/OSC1/CLKIN 2 19 GP0/CIN+/ICSPDAT
1.1 Hardware Requirements GP4/T1G/OSC2/CLKOUT 3 18 GP1/CIN-/ICSPCLK
GP3/MCLR/VPP 4 17 GP2/T0CKI/INT/COUT
RFXTAL 5 16 FSKOUT
The PIC12F629/675 requires one power supply for RFEN 6 15 DATAFSK
VDD (5.0V) and one for VPP (12V). CLKOUT 7 14 DATAASK
PS 8 13 LF
VDDRF 9 12 VSSRF
1.2 Programming Mode VSSRF 10 11 ANT

The Programming mode for the PIC12F629/675 allows

programming of user program memory, data memory,
special locations used for ID, and the configuration
word.

TABLE 1-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC12F629/675

During Programming
Pin Name
Function Pin Type Pin Description
GP1 CLOCK I Clock input – Schmitt Trigger input
GP0 DATA I/O Data input/output – TTL input
MCLR Programming mode P(1) Program Mode Select
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
Note 1: In the PIC12F629/675, the programming high voltage is internally generated. To activate the Programming
mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, this
means that MCLR does not draw any significant current.

 2003 Microchip Technology Inc. Preliminary DS41173C-page 1

PIC12F629/675
2.0 PROGRAM MODE ENTRY 2.2 ID Locations
A user may store identification information (ID) in four
2.1 User Program Memory Map
ID locations. The ID locations are mapped in [0x2000 :
The user memory space extends from 0x0000 to 0x2003]. It is recommended that the user use only the
0x1FFF. In Programming mode, the program memory seven Least Significant bits (LSb) of each ID location.
space extends from 0x0000 to 0x3FFF, the first half Locations read out normally, even after code protec-
(0x0000-0x1FFF) is user program memory and the tion. The ID locations read out in an unscrambled
second half (0x2000-0x3FFF) is configuration memory. fashion after code protection is enabled. It is
The PC will increment from 0x0000 to 0x1FFF and recommended that ID location is written as “xx xxxx
wrap to 0x000, 0x2000 to 0x3FFF and wrap around to xbbb bbbb” where ‘bbb bbbb’ is ID information.
0x2000 (not to 0x0000). Once in configuration memory, The 14 bits may be programmed, but only the LSbs are
the highest bit of the PC remains a ‘1’, thus always displayed by MPLAB® IDE. xxxx’s are “don’t care” bits
pointing to the configuration memory. The only way to as they won’t be read by MPLAB IDE.
point to the user program memory is to reset the part
and re-enter Program/Verify mode as described in
Section 2.3.
In the configuration memory space, 0x2000-0x201F
are physically implemented. However, only locations
0x2000 through 0x2003, and 0x2007 are available.
Other locations are reserved.

FIGURE 2-1: PROGRAM MEMORY MAPPING

1 KW

Implemented
03FE
03FF 03FF
OSCCAL Implemented

400

Maps to
0 - 3FF

1FFF
2000 ID Location
2000
Implemented
2001 2008
ID Location Reserved
201F
2002
ID Location

2003
ID Location

2004
Reserved
Maps to
2000 - 201F
2005
Reserved

2006
Reserved

2007
Configuration Word 3FFF

DS41173C-page 2 Preliminary  2003 Microchip Technology Inc.

 PIC12F629/675
2.3 Program/Verify Mode A device RESET will clear the PC and set the address
to ‘0’. The Increment Address command will increment
The Program/Verify mode is entered by holding pins the PC. The Load Configuration command will set the
CLOCK and DATA low while raising MCLR pin from VIL PC to 0x2000. The available commands are shown in
to VIHH (high voltage). Apply VDD and data. Once in this Table 2-1.
mode, the user program memory, data memory and the
configuration memory can be accessed and 2.3.1 SERIAL PROGRAM/VERIFY
programmed in serial fashion. CLOCK is Schmitt OPERATION
Trigger and DATA is TTL input in this mode. GP4 is
tristate, regardless of fuse setting. The CLOCK pin is used as a clock input pin, and the
DATA pin is used for entering command bits and data
The sequence that enters the device into the Program-
input/output during serial operation. To input a
ming/Verify mode places all other logic into the RESET
command, the clock pin (CLOCK) is cycled six times.
state (the MCLR pin was initially at VIL). This means
Each command bit is latched on the falling edge of the
that all I/O are in the RESET state (hi-impedance
clock with the LSb of the command being input first.
inputs).
The data on pin DATA is required to have a minimum
setup and hold time (see AC/DC specifications), with
FIGURE 2-2: ENTERING HIGH VOLTAGE respect to the falling edge of the clock. Commands that
PROGRAM/VERIFY MODE have data associated with them (Read and Load) are
TPPDP THLD0 specified to have a minimum delay of 1 µs between the
command and the data. After this delay, the clock pin is
cycled 16 times with the first cycle being a START bit
and the last cycle being a STOP bit. Data is also input
VPP and output LSb first.
Therefore, during a read operation the LSb will be
VDD transmitted onto pin DATA on the rising edge of the
second cycle. During a load operation, the LSb will be
DATA latched on the falling edge of the second cycle. A
minimum 1 µs delay is also specified between
CLOCK consecutive commands.
SDATA = Input All commands are transmitted LSb first. Data words
are also transmitted LSb first. The data is transmitted
on the rising edge and latched on the falling edge of
The normal sequence for programming is to use the the clock. To allow for decoding of commands and
Load Data command to set a value to be written at the reversal of data pin configuration, a time separation of
selected address. Issue the Begin Programming at least 1 µs is required between a command and a
command followed by Read Data command to verify data word (or another command).
and then increment the address.

TABLE 2-1: COMMAND MAPPING FOR PIC12F629/675

Command Mapping (MSb … LSb) Data
Load Configuration X X 0 0 0 0 0, data (14), 0
Load Data for Program Memory X X 0 0 1 0 0, data (14), 0
Load Data for Data Memory X X 0 0 1 1 0, data (8), zero (6), 0
Read Data from Program Memory X X 0 1 0 0 0, data (14), 0
Read Data from Data Memory X X 0 1 0 1 0, data (8), zero (6), 0
Increment Address X X 0 1 1 0
Begin Programming 0 0 1 0 0 0 Internally Timed
Begin Programming 0 1 1 0 0 0 Externally Timed
End Programming 0 0 1 0 1 0
Bulk Erase Program Memory X X 1 0 0 1 Internally Timed
Bulk Erase Data Memory X X 1 0 1 1 Internally Timed

 2003 Microchip Technology Inc. Preliminary DS41173C-page 3

PIC12F629/675
2.3.1.1 Load Configuration
After receiving this command, the program counter
(PC) will be set to 0x2000. Then, by applying 16 cycles
to the clock pin, the chip will load 14 bits in a “data
word,” as described above, which will be programmed
into the configuration memory. A description of the
memory mapping schemes of the program memory for
normal operation and Configuration mode operation is
shown in Figure 2-1. After the configuration memory is
entered, the only way to get back to the user program
memory is to exit the Program/Verify mode by taking
MCLR low (VIL).

FIGURE 2-3: LOAD CONFIGURATION COMMAND

1 2 3 4 5 6 Tdly2 1 2 3 4 5 15 16
GP1
CLOCK

GP0 0 00 0 0 X X strt_bit LSb MSb stp_bit

DATA Tset1
Tdly1
Thld1

2.3.1.2 Load Data For Program Memory

After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. A timing diagram for the Load
Data command is shown in Figure 2-4.

FIGURE 2-4: LOAD DATA FOR PROGRAM MEMORY COMMAND

1 2 3 4 5 6 Tdly2 1 2 3 4 5 15 16
GP1
CLOCK

GP0 0 1 0 0 X X strt_bit LSb MSb stp_bit

DATA Tset1 Tset1
Tdly1
Thld1 Thld1

DS41173C-page 4 Preliminary  2003 Microchip Technology Inc.

 PIC12F629/675
2.3.1.3 Load Data For Data Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied.
However, the data memory is only 8-bits wide and thus,
only the first 8 bits of data after the START bit will be
programmed into the data memory. It is still necessary
to cycle the clock the full 16 cycles in order to allow the
internal circuitry to reset properly. The data memory
contains 128 bytes. Only the lower 8 bits of the PC are
decoded by the data memory, and therefore, if the PC
is greater than 0x7F, it will wrap around and address a
location within the physically implemented memory.

FIGURE 2-5: LOAD DATA FOR DATA MEMORY COMMAND

Tdly2

1 2 3 4 5 6 1 2 3 4 5 15 16
GP1
CLOCK Tdly3
GP0 1 1 0 0 X X strt_bit stp_bit
DATA LSb MSb
Tdly1

input output input

2.3.1.4 Read Data From Program Memory

After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently accessed, starting with the
second rising edge of the clock input. The DATA pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (hi-impedance) after the
16th rising edge.
If the program memory is code protected (CP = 0), the
data is read as zeros.

FIGURE 2-6: READ DATA FROM PROGRAM MEMORY COMMAND

Tdly2

1 2 3 4 5 6 1 2 3 4 5 15 16
GP1
CLOCK Tdly3
GP0 1 0 0 1 0 X X strt_bit stp_bit
DATA LSb MSb
Tset1 Tdly1

Thld1

input output input

 2003 Microchip Technology Inc. Preliminary DS41173C-page 5

PIC12F629/675
2.3.1.5 Read Data From Data Memory
After receiving this command, the chip will transmit
data bits out of the data memory starting with the
second rising edge of the clock input. The DATA pin will
go into Output mode on the second rising edge, and it
will revert to Input mode (hi-impedance) after the 16th
rising edge. As previously stated, the data memory is
8-bits wide, and therefore, only the first 8 bits that are
output are actual data. If the data memory is code
protected, the data is read as all zeros. A timing
diagram of this command is shown in Figure 2-7.

FIGURE 2-7: READ DATA FROM DATA MEMORY COMMAND

Tdly2

1 2 3 4 5 6 1 2 3 4 5 15 16
GP1
CLOCK Tdly3
GP0 1 0 1 0 X X strt_bit stp_bit
DATA LSb MSb
Tset1 Tdly1
Thld1

input output input

2.3.1.6 Increment Address

The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 2-8.
It is not possible to decrement the address counter. To
reset this counter, the user should exit and re-enter
Programming mode.

FIGURE 2-8: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

Tdly2
Next Command
1 2 3 4 5 6 1 2

GP1
CLOCK

0 1 1 0 X X X 0
GP0
DATA Tset1 Tdly1
Thld1

DS41173C-page 6 Preliminary  2003 Microchip Technology Inc.

 PIC12F629/675
2.3.1.7 Begin Programming (Internally
Timed)
A Load command must be given before every Begin
Programming command. Programming of the appropri-
ate memory (user program memory or data memory)
will begin after this command is received and decoded.
An internal timing mechanism executes a write. The
user must allow for program cycle time for program-
ming to complete. No End Programming command is
required.
When programming data memory, the byte being
addressed is erased before being programmed.

FIGURE 2-9: BEGIN PROGRAMMING COMMAND (INTERNALLY TIMED)

Tprog1
Next Command
1 2 3 4 5 6 1 2
GP1
CLOCK

GP0 0 0 0 1 0 0 X 0
DATA
Tset1 Tdly1
Thld1

Program/Verify Test Mode

 2003 Microchip Technology Inc. Preliminary DS41173C-page 7

PIC12F629/675
2.3.1.8 Begin Programming (Externally
Timed)
A Load command must be given before every Begin
Programming command. Programming of the appropri-
ate memory (user program memory or data memory)
will begin after this command is received and decoded.
Programming requires (tprog2) time and is terminated
using an End Programming command. This command
programs the current location, no erase is performed.

FIGURE 2-10: END PROGRAMMING (SERIAL PROGRAM/VERIFY)

VIHH
MCLR
Next Command
1 2 3 4 5 6 1 2
ICSPCLK

ICSPDAT
0 1 0 1 0 0 X 0
tdly1
tset1
1 µs min.
thld1
}

100 ns min.

RESET Program/Verify Test Mode

DS41173C-page 8 Preliminary  2003 Microchip Technology Inc.

 PIC12F629/675
2.3.1.9 Bulk Erase Program Memory To perform a bulk erase of the program memory, the
following sequence must be performed.
After this command is performed and calibration bits
are erased, the entire program memory is erased. If 1. Read OSCCAL 0x3FF.
data is code protected, data memory will also be 2. Read configuration word.
erased. 3. Do a Bulk Erase Program Memory command.
Note: The OSCCAL word and BG bits must be 4. Wait Tera to complete bulk erase.
read prior to erasing the device and If the address is pointing to the ID/configuration
restored during the programming program memory (0x2000 - 0x200F), then both the
operation. OSCCAL is at location 0x3FF user memory and the ID locations will be erased.
and the BG bits are bits 12 and 13 of the
configuration word (0x2007).

FIGURE 2-11: BULK ERASE PROGRAM MEMORY COMMAND

Tera
Next Command
1 2 3 4 5 6 1 2
GP1
CLOCK

GP0 1 0 0 1 X X X 0
DATA
Tset1 Tset1 Tdly1

Thld1 Thld1

Program/Verify Test Mode

 2003 Microchip Technology Inc. Preliminary DS41173C-page 9

PIC12F629/675
2.3.1.10 Bulk Erase Data Memory
To perform a bulk erase of the data memory, the
Note: All bulk erase operations must take place
following sequence must be performed.
at 4.5V to 5.5V VDD range for PIC12F629/
1. Do a Bulk Erase Data Memory command. 675 devices and 2.0V to 5.5V VDD for
2. Wait Tera to complete bulk erase. PIC12F675-ICD device.
Data memory won’t erase if code protected (CPD = 0).

FIGURE 2-12: BULK ERASE DATA MEMORY COMMAND

Tera
Next Command
1 2 3 4 5 6 1 2
GP1
CLOCK

GP0 1 1 0 1 X X X 0
DATA
Tset1 Tdly1
Thld1

Program/Verify Test Mode

DS41173C-page 10 Preliminary  2003 Microchip Technology Inc.

 PIC12F629/675
FIGURE 2-13: PROGRAM FLOW CHART - PIC12F629 PROGRAM MEMORY

Start

Read and Save

OSCCAL value

Read and Save

Bandgap Cal.
Value

Bulk Erase
Device
PROGRAM CYCLE

Load Data
Program Cycle
for
Program Memory

Read Data
from Begin Begin
Program Memory Programming Programming
Command Command
(Internally timed) (Externally timed)
Report
No
Data Correct? Programming
Failure

Yes Wait Tprog1 Wait Tprog2

Increment
No All Locations
Address
Done?
Command End
Programming

Program
OSCCAL

Program Data
Memory
(if required)

Verify all
Locations

No Report Verify
Data Correct? Error

Yes
Program
Bandgap Cal.
and Config bits

Done

 2003 Microchip Technology Inc. Preliminary DS41173C-page 11

PIC12F629/675
FIGURE 2-14: PROGRAM FLOW CHART - PIC12F629 CONFIGURATION MEMORY

Start

Load
Configuration
Data

Program Cycle

Read Data
Command

No Report
Data Correct? Programming
Failure

Yes
Increment
Address
Command

Increment
No Address = Yes
Address
0x2004?
Command

Increment
Address
Command

Increment
Address
Command

Set Bits 12 and

13 to Saved
Bandgap Bits

Program
Cycle
(config. word)

Read Data
Command

Report
No
Data Correct? Programming
Failure

Yes

Done

DS41173C-page 12 Preliminary  2003 Microchip Technology Inc.

 PIC12F629/675
FIGURE 2-15: PROGRAM FLOW CHART - PIC12F629 DATA MEMORY

Start

PROGRAM CYCLE

Load Data
Program Cycle for
Program Memory

Read Data Begin Begin

from Programming Programming
Data Memory Command Command
(Internally timed) (Externally timed)

Report
No
Data Correct? Programming Wait Tprog1 Wait Tprog2
Failure

Yes
End
Increment No Programming
All Locations
Address
Done?
Command

Yes

Done

 2003 Microchip Technology Inc. Preliminary DS41173C-page 13

PIC12F629/675
FIGURE 2-16: PROGRAM FLOW CHART - ERASE FLASH DEVICE

Start

Read and Save

OSCCAL Value

Read and Save

Band Gap Cal
Value

Bulk Erase Device

Program
OSCCAL

Program
Band Gap Cal
Bits

Done

DS41173C-page 14 Preliminary  2003 Microchip Technology Inc.

 PIC12F629/675
3.0 CONFIGURATION WORD
The PIC12F629/675 has several configuration bits.
These bits can be programmed (reads ‘0’), or left
unchanged (reads ‘1’), to select various device
configurations.

REGISTER 3-1: CONFIGURATION WORD OR PIC12F629/675 DEVICE

R/P-1 R/P-1 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
BG1 BG0 — — — CPD CP BODEN MCLRE PWRTE WDTE FOSC2 F0SC1 F0SC0
bit 13 bit 0

bit 13-12: BG<1:0>: Bandgap Calibration bits(2)

00 = Lowest Bandgap voltage
...
11 = Highest Bandgap voltage
bit 11-9: Unimplemented: Read as ‘0’
bit 8: CPD: Code Protection Data
1 = Data memory is not protected
0 = Data memory is external read protected
bit 7: CP: Code Protection
1 = Program memory is not code protected
0 = Program memory is code protected
bit 6: BODEN: Brown-out Detect Reset Enable bit(1)
1 = BOD Reset enabled
0 = BOD Reset disabled
bit 5: MCLRE: MCLR Pin Function Select
1 = MCLR pin is MCLR function
0 = MCLR pin is alternate function, MCLR function is internally disabled.
bit 4: PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 3: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0: FOSC<2:0>: Oscillator Selection bits
000 = LP oscillator: Low power crystal on GP5/T1CKI/OSC1/CLKIN and GP4/T1G/OSC2/CLKOUT
001 = XT oscillator: Crystal/resonator on GP5/T1CKI/OSC1/CLKIN and GP4/T1G/OSC2/CLKOUT
010 = HS oscillator: High speed crystal/resonator on GP5/T1CKI/OSC1/CLKIN and GP4/T1G/OSC2/CLKOUT
011 = EC: I/O function on GP4/T1G/OSC2/CLKOUT, CLKIN on GP5/T1CKI/OSC1/CLKIN
100 = INTOSC oscillator: I/O function on GP4/T1G/OSC2/CLKOUT, I/O function on GP5/T1CKI/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on GP4/T1G/OSC2/CLKOUT, I/O function on GP5/T1CKI/OSC1/CLKIN
110 = RC oscillator: I/O function on GP4/T1G/OSC2/CLKOUT, RC on GP5/T1CKI/OSC1/CLKIN
111 = RC oscillator: CLKOUT function on GP4/T1G/OSC2/CLKOUT, RC on GP5/T1CKI/OSC1/CLKIN
Note 1: Enabling Brown-out Detect Reset Enable does not automatically enable the Power-up Timer Enable (PWRTE).
2: The Bandgap Calibration bits must be read, preserved, then replaced by the user during any bulk erase operation.

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

3.1 Device ID Word

The device ID word for the PIC12F629/675 is located
at 2006h.

TABLE 3-1: DEVICE ID VALUES

Device ID Value
Device
Dev Rev
PIC16F629 00 1111 100 x xxxx
PIC16F675 00 1111 110 x xxxx

 2003 Microchip Technology Inc. Preliminary DS41173C-page 15

PIC12F629/675
4.0 CODE PROTECTION To disable code protect:
a) Read and store OSCCAL and BG bits.
For PIC12F629/675 devices, once code protection is
enabled, all program memory locations, except 0X3FF, b) Execute Load Configuration (000000).
read all 0’s. The ID locations and the configuration c) Execute Bulk Erase Program Memory
word read out in an unprotected fashion. Further (001001).
programming is disabled for the entire program d) Wait Tera.
memory. Data memory is protected with its own code e) Execute Bulk Erase Data Memory (001011).
protect bit (CPD). It is possible to program the ID
f) Wait Tera.
locations and the configuration word.
g) Reset device to RESET address counter before
4.1 Disabling Code Protection re-programming device.
h) Restore OSCCAL and BG bits.
It is recommended that the following procedure be
performed before any other programming is attempted.
It is also possible to turn code protection off (data Note: To ensure system security, if CPD bit = 0,
protect bit = 1) using this procedure. However, all data step c) will also erase data memory.
within the program memory and the data memory will
be erased when this procedure is executed, and thus,
the security of the data or code is not compromised.

4.2 Embedding Configuration Word and ID Information in the HEX File

To allow portability of code, the programmer is required to read the configuration word and ID locations from the HEX
file when loading the HEX file. If configuration word information was not present in the HEX file, then a simple warning
message may be issued. Similarly, while saving a HEX file, configuration word and ID information must be included.
An option to not include this information may be provided.
Specifically for the PIC12F629/675, the EEPROM data memory should also be embedded in the HEX file (see
Section 4.3.2).
Microchip Technology Incorporated feels strongly that this feature is important for the benefit of the end customer.

DS41173C-page 16 Preliminary  2003 Microchip Technology Inc.

 PIC12F629/675
4.3 Checksum Computation The following table describes how to calculate the
checksum for each device.
4.3.1 CHECKSUM
Note 1: The checksum calculation differs depend-
Checksum is calculated by reading the contents of the ing on the code protect setting. Since the
PIC12F629/675 memory locations and adding up the program memory locations read out differ-
op codes to the maximum user addressable location, ently depending on the code protect set-
(e.g., 0x3FF for the PIC12F629/675). Any carry bits ting, the table describes how to
exceeding 16 bits are neglected. Finally, the configura- manipulate the actual program memory
tion word (appropriately masked) is added to the values to simulate the values that would
checksum. Checksum computation for each member of be read from a protected device. When
the PIC12F629/675 devices is shown in Table 4-1. calculating a checksum by reading a
device, the entire program memory can
The checksum is calculated by summing the following:
simply be read and summed. The
• The contents of all program memory locations configuration word and ID locations can
• The configuration word, appropriately masked always be read
• Masked ID locations (when applicable) 2: Some older devices have an additional
The Least Significant 16 bits of this sum is the value added in the checksum. This is to
checksum. maintain compatibility with older device
programmer checksums.

TABLE 4-1: CHECKSUM COMPUTATION

Blank 0x25E6 at 0 and
Device Code Protect Checksum*
Value Max Address
PIC12F629/675 OFF SUM[0x0000:0x3FE] + CFGW & 01FF BE00 89CE
ALL CFGW & 0x01FF + SUM_ID BF7F 8B4D
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant
nybble.
For example: ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND

4.3.2 EMBEDDING DATA EEPROM

CONTENTS IN HEX FILE
The programmer should be able to read data EEPROM
information from a HEX file and conversely (as an
option), write data EEPROM contents to a HEX file
along with program memory information and fuse
information.
The 128 data memory locations are logically mapped
starting at address 0x2100. The format for data
memory storage is one data byte per address location,
LSb aligned.

 2003 Microchip Technology Inc. Preliminary DS41173C-page 17

PIC12F629/675
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS

TABLE 5-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY

MODE
Standard Operating Conditions (unless otherwise stated)
AC/DC Characteristics Operating Temperature -40°C ≤ TA ≤ +85°C
Operating Voltage 4.5V ≤ VDD ≤ 5.5V
Sym Characteristics Min Typ Max Units Conditions/Comments
General
VDD level for word operations, 2.0 5.5 V PIC12F675-ICD
VDD
program memory 4.5 5.5 V PIC12F629/675
VDD level for word operations, data
VDD 4.5 5.5 V
memory
VDD level for bulk erase/write
VDD 4.5 5.5 V
operations, program and data memory
High voltage on MCLR for
VIHH VDD + 3.5 13.5 V
Programming mode entry
MCLR rise time (VSS to VHH) for
TVHHR 1.0 µs
Programming mode entry
TPPDP Hold time after VPP↑ 5 µs
VIH1 (CLOCK, DATA) input high level 0.8 VDD V
VIL1 (CLOCK, DATA) input low level 0.2 VDD V
CLOCK, DATA setup time before
TSET0 MCLR↑ (Programming mode selection 100 ns
pattern setup time)
CLOCK, DATA hold time after MCLR↑
THLD0 (Programming mode selection pattern 5 µs
setup time)
Serial Program/Verify
TSET1 Data in setup time before clock↓ 100 ns
THLD1 Data in hold time after clock↓ 100 ns
Data input not driven to next clock
TDLY1 input (delay required between com- 1.0 µs
mand/data or command/command)
Delay between clock↓ to clock↑ of
TDLY2 1.0 µs
next command or data
Clock↑ to data out valid (during READ
TDLY3 80 ns
DATA)
TERA Erase cycle time 4 8 ms
Programming cycle time (internally 5 6 Data Memory
TPROG1 ms
timed) 2 2.5 Program Memory
Programming cycle time (externally 10°C ≤ TA ≤ +40°C
TPROG2 2 2 ms
timed) Program Memory
Time delay from program to compare
TDIS 0.5 µs
(HV discharge time)

DS41173C-page 18 Preliminary  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, KEELOQ,
ensure that your application meets with your specifications. No MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
representation or warranty is given and no liability is assumed by PowerSmart are registered trademarks of Microchip Technology
Microchip Technology Incorporated with respect to the accuracy Incorporated in the U.S.A. and other countries.
or use of such information, or infringement of patents or other
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
intellectual property rights arising from such use or otherwise.
and The Embedded Control Solutions Company are registered
Use of Microchip’s products as critical components in life
trademarks of Microchip Technology Incorporated in the U.S.A.
support systems is not authorized except with express written
approval by Microchip. No licenses are conveyed, implicitly or Accuron, Application Maestro, dsPIC, dsPICDEM,
otherwise, under any intellectual property rights.
dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM,
fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal,
PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark of

Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

© 2003, Microchip Technology Incorporated, Printed in the

U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.

 2003 Microchip Technology Inc. Preliminary DS41173C - page 19

 WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC Japan
Microchip Technology Japan K.K.
Corporate Office Australia
Benex S-1 6F
2355 West Chandler Blvd. Microchip Technology Australia Pty Ltd
3-18-20, Shinyokohama
Chandler, AZ 85224-6199 Marketing Support Division
Kohoku-Ku, Yokohama-shi
Tel: 480-792-7200 Fax: 480-792-7277 Suite 22, 41 Rawson Street
Kanagawa, 222-0033, Japan
Technical Support: 480-792-7627 Epping 2121, NSW
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Web Address: http://www.microchip.com Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Korea
Atlanta Microchip Technology Korea
3780 Mansell Road, Suite 130 China - Beijing
168-1, Youngbo Bldg. 3 Floor
Alpharetta, GA 30022 Microchip Technology Consulting (Shanghai)
Samsung-Dong, Kangnam-Ku
Tel: 770-640-0034 Fax: 770-640-0307 Co., Ltd., Beijing Liaison Office
Seoul, Korea 135-882
Unit 915
Boston Tel: 82-2-554-7200 Fax: 82-2-558-5934
Bei Hai Wan Tai Bldg.
2 Lan Drive, Suite 120 No. 6 Chaoyangmen Beidajie Singapore
Westford, MA 01886 Beijing, 100027, No. China Microchip Technology Singapore Pte Ltd.
Tel: 978-692-3848 Fax: 978-692-3821 Tel: 86-10-85282100 Fax: 86-10-85282104 200 Middle Road
#07-02 Prime Centre
Chicago China - Chengdu
Singapore, 188980
333 Pierce Road, Suite 180 Microchip Technology Consulting (Shanghai) Tel: 65-6334-8870 Fax: 65-6334-8850
Itasca, IL 60143 Co., Ltd., Chengdu Liaison Office
Tel: 630-285-0071 Fax: 630-285-0075 Rm. 2401-2402, 24th Floor, Taiwan
Ming Xing Financial Tower Microchip Technology (Barbados) Inc.,
Dallas Taiwan Branch
4570 Westgrove Drive, Suite 160 No. 88 TIDU Street
Chengdu 610016, China 11F-3, No. 207
Addison, TX 75001 Tung Hua North Road
Tel: 972-818-7423 Fax: 972-818-2924 Tel: 86-28-86766200 Fax: 86-28-86766599
Taipei, 105, Taiwan
China - Fuzhou Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Detroit
Microchip Technology Consulting (Shanghai)
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Co., Ltd., Fuzhou Liaison Office EUROPE
Unit 28F, World Trade Plaza
Farmington Hills, MI 48334 Austria
No. 71 Wusi Road
Tel: 248-538-2250 Fax: 248-538-2260 Microchip Technology Austria GmbH
Fuzhou 350001, China
Kokomo Tel: 86-591-7503506 Fax: 86-591-7503521 Durisolstrasse 2
2767 S. Albright Road A-4600 Wels
China - Hong Kong SAR Austria
Kokomo, Indiana 46902 Microchip Technology Hongkong Ltd.
Tel: 765-864-8360 Fax: 765-864-8387 Tel: 43-7242-2244-399
Unit 901-6, Tower 2, Metroplaza Fax: 43-7242-2244-393
Los Angeles 223 Hing Fong Road Denmark
18201 Von Karman, Suite 1090 Kwai Fong, N.T., Hong Kong Microchip Technology Nordic ApS
Irvine, CA 92612 Tel: 852-2401-1200 Fax: 852-2401-3431 Regus Business Centre
Tel: 949-263-1888 Fax: 949-263-1338 China - Shanghai Lautrup hoj 1-3
Microchip Technology Consulting (Shanghai) Ballerup DK-2750 Denmark
Phoenix
Co., Ltd. Tel: 45 4420 9895 Fax: 45 4420 9910
2355 West Chandler Blvd.
Room 701, Bldg. B France
Chandler, AZ 85224-6199
Far East International Plaza Microchip Technology SARL
Tel: 480-792-7966 Fax: 480-792-4338
No. 317 Xian Xia Road Parc d’Activite du Moulin de Massy
San Jose Shanghai, 200051 43 Rue du Saule Trapu
Microchip Technology Inc. Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Batiment A - ler Etage
2107 North First Street, Suite 590 China - Shenzhen 91300 Massy, France
San Jose, CA 95131 Microchip Technology Consulting (Shanghai) Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Tel: 408-436-7950 Fax: 408-436-7955 Co., Ltd., Shenzhen Liaison Office Germany
Toronto Rm. 1812, 18/F, Building A, United Plaza Microchip Technology GmbH
6285 Northam Drive, Suite 108 No. 5022 Binhe Road, Futian District Steinheilstrasse 10
Mississauga, Ontario L4V 1X5, Canada Shenzhen 518033, China D-85737 Ismaning, Germany
Tel: 905-673-0699 Fax: 905-673-6509 Tel: 86-755-82901380 Fax: 86-755-82966626 Tel: 49-89-627-144-0
China - Qingdao Fax: 49-89-627-144-44
Rm. B505A, Fullhope Plaza, Italy
No. 12 Hong Kong Central Rd. Microchip Technology SRL
Qingdao 266071, China Via Quasimodo, 12
Tel: 86-532-5027355 Fax: 86-532-5027205 20025 Legnano (MI)
India Milan, Italy
Microchip Technology Inc. Tel: 39-0331-742611 Fax: 39-0331-466781
India Liaison Office United Kingdom
Marketing Support Division Microchip Ltd.
Divyasree Chambers 505 Eskdale Road
1 Floor, Wing A (A3/A4) Winnersh Triangle
No. 11, O’Shaugnessey Road Wokingham
Bangalore, 560 025, India Berkshire, England RG41 5TU
Tel: 91-80-2290061 Fax: 91-80-2290062 Tel: 44 118 921 5869 Fax: 44-118 921-5820

03/25/03

DS41173C-page 20 Preliminary  2003 Microchip Technology Inc.