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DEPARTMENT OF ELECTRICAL AND COMPUTER

ENGINEERING

DIGITAL LOGIC DESIGN – EEE241

LAB#02: Boolean Function Implementation
using Universal Gates

NAME RAYAN ALI SAJID

REGISTRATION NUMBER FA24-EEE-041

SECTION EEE-2 NULL A

INTRUCTOR Dr. AHMED NASEEM ALVI

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OBJECTIVES:

The chief objective is to construct various logic gates using NAND gates and NOR
gates to determine their universality.

INTRODUCTION:

The logic gates perform the basic Boolean functions like AND, OR, NAND, NOR,
Inversion, XOR and XNOR. Digital circuits are more frequently constructed with NAND or
NOR gates than with AND and OR gates. NAND and NOR gates are easier to fabricate with
electronic components and are the basic gates used in all IC digital logic families.
Because of the prominence of NAND and NOR gates in the design of digital circuits,
rules and procedures have been developed for conversion from Boolean function given in
terms of AND, OR, and NOT into equivalent NAND and NOR logic diagram.

LAB TASKS:

(Part A)

Task 1:

Verification of AND gate:

Inputs
Outputs
A B
0 0 1
0 1 1
1 0 1
1 1 0

Task 2:
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Verification of OR gate:

Inputs
Outputs
A B
0 0 0
0 1 1
1 0 1
1 1 1

Task 3:

Verification of NOT gate:

Input
A output

0 1
1 0
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(Part B)
Task 1:

Verification of AND gate:

Inputs
Outputs
A B
0 0 1
0 1 0
1 0 0
1 1 1

Task 2:

Verification of OR gate:
Task 3:

Verification of NOT gate:

Inputs
Outputs
A B
0 0 1
0 1 0
1 0 0
1 1 0
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Input
A output

0 1
1 0

CONCLUSION:

AND, NOT and OR gates are the basic gates; we can create any logic gate or any
Boolean expression by combining a concoction of these gates. NOR gates and NAND gates
have the actual property that any one of them can generate any logical Boolean expression if
aptly designed. While executing AND gate using NAND gates, the AND gate is replaced by
a NAND gate with its output complemented by a NAND gate inverter. And while
implementing OR gate using only NAND gate, the OR gate is replaced by a NAND gate with
all its inputs accompanied by NAND gate inverters.
POST LAB

1- Design NOR, XOR and XNOR gate Using NAND gate only.

NOR gate:
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Inputs
Outputs
A B
0 0 1
0 1 0
1 0 0
1 1 0

XOR gate:
Inputs
Outputs
A B
0 0 0
0 1 1
1 0 1
1 1 0
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XNOR gate:

Inputs
Outputs
A B
0 0 1
0 1 1
1 0 1
1 1 0

2- Design NAND, XOR and XNOR gate Using NOR gate only.

NAND gate: Inputs

Outputs
A B
0 0 1
0 1 0
1 0 0
1 1 0
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XOR gate:
Inputs
Outputs
A B
0 0 0
0 1 1
1 0 1
1 1 1

XNOR gate:

Inputs
Outputs
A B
0 0 1
0 1 0
1 0 0
1 1 1
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LAB ASSESSMENT

Pre-Lab /1

In-Lab /5

Data
Analysis
/4
/10
/4
Data /4
Post-Lab Presentation

Writing /4
Style

Instructor Signature and Comments