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 20CS301 DIGITAL
PRINCIPLES AND SYSTEM
DESIGN
Department: COMPUTER SCIENCE AND ENGINEERING
Batch/Year: BATCH 2020-24/II
Created by:
Dr. S.Selvi , Professor, CSE, RMKEC
Ms K. Elavarasi , AP, CSE, RMKEC

Date: 5th October 2021

Syllabus

UNIT IV
Analysis and Design of Asynchronous Sequential Circuits
– Reduction of State and Flow Tables – Race-free State
Assignment – Hazards.
Lecture Plan – Unit 4 -
ASYNCHRONOUS SEQUENTIAL LOGIC

Sl. Topic Number Propos Actual CO Taxo Mode

No of Periods ed Lecture nomy of
. Date Date Level Deliver
y
1 Analysis and 2 09.10.2 CO4 K4 PPT /
Design of 1 Online
Asynchrono Lecture
us
Sequential
Circuits
2 Design of 2 12.10.2 CO4 K4 PPT /
Asynchrono 1 Online
us Lecture
Sequential
Circuits
3 Reduction of 2 16.10.2 CO4 K4 PPT /
State and 1 Online
Flow Tables Lecture

4 Race-free 2 20.10.2 CO4 K4 PPT /

State 1 Online
Assignment Lecture

5 Hazards 2 21.10.2 CO4 K3 PPT /

1 Online
Lecture
Activity Based Learning
Sl. No. Contents Page No.

1 Flash Cards 38

2 Implication Table 47

3 Quiz 99
Lecture Notes – Unit IV
UNIT IV ASYNCHRONOUS SEQUENTIAL LOGIC

Sl. No. Contents Page No.

Asynchronous Sequential Circuits
1 12
Analysis of Asynchronous Sequential Circuits
2 14
Analysis of SR Latch
3 18
Transition table; Flow Table; Primitive Flow Table
4 12
Race Condition – Critical and Non-critical race condition
5 29
Procedure for analyzing an asynchronous sequential
6 33
circuit with SR Latch
Key Debounce circuit
7 35
Implementing a circuit with SR Latch
8 37
Design of Asynchronous sequential circuit - Procedure
9 41

State reduction using Implication Table - Completely

10 46
specified and Incompletely specified State Table
Race Free State Assignment
11 54
Assigning values to output variables
12 57
Design of Asynchronous sequential circuit – complete
13 59
examples
Hazards ; types
Hazards in combinational circuit
14 85
Hazards in sequential circuits
Problems on Hazard elimination
 Unit - IV

ASYNCHRONOUS SEQUENTIAL CIRCUITS

• Asynchronous sequential circuits do not use clock pulses.
• The change of internal state occurs when there is a change in the
input variables.
• The memory elements in asynchronous sequential circuits are either
un clocked flip-flops or time delay circuits.
• An asynchronous sequential circuit resembles a combinational circuit
with feedback.
• Since no clock pulse is used, the state of the system is allowed to
change immediately after the input changes.
Uses:
When speed of operation is important, especially in those cases where
the digital system must respond quickly without waiting for a clock
pulse.

Block Diagram of an Asynchronous Sequential Circuit

 Unit - IV

• It consists of a combinational circuit and delay elements connected to form

feedback loops.
• There are ‘n’ input variables, ‘m’ output variables and ‘R” internal states.
• The delay elements provide short term memory for the sequential circuit.
• The present state and next state variables in asynchronous sequential circuits are
called secondary variables and excitation variables respectively.
• When an input variable changes in value, the Y secondary variables do not
change instantly.
• It takes certain time for the signal to propagate from the input terminals through
the combinational circuit, to the Y excitation variables, which generate new values
for the next state.
• These values propagate through the delay elements and become the new present
state for the secondary variables.
• In the steady state condition, the secondary variables and excitation variables are
the same, but during transition they are not.
yi = Yi for i=1,2,…. R - Steady State
• Otherwise, the circuit is in a continuous transition and is said to be unstable.
• A transition from one stable to another occurs only in response to a change in an
input variable.
• To ensure proper operation:
• Asynchronous sequential circuits must be allowed to attain a stable state before
the input is changed to a new value.
• Because of the delays in the wires and the gate circuits, it is impossible to have
two or more input variables change at exactly the same instant of time without an
uncertainty as to which one changes first.
• Simultaneously change of two or more varaibles is prohibited. Only one input
variables can change at any one time and the time between two input changes
must be no longer than the time it takes, the circuit to reach a stable state.
• Fundamental mode that assumes that the input signals change one at time and
only when the circuit is in stable operation.
Steady State Condition
• Current states and next states are the same.
• Difference between Y and y will cause a transition.
 Unit - IV

Fundamental Mode
• The input signals change one at a time and only when the circuit is in a stable
condition.
Pulse Mode
• The input and output are represented by pulses.
• Only one input is allowed to have pulse present at any time.
• The width of the pulse is long enough for the circuit to respond to the input and
• It must not be so long that it is still present after the new state is reached.

Analysis of Asynchronous Sequential Circuit

Procedure for obtaining a transition table from the circuit of an asynchronous
sequential circuit.
i) Determine all feedback loops in the circuit.
ii) Designate the output of each feedback loop with variable Yi and its
corresponding input with yi for i=1,2,…k, where k is the number of feedback
loops in the circuit.
iii) Derive the Boolean functions of all Y’s as a function of the external inputs and
the y’s.
iv) Plot each Y function in a map using the y variables for the rows an external
inputs for the columns (state table)
v) Combine all the maps to a transition table showing the value of Y = Y1,Y2…YK
inside the each square.
vi) Circle those values of Y in each square that are equal to the value of y =
y1,y2,..yk in the same row.
Once the transition table is available, the behavior of the circuit can be analyzed by
observing the state transition as a function of changes in the input variables.
 Unit - IV

i) Analyze the given asynchronous sequential circuit.

Analysis:
Input variable = x
Present state/Secondary variables = y1,y2
Excitation variables/Next State = Y1, Y2
Secondary variables => Inputs
Excitation variables => Outputs
Boolean expressions are expressed as a function of the input and secondary
variables.
Y1 = y1x + x’y2
Y2 = xy1’ + x’y2

Present State Next State Stable State

y1 y2 Input Y1 Y2 Yes/No
(x)
0 0 0 0 0 Yes
0 0 1 0 1 No
0 1 0 1 1 No
0 1 1 0 1 Yes
1 0 0 0 0 No
1 0 1 1 0 Yes
1 1 0 1 1 Yes
1 1 1 1 0 No

If y1y2 = Y1Y2, the state is said to be stable

 Unit - IV

Transition Table: Shows the values Y = Y1Y2 inside each square.

The encoded binary values of the y variables are labelled in the rows and the input x
variable is used to designate the columns.

Behavior of the circuit:

• The square x = 0 and y=00 in the transition table shows that Y =00, since Y
represents the next value of y this is a stable condition.
• If x changes from 0 to 1, while y1y2 = 00, the circuit changes the value of Y to
01. This represents a temporary unstable state, because Y is not equal to the
present value of y.
• Next as the signal propagates to make Y=01, the feedback path in the circuit
causes a change in y to 01. Now that the y = Y, with an input of x =1 , is the
stable state.
• The circuit repeats the sequence of states.
000 -> 0001 -> 0010 -> 0011 -> 0100
The internal state with input value together is called the total state of the circuit.
In an asynchronous transition table, there usually is at least one next-state entry
that is the same as the present state value in each row. Otherwise, all the total
states in that row will be unstable.
Flow Table
Flow Table is similar to transition table, but the states are referred by letter symbols
without making specific reference to their binary values.
 Unit - IV

Flow Table
• Flow Table is similar to transition table, but the states are referred by letter
symbols without making specific reference to their binary values

b) Two states with two Input

and one output
a) Four states with one Input

• Flow Table (a) is called a primitive flow table because it has only one stable state
in each row.
.
• Flow Table (b) has more than one stable states in each row.
Behavior of the Circuit (From flow table (b))
• If x1 =0, the circuit is in state a.
• If x1 goes to 1, while x2 is 0, the circuit goes to state b.
• With input x1x2 = 11, the circuit may be either in state ‘a’ or state ‘b’.
• If it is in state ‘a’, the output is 0 and if it is in state b, the output is 1.
 Unit - IV

ANALYZE THE SR LATCH WITH NOR GATES

Truth Table
Cross-coupled circuit

Redraw the circuit to see the feedback path from the output of gate 1
to the input of gate 2.

I/O equations = (S+y)’+R = (S+y). R’ = SR’ + yR’

State Table
Present Input Next Stable State
State State

y S R Y Yes/No
0 0 0 0 Yes
0 0 1 0 Yes
0 1 1 0 Yes
0 1 0 1 No
1 0 0 1 Yes
1 0 1 0 No
1 1 1 0 No
1 1 0 1 Yes
 Unit - IV

Transition Table

Behavior of the SR Latch

• The state with SR = 10 is a stable state because Y = y+1; the output Q=Y=1
and the latch is said to be set.
• The state with SR = 01 is a stable state because Y = y-0; the output Q=Y=0 and
the latch is said to be reset.
• A change of R back to 0 leaves the circuit in the reset state.
• Going from SR=11 to SR=00 produces an unpredictable result.
• If S goes to ‘0’ first, the output remains at 0
11 -> 01 -> 00
0 -> 0 -> 0
• If R goes to ‘0’ first, the output goes to 1.
11 -> 10 -> 00
0 -> 1 -> 1
 Unit - IV

ANALYZE THE SR LATCH WITH NAND GATES

Redraw the circuit to see the feedback path from the output of gate 1
to the input of gate 2.

I/O equations = ((Ry)’.S)’ = R’’.y’’+S’ = Ry+S’

Present Input Next Stable State

State State

y S R Y Yes/No
0 0 0 1 No
0 0 1 1 No
0 1 1 0 Yes
0 1 0 0 Yes
1 0 0 1 Yes
1 0 1 1 Yes
1 1 1 1 Yes
1 1 0 0 No
 Unit - IV

Transition Table

Behavior of the SR Latch

The NAND latch operates with both inputs normally at 1 unless the state of the latch
has to be changed.
The application of 0 to R causes the output Q to go to 0 , thus putting the latch in
the reset state.
After the R returns to 1, a change of S to 0 causes a change to the set state.
The condition to be avoided here is that both S and R not be 0 simultaneously. This
condition is satisfied when S’R’ =0 . The Excitation function for the circuit is

Comparing it with the excitation function of the NOR latch . S has been replaced
with S’ and R with R’.
Hence the input variables for the NAND latch require the complemented values of
those used in the NOR latch.
For this reason, the NAND latch is referred to as an S’R’ latch.

Activity

Flash Cards

Link: http://quizlet.com/_8l9o3j?x=1qqt&i=2zp4cc
 4. TRANSITION TABLE

Transition table is useful to analyze an asynchronous circuit from an circuit

diagram.

For example, consider the following circuit

Fig. 4.1 Example of a Asynchronous Sequential Circuit

The circuit consists of one input variable (x) and two internal states.

The internal states have two excitation variables(Y1 and Y2) and two secondary
variables (y1 and y2). Y1 and Y2 represents Next state and y1 and y2 represents
present state of the circuit.

Each logic gate in the path introduces a propagation delay of about 2 to 10

nanoseconds.

The delay associated with each feedback loop is obtained from the propagation
delay between each y input and its corresponding Y output.

Thus, no additional external delay elements are necessary when the

combinational circuit and the wires in the feedback path provide sufficient delay.

STEPS TO OBTAIN A TRANSITION TABLE

Step 1: Obtain Boolean expression for the excitation variables

Considering the excitation variables as outputs and the secondary variables as

inputs, the Boolean expressions for the excitation variables are obtained as
follows.
Y1 = x y1 + x’ y2
Y2 = x y1’ + x’ y2
 4. TRANSITION TABLE

Step 2: Plot the Boolean expressions for Excitation variables in the K map

Plot the Y1 and Y2 functions in the K map.

The encoded binary values of the y variables are used for labeling rows.

The input variable x, is used to designate the columns

x x

y1y2 0 1 y1y2 0 1

0 0 0 1
00 00

1 0 1 1
01 01

1 1 11 1 0
11

10 0 1 10 0 0

Fig 4.2. K map for Y1 = x y1 + x’ y2 Fig 4.3. K map for Y2 = x y1’ + x’ y2

This type of K map configuration is more convenient when dealing with

asynchronous sequential circuits.
Step 3: Obtain the Transition table from the K map

The transition table is obtained from the K map by combining the binary values in
the corresponding squares.

Each square of the Transition table shows the value of Y=Y1Y2 (i.e.)

The first bit of Y is obtained from the value of Y1 and the second bit is obtained
from the value of Y2 in the same square position.

Stable state: A state is said to be a stable state if the value of Y1Y2 is same
as that of y1y2. Y1, Y2 represents the next state of y1, y2

Those entries in the transition table are circled to indicate stable condition

Other uncircled entries represents an unstable state.

 4. TRANSITION TABLE
x
y1y2 0 1
00 01
00
11 01
01

11 11 10

10 00 10

Fig 4.4 Transition table corresponding to Fig 4.2 and 4.3

In an asynchronous sequential circuit, the internal state can change immediately

after a change in the input. So, it is convenient to combine the internal state with
the input and represent it as total state of the circuit.

The above transition table, has four total stable states and four total unstable
states:

Total stable states y1y2x = 000,011,110,101

Total unstable states y1y2x = 001,010,111,100

In general, if a change in the input takes the circuit to unstable state, the value of
‘y’ keeps changing until it reaches the stable state.

If we regard the secondary variables as present state and excitation variables as

next state, the transition table of asynchronous sequential circuit is similar to the
state table of synchronous sequential circuit.

Fig 4.5 State table for the circuit in Fig 4.1

 4. TRANSITION TABLE
Procedure to obtain Transition table
1. Determine all feedback loops in the circuit.

2. Designate the output of each feedback loop with variable Y, and its corresponding
input with Yi for i = 1,2, ... , k, where k is the number of feedback loops in the
circuit.

3. Derive the Boolean functions of all Y's as a function of the external inputs and the
y's.

4. Plot each Y function in a map, using the y variables for the rows and the x
variables for the columns.

5. Combine all the maps into one table showing the value of Y = Y1, Y2, ... Yk, inside
each square.

6. Circle those values of Y in each square that are equal to the value of y = y1 y2 ....
yk in the same row.

- The behaviour of the circuit can be analyzed by observing the state

transition as a function of changes in the input variables
 4. FLOW TABLE AND PRIMITIVE FLOW TABLE
During the design of asynchronous sequential circuits, it is more convenient to
name the states by letter symbols without making specific reference to their
binary values. Such a table is called a flow table.

A flow table is similar to a transition table except that the internal states are
symbolized with letters rather than binary numbers.

The flow table also includes the output values of the circuit for each stable state.

Example:

The flow table is obtained by designating the four states with letters such as
a,b,c,d and assigning binary values to the states ; a=00, b=01, c=11, d=10
x x
y1y2 0 1 y1y2 0 1
00 01 a b
00 a
11 01 c b
01 b
11 11 10 c d
c
10 00 10 d a d

Transition table for the circuit in Fig.4.1 Fig 4.5.Flow table for the circuit in Fig.4.1

PRIMITIVE FLOW TABLE

A primitive Flow table contains only one stable state in each row.
Example x
y1 y2 0 1 x1 x2
a b y 00 01 11 10
a a ,0 a ,0 a ,0 b,0
c b a
b
b a,0 a,0 b ,1 b ,0
c c d

d a d

Fig. 4.6 Flow table with 4 states and Fig. 4.7 Flow table with 2 states, 2 inputs

1 input and 1 output

 4. FLOW TABLE AND PRIMITIVE FLOW TABLE

The flow table in Fig 4.6 is a primitive flow table because, it has only one stable
state in each row.

Fig 4.7 shows a flow table with more than one stable state in the same row. It has
two states, a and b; two inputs, x1 and x2; one output, z. The binary value of the
output variable is indicated inside the square next to the state symbol and is
separated by a comma.

From the flow table, we observe the following behaviour of the circuit can be
observed.

Procedure to obtain circuits from Flow table

Let us consider the flow table in Fig. 4.7. The circuit can be obtained from the Flow
table as follows:

1. Assign distinct binary values to each state. We assign binary 0 to state ‘a’ and
binary 1 to state ‘b’. This converts the flow table into a transition table.
x1 x2
y 00 01 11 10
0 ,0 0 ,0 0 ,0 1,0
0 Next state

1 0,0 0,0 1 ,1 1 ,0 Output

2. Construct the maps to find the Boolean expressions for Next state and Output
x1 x2
x1 x2
y 00 01 11 10 y 00 01 11 10
0 0 0 1 0 0 0 0
0
0
1 0 0 1 1 1 0 0 1 0

Next state Expression Y = x1x2’ + x1y Output Expression z= x1x2y

 4. FLOW TABLE AND PRIMITIVE FLOW TABLE

3. Obtain the circuit from the maps

x1
x2
Y

y
Fig. 4.8 Derivation of a circuit specified by the flow table in Fig. 4.7

This approach have two difficulties: i) Binary state assignment and ii) Output
assigned to unused states.
 5. RACE CONDITION –
CRITICAL AND NON-CRITICAL RACE CONDITION

A race condition is said to exist in an asynchronous sequential circuit when two or

more binary state variables change value in response to a change in an input
variable.

When unequal delays are encountered, a race condition may cause the state
variables to change in an unpredictable manner.

For example, if the state variables must change from 00 to 11, the difference in
delays may cause

The first variable to change faster than the second, with the result that the
state variables change in sequence from 00 to 10 and then to 11.

00 -> 10 -> 11

If the second variable changes faster than the first, the state variables will
change from 00 to 01 and then to 11.

00 -> 01 -> 11

Thus, the order by which the state variables change may not be known in
advance.

If the final stable state that the circuit reaches does not depend on the order in
which the state variables change, the race is called as Noncritical race.

If it is possible to end up in two or more different stable states, depending on the

order in which the state variables change, then it is a Critical race.

Critical races must be avoided to ensure proper operation of the Asynchronous

Sequential Circuit.
 5. RACE CONDITION –
CRITICAL AND NON-CRITICAL RACE CONDITION
Examples of Noncritical races:

We start with the total stable state y1y2x = 000 and then change the input
from 0 to 1.

(1) x (2) x
y1y2 0 1 y1y2 0 1
00 11 00 11
00 00
11 01
01 01
11 01
11 11
11 11
10 10

(a) Possible Transitions (b) Possible Transitions

00 -> 11 00->11-> 01

00 -> 01 -> 11 00->01

00 -> 10 -> 11 00->10->11->01

Final total state y1y2 x =111 Final total state y1y2 x =011

The state variables must change from 00 to 11, which defines a race condition.

The listed transitions under each table show three possible ways that the state
variables may change.

They can either change simultaneously from 00 to 11, or they may change in
sequence from 00 to 01 and then to 11, or they may change in sequence from 00
to 10 and then to 11.

In all cases, the final stable state is the same, which results in a noncritical race
condition.
 5. RACE CONDITION –
CRITICAL AND NON-CRITICAL RACE CONDITION
Examples of Critical races:

We start with the total stable state y1y2x = 000 and then change the input
from 0 to 1.
x x
y 1y2 0 1 y1y2 0 1
00 11 00 11
00 00
01 11
01 01
11 11
11 11
10 10
10 10

(a) Possible Transitions (b) Possible Transitions

00 -> 11 00->11

00 -> 01 00->01->11

00 -> 10 00->10

The state variables must change from 00 to 11.

If they change simultaneously, the final total stable state is 111.

In the transition table (a), if Y2 changes to 1 before Y1 because of unequal

propagation delay, then the circuit goes to the total stable state 011 and remains
there.

On the other hand, if Y1 changes first, the internal state becomes 10 and the
circuit will remain in the stable total state 101.

Hence, the race is critical because the circuit goes to different stable states
depending on the order in which the state variables change.

In the transition table (b) two possible transitions result in one final total state,
but the third possible transition goes to a different final total state leading to
Critical race.
 5. RACE CONDITION –
CRITICAL AND NON-CRITICAL RACE CONDITION

CYCLES

Races can be avoided by directing the circuit through intermediate unstable states
with a unique state-variable change. When a circuit goes through a unique
sequence of unstable states, it is said to have a cycle.

Again, we start with y1y2 = 00 and change the input from 0 to 1. The transition
table (a) gives a unique sequence that terminates in a total stable state 101.

The table in (b) shows that even though the state variables change from 00 to 11,
the cycle provides a unique transition from 00 to 01 and then to 11, Care must be
taken when using a cycle that terminates with a stable state.

If a cycle does not terminate with a stable state, the circuit will keep going from
one unstable state to another, making the entire circuit unstable. This is
demonstrated in the transition table(c).
x x x
y1y2 0 1 y1y2 0 1 y1y2 0 1
00 01 00 01 00 01
00 00 00
11 11 11
01 01 01
10 11 10
11 11 11

10 10 01
10 10 10

(a) State transition: (b) State transition: (c) Unstable

00->01->11->10 00->01->11 01->11->10

 6. PROCEDURE FOR ANALYZING AN ASYNCHRONOUS
SEQUENTIAL CIRCUIT WITH SR LATCH
The procedure for analyzing an Asynchronous Sequential circuit with SR Latch:

1. Label each latch output with Yi, and its external feedback path (if any) with yi for
i=1,2, ... k.

2. Derive the Boolean functions for the Si and Ri inputs in each latch.

3. Check whether SR = 0 for each NOR latch or whether S 'R' = 0 for each NAND
latch. If this condition is not satisfied, there is a possibility that the circuit may not
operate properly.

4. Evaluate Y = S + R' y for each NOR latch or Y = S' + Ry for each NAND latch.

5. Construct a map with the y's representing the rows and the x inputs representing
the columns.

6. Plot the value of Y = Y1, Y2 … Yk, in the map.

7. Circle all stable states where Y = y. The resulting map is then the transition table.

Example:

The given circuit has two SR latches with outputs Y1 and Y2. There are two inputs, x1
and x2 and two external feedback loops giving rise to the secondary variables y1
and y2.

Fig 6.1 Example of a circuit with SR latches

 6. PROCEDURE FOR ANALYZING AN ASYNCHRONOUS
SEQUENTIAL CIRCUIT WITH SR LATCH
For the given circuit, the Boolean functions for the S and R inputs in each latch
are written as follows:
S 1 = x 1 y2 S2 = x 1 x 2
R1 = x1’x2’ R2 = x2’y1

Now, check whether SR =0 to ensure proper operation.

S1R1 = x1y2x1’x2’ = 0

S2R2 = x1x2x2’y1 = 0

The next step is to derive the transition table of the circuit. Remember that the
transition table specifies the value of Y as a function of y and x. The excitation
functions are derived from the relation Y = S + R' y.

Y1 = S1 + R1’y1 = x1y2 + (x1+x2) y1 = x1y2 + x1y1 + x2y1

Y2 = S2 + R2’y2 = x1x2 + (x2 + y1’) y2 = x1x2 + x2y2 + y1’y2

We now develop a composite map for Y = Y1Y2 .The y variables are assigned to
the rows in the map, and the x variables are assigned to the column. The Boolean
functions of Y1 and Y2 , as expressed above are used to plot the composite map
for Y.

The entries of Y in each row that have the same value as that given to Y are
circled and represent stable states.

Transition table for the circuit in Fig 6.1

 7 . Key Debounce Circuit

What is Key Bouncing?

When we press a pushbutton or toggle switch or a micro switch, two metal

parts come into contact to short the supply. But they don’t connect instantly but the
metal parts connect and disconnect several times before the actual stable
connection is made. The same thing happens while releasing the button. This
results the false triggering or multiple triggering like the button is pressed
multiple times. Its like falling a bouncing ball from a height and it keeps bouncing
on the surface, until it comes at rest.

Debouncing is any kind of hardware device or software that ensures that only a
single signal will be acted upon for a single opening or closing of a contact.
When you press a key on your computer keyboard , you expect a single contact to
be recorded by your computer.

Key Debouncing : When you press a key down and it triggers the switch,
sometimes the key can bounce. Since computers run so quickly, this bouncing can
register as multiple keystrokes as it triggers the switch multiple
times. Debouncing mechanisms detect these bounces and register them as only
one keystroke so you have more reliable key input.
There are various implementations of circuits which can be used for
eliminating the effect of switch debouncing right at the hardware level. The
different types of circuits used are:
 7. Key Debounce Circuit

A debounce circuit is a circuit which removes the series of pulses that

result from a contact bounce and produces a single smooth transition of the
binary signal from 0 to 1 or from 1 to 0. One such circuit consists of a single-pole,
double-throw switch connected to an SR latch, as shown below. The center
contact is connected to ground that provides a signal equivalent to logic 0. When
one of the two contacts, A or B, is not connected to ground through the switch, it
behaves like a logic-1 signal. When the switch is thrown from position A to
position B and back, the outputs of the latch produce a single pulse as shown,
negative for Q and positive for Q'. The switch is usually a push button whose
contact rests in position A. When the pushbutton is depressed, it goes to position
B and when released, it returns to position A.

Debounce circuit

The operation of the debounce circuit is as follows: When the switch

resets in position A, we have the condition S = 0, R = 1 and Q = 1, Q' = 0. When
the switch is moved to position B, the ground connection causes R to go to 0,
while S becomes a 1 because contact A is open. This condition in turn causes
output Q to go to 0 and Q' to go to 1. After the switch makes an initial contact
with B, it bounces several times. The output of the latch will be unaffected by the
contact bounce because Q' remains 1 (and Q remains 0) whether R is equal to 0
(contact with ground) or equal to 1 (no contact with ground). When the switch
returns to position A, S becomes 0 and Q returns to 1. The output again will
exhibit a smooth transition, even if there is a contact bounce in position A.
 8. Implementing a Circuit with SR Latch
SR Latch

SR Latch is also called as Set Reset Latch. This latch affects the outputs as long as the
enable, E is maintained at ‘1’. The circuit diagram of SR Latch is shown in the following
figure.

SR Latch

This circuit has two inputs S & R and two outputs Qtt & Qtt’. The upper NOR
gate has two inputs R & complement of present state, Qtt’ and produces next
state, Qt+1t+1when enable, E is ‘1’.
Similarly, the lower NOR gate has two inputs S & present state, Qtt and produces
complement of next state, Qt+1t+1’ when enable, E is ‘1’.
We know that a 2-input NOR gate produces an output, which is the complement of
another input when one of the input is ‘0’. Similarly, it produces ‘0’ output, when
one of the input is ‘1’.
If S = 1, then next state Qt+1t+1 will be equal to ‘1’ irrespective of present
state, Qtt values.
If R = 1, then next state Qt+1t+1 will be equal to ‘0’ irrespective of present
state, Qtt values.
At any time, only of those two inputs should be ‘1’. If both inputs are ‘1’,
then the next state Qt+1t+1 value is undefined.
The following table shows the state table of SR latch.

S R Qt+1t+1

0 0 Qtt

0 1 0

1 0 1

1 1 -
 8. Implementing a Circuit with SR Latch

Pulse mode asynchronous sequential circuits rely on the input pulses

rather than levels. They allow only one input variable to change at a time. They
can be implemented by employing a SR latch.
The procedure for analyzing an asynchronous sequential circuit with SR
latches can be summarized as follows:
1. Label each latch output with Yi and its external feedback path (if any) with yi for
i = 1,2 ,..,, k.
2. Derive the Boolean functions for the Si and Ri inputs in each latch.
3. Check whether SR = 0 for each NOR latch or whether S'R' = 0 for each NAND
latch. If either of these condition is not satisfied, there is a possibility that the circuit
may not operate properly.
4. Evaluate Y = S + R’y for each NOR latch or Y = S' + Ry for each NAND
latch.
5. Construct a map with the y’s representing the rows and the x inputs
representing the columns.
6. Plot the value of Y= Y1Y2 ……Yk in the map.
7. Circle all stable states such that Y = y. The resulting map is the transition
table.
The analysis of a circuit with latches will be demonstrated by means of the
below example.
Example : Derive the transition table for the pulse mode asynchronous sequential
circuit shown below.
 8. Implementing a Circuit with SR Latch

Solution:
T here are two inputs x1 and x2 and two external feedback loops giving rise to
the secondary variables y1 and y2.
Step 1:
The Boolean functions for the S and R inputs in each latch are:
S1= x1y2 S2= x1x2 R1= x1’x2’ R2= x2’y1
Step 2:
Check whether the conditions SR= 0 is satisfied to ensure proper operation of the
circuit.
S1R1= x1y2 x1’x2’ = 0 S2R2= x1x2 x2’y1 = 0
The result is 0 because x1x1’ = x2x2’ = 0
Step 3:
Evaluate Y1 and Y2. The excitation functions are derived from the relation
Y= S+ R’y.
Y1= S1+ R1’y1 = x1y2 +(x1’x2’)’ y1 = x1y2 +(x1+ x2) y1 = x1y2 +x1y1+ x2y1
Y2= S2+ R2’y2 = x1x2+ (x2’y1)’y2 = x1x2+ (x2+ y1’) y2 = x1x2+ x2y2+ y1’y2
Step 4:
Maps for Y1 and Y2.
8. Implementing a Circuit with SR Latch

Step 5:
Transition Table

Flash Cards
Link: https://quizlet.com/_8l9o3j?x=1qqt&i=2zp4cc
 9. Design of Asynchronous Sequential Circuit- Procedure

Asynchronous Sequential circuits

An asynchronous sequential circuit is the one in which the transition from one state to another is
initiated by the change in the primary inputs. i.e there is no external synchronization.

Asynchronous sequential circuits do not use clock signals as synchronous circuits . These
circuit are driven by the pulses of the inputs which means the state of the circuit changes when the
inputs change. Their memory elements are either un-clocked flip-flops or time-delay elements which
are usually implemented by a feedback among logic gates.

Thus, asynchronous sequential circuits may be regarded as combinational circuits with feedback.
Advantages
No clock signal, hence no waiting for a clock pulse to begin processing inputs, therefore fast.
Lower power consumption because no transistor transitions when it is not performing a useful
computation. Absence of clock drivers reduce power consumption.

More tolerant to process variations and external voltage fluctuations.

Circuit speed adapts to changing temperature and voltage conditions. Immunity to transistor-to-
transistor variability in the manufacturing process, which is one of the most serious problems faced
by the semiconductor industry

Disadvantages
 More difficult to design

 Difficult to test and debug. Their output is uncertain.

 Performance of asynchronous circuits may be reduced in architectures that have a complex data
path
9. Design of Asynchronous Sequential Circuit- Procedure

Design Procedure
There are a number of steps that must be carried out in order to minimize the
circuit complexity and to produce a stable circuit without critical races. Briefly, the
design steps are as follows:
1. Obtain a primitive flow table from the given specification.
2. Reduce the flow table by merging rows in the primitive flow table.
3. Assign binary states variables to each row of the reduced flow
table to obtain the transition table.
4. Assign output values to the dashes associated with the unstable states to obtain
the output maps.
5. Simplify the Boolean functions of the excitation and output variables and draw the
logic diagram.
Design Example – Specification
Design a gated latch circuit with two inputs, G (gate) and D (data), and one
output Q. The gated latch is a memory element that accepts the value of D when
G = 1 and retains this value after G goes to 0. Once G = 0, a change in D does not
change the value of the output Q.

Step 1: Primitive Flow Table

A primitive flow table is a flow table with only one stable total state in each row.
The total state consists of the internal state combined with the input.
To derive the primitive flow table, first a table with all possible total states in the
system is needed:
 9. Design of Asynchronous Sequential Circuit- Procedure

The resulting primitive table for the gated latch is shown below:

First, we fill in one square in each row belonging to the stable state in that row.
Next recalling that both inputs are not allowed to change at the same time, we enter dash
marks in each row that differs in two or more variables from the input variables associated
with the stable state.
Next we find values for two more squares in each row. The comments listed in the
previous table may help in deriving the necessary information. A dash indicates don’t care
conditions.
Step 2: Reduction of the Primitive Flow Table
The primitive flow table can be reduced to a smaller number of rows if two or more stable
states are placed in the same row of the flow table. The simplified merging rules are as
follows:
1. Two or more rows in the primitive flow table can be merged into one if there are non
conflicting states and outputs in each of the columns.
2. Whenever, one state symbol and don’t care entries are encountered in the same
column, the state is listed in the merged row.
3. If the state is circled in one of the rows, it is also circled in the merged row.
4. The output state is included with each stable state in the merged row. Now apply these
rules to the primitive flow table shown previously.

To see how this is done the primitive flow table is separated into two parts of three rows
each:
 9. Design of Asynchronous Sequential Circuit- Procedure

Each part shows three stable states that can be merged because there no
conflicting entries in each of the four columns. Since a dash represents a don’t
care condition it can be associated with any state or output. The first column of
can be merged into a stable state c with output 0, the second into a stable state a
with output 0, etc.
The resulting reduced flow table is as follows:

Step 3: Transition Table and Logic Diagram

To obtain the circuit described by the reduced flow table, a binary value must be
assigned to each state. This converts the flow table to a transition table.
In assigning binary states, care must be taken to ensure that the circuit will be free
of critical races. No critical races can occur in a two-row flow table.
Assigning 0 to state a and 1 to state b in the reduced flow table, the following
transition table is obtained:

The transition table is, in effect, a map for the excitation variable Y.
The simplified Boolean function for Y as obtained from the map is:
Y = DG +G′’y
9. Design of Asynchronous Sequential Circuit- Procedure

There are two don’t care outputs in the final reduced flow table. By
assigning values to the output as shown below:

It is possible to make output Q equal to Y. If the other possible

values are assigned to the don’t care outputs, output Q is made
equal to y. In either case, the logic diagram of the gated latch is as
follows:
REDUCTION OF STATE AND FLOW TABLES

State Reduction (State Minimization)

Since (N) flip-flops produce (2N) states, a reduction in the number of states may (or
may not) result in a reduction in the number of flip-flops. For example if a finite
state machine drops from 8 states to 4 states, only two flip-flops are required rather
than three. The total number of states is reduced by eliminating the equivalent
states.
To illustrate the state reduction procedure with an example."Two states are
said to be equivalent if, for each member of the set of inputs, they give exactly the
same output and send the circuit either to the same state or to an equivalent state."
When two states are equivalent, one of them can be removed without altering the
input-output relationships.

Present
Next State Output
State X=0 X=1 X=0 X=0

Reduced State diagram and state table

Present
Next State Output
State X=0 X=1 X=0 X=0
REDUCTION OF STATE AND FLOW TABLES

State Reduction using the Implication Table(Completely

Specified Tables)

One method to eliminate the redundant states is to use an implication table. The
implication table is a chart that consists of squares, one for every possible pair of
states,that provide spaces for listing any possible implied states.
On the left side along the vertical are listed all the states defined in the state table
except the first, and across the bottom horizontally are listed all the states except
the last. The result is a display of all possible combinations of two states with a
square placed in the intersection of a row and a column where the two states can be
tested for equivalence.
Two states that are not equivalent are marked with a cross (X) in the corresponding
square, whereas their equivalence is recorded with a check mark ( ).

Procedure of filling in the squares

1. Place a cross in any square corresponding to a pair of states whose outputs

are not equal for every input.
2. Enter in the remaining squares the pairs of states that are implied by the pair
of states representing the squares.
3. Make successive passes through the table to determine whether any
additional squares should be marked with a cross. A square in the table is
crossed out if it contains at least one implied pair that is not equivalent.
This procedure is repeated until no additional squares can be crossed out.
1. All the squares that have no crosses are recorded with check marks. These
squares define pairs of equivalent states.
2. Finally,combine pairs of states into larger groups of equivalent states.
REDUCTION OF STATE AND FLOW TABLES

Example
Consider the state table to be reduced.

Present
Next State Output
State X=0 X=1 X=0 X=0

Solution:

The procedure is as follows:

1. List state-combination possibilities in an implication table,

2. Eliminate combinations that are impossible because the states produce
different outputs,
3. Eliminate combinations that are impossible because the combination depends
on the equivalence of a previously eliminated possibility,
4. Repeat the above step until no more eliminations are possible.

d,e
b

c x x

d x x x

e x x x

c,d x c,e x
f a,b a,b
x x x

x x x d,e d,e x
REDUCTION OF STATE AND FLOW TABLES

Now combine pairs of states into larger groups of equivalent states.

The last three pairs can be combined into a set of three equivalent states (d,e,g)
because each one of the states in the group is equivalent to the other two.

The final partition of the states consists of the equivalent states found from the
implication table, together with all the remaining states in the state table that are
not equivalent to any other state.

(a,b) (c) (d,e,g) (f)

The State Table can be reduced from seven states to four states, one for each
member of the above partition. The reduced table is obtained by replacing state (b
by a and states e and g by d).

Present
Next State Output
State X=0 X=1 X=0 X=0

Activity

This is an interactive Implication Table. You can change the Next State and Present
Output of the Next State Table. Press the Calculate button to re-evaluate the Implication
Table using your modified values

http://electronics-course.com/implication-
table#:~:text=State%20Reduction%20using%20the%20Implication,to%20use%20an%20imp
lication%20table.&text=If%20the%20outputs%20are%20the%20same%20and%20if%20both
%20the,a%20%E2%9C%93%20in%20the%20square.
REDUCTION OF STATE AND FLOW TABLES

Merging of the Flow Table - Incompletely specified states table

Incompletely specified states can be combined to reduce the number of state in the
flow table. Such states cannot be called equivalent because the formal definition of
equivalence requires that all outputs and next states be specified for all inputs.
Instead, two incompletely specified states that can be combined are said to be
Compatible.
The process that must be applied in order to find a suitable group of compatibles for
the purpose of merging a flow table can be divided into three steps:
1. Determine all compatible pairs by using the implication table.
2. Find the maximal compatibles with the use of a merger diagram.
3. Find a minimal collection of compatibles that covers all the states and
is closed (Closed Covering)

Compatible Pairs-The entries in each square of primitive flow table represent the
next state and output The dashes represent the unspecified states or outputs. The
implication table is used to fmd compatible states just as it is used to find equivalent
stales in the completely specified case. The only difference is that, when comparing
rows, there is a liberty to adjust the dashes to fit any desired condition.
00 01 11 10 b

a c,-- a ,0 b,-- --,-- d,e

c x
b --,-- a,-- b ,1 e,--
d,e
d x
c c ,0 a,-- --,-- d,--
c,f
d c,-- --,-- b,-- d ,0 d,e x d,e x
e c,f x
x
e f,-- --,-- b,-- e ,1
c,f
f f ,1 a,-- --,-- e,-- d,e x
f x c,f x
x
a. Primitive flow table
a b c d e
Compatible Pairs are (a,b) (a,c) (a,d) (b,e) (b,f) (c,d) (e,f) b.Implication table
REDUCTION OF STATE AND FLOW TABLES

Maximal Compatibles

The maximal compatible is a group of compatibles that contains all the possible
combinations of compatible states. The maximal compatible can be obtained
from a merger diagram.

The merger diagram is a graph in which each state is represented by a dot placed
along the circumference of a circle. Lines are drawn between any two corresponding
dots that form a compatible pair. All possible compatibles can be obtained from the
merger diagram by observing the geometrical patterns in which states are
connected to each other. An isolated dot represents a state that is not compatible
with any other state. A line represents a compatible pair. A triangle constitutes a
compatible with three states.

The maximal compatible pairs in a are (a,b) (a,c,d) (b,e,f)

The maximal compatible pairs in b are (a,b,e,f) (b,c,h) (c,d) (g)
REDUCTION OF STATE AND FLOW TABLES

Closed-Covering Condition

The condition that must be satisfied for merging rows is that the set of chosen
compatibles must cover all the states and must be closed. The set will cover all the
states if it includes all the states of the original state table. The closure condition is
satisfied if there are no implied states or if the implied states are included within the
set. A closed set of compatibles that covers all the states is called a closed covering.

Consider the maximal compatibles from merger diagram (a). If (a, b), were removed
the left with two compatibles (a,c,d) (b,e,f)

Flow diagram of (a, c, d) (b, e,f)

00 01 11 10 00 01 11 10

a c,-- a ,0 b,-- --,-- b --,-- a,-- b ,1 e,--

c c ,0 a,-- --,-- d,-- e f,-- --,-- b,-- e ,1

d c,-- --,-- b,-- d ,0 f f ,1 a,-- --,-- e,--

Reduced Table

00 01 11 10

a c ,0 a ,0 b,-- d ,0

b f ,1 a,-- b ,1 e ,1

After renaming 00 01 11 10

a a ,0 a ,0 b,-- a ,0

b b ,1 a,-- b ,1 b ,1
Reduce the primitive flow table given in the implication table blow.

00 01 11 10
b,c
b
a a ,0 b,-- --,-- c ,1
d,e
c x b d ,0 c,-- a ,0 --,--

b,c a,d c e ,1 --,-- a,-- b,--

d x
d --,-- c,-- d ,1 c,--

e b,c
x e e ,1 b,-- --,-- --,--
x

aa. Implication
b c table d b. Primitive flow table
Solution:
i) Compatible pairs
(a,b) (a,d) (b,c) (c,d) (c,e) (d,e)
ii) Maximal Compatibles using merger diagram

Maximal Compatibles
(c,d,e) (a,d) (a,b) (b,c)

iii) Minimal Collections of compatibles(Closed Covering) (a,d) (b,c) (c,d,e) cover

all the states,closed
(c,d,e) (a,b) Covers all the states but not closed implied states: (b,c)
iv) Closure Covering (d,e) (a,d)
Note:
Compatible Pairs a,b a,d b,c c,d,e
the same state can be
Implied States b,c b,c d,e a,d repeated more than
b,c
once
RACE-FREE STATE ASSIGNMENT

Applications
• Asynchronous sequential circuits are useful when circuit system must respond
quickly without waiting for clock.
• Asynchronous sequential circuit is important for small circuit which behaves
independently and contain few components

Advantages
• Robust handling of metastability and higher performance compare to
synchronous sequential circuit.
• Faster than Synchronous sequential circuit
• Lower power consumption
• Clock driver can be removed in this case because Clock is not used here so
power consumption of clock drivers and controller can be avoided.
• few assumptions are needed in manufacture process
• system speed adapts changes in environment and voltage levels
• Designing of power distribution network is easy here because here leakage
current will be less compare to synchronous sequential circuit

Disadvantages
• When some encoding is performed then asynchronous circuit requires more
area then synchronous circuit and because of the same power consumption
may increase
• Area of circuit is increased. No. of Transistors may be double here because of
addition of completion detection circuit and design for test circuit
• Synchronous sequential circuits are easier to test and debug compare to
asynchronous sequential circuit
• Performance of asynchronous sequential circuits may be reducing in
architecture which includes complex data paths and feedbacks.
• Race conditions are generated internally and cannot be handling by outside.
RACE-FREE STATE ASSIGNMENT

The assignment of binary values to each state results in the transformation of the
flow table into its equivalent transition table.
Critical races can be avoided by making a binary state assignment in such a way that
only one variable changes at any given time when a state transition occurs in the
flow table.
To accomplish this, it is necessary that
● States between which transitions occur be given adjacent assignments.
● Two binary values are said to be adjacent if they differ in only one variable.
For example, 010 and 011 are adjacent because they only differ in the third bit.

Shared Row State Assignment Method

Three-Row Flow-Table
The assignment of a single binary variable to a flow table with two rows does not
impose critical race problems. A flow table with three rows requires an assignment
of two binary variables. The assignment of binary values to the stable states may
cause critical races if not done properly.
Example
Consider, for example, the reduced flow table below

00 01 11 10

a a b c a

b a b b c

c a c c c

A.Flow table
Inspection of row a,there is a transition from state a to state b in column 01 and
from state a to state c in column 11. Similarly, the transitions from the other two
rows are represented by directed lines in the transition diagram.
RACE-FREE STATE ASSIGNMENT

After all the stable states have been entered, the unstable states are filled in by
reference to the assignment specified in the map . When choosing the next state for
a given present state, a state that is adjacent to the present state is selected from
the map. In the original table, the next states of b are a and d for inputs 10 and 01,
respectively. In the expanded table, the next states for b1 are a1 and d2 because
these are the states adjacent to b1. Similarly, the next states for b2 are a2 and d1,
because they are adjacent to b2.

00 01 11 10

a1=000 b1 a1 d1 a1

a2=111 b2 a2 d2 a2

b1=001 b1 d2 b1 a1
-
b2=110 b2 d1 b2 a2

c1=011 c1 a2 b1 c1

c2=100 c2 a1 b2 c2

d1=010 c1 d1 d1 c1

d2=101 c2 d2 d2 c2

Modified Flow Table

In the multiple-row assignment, the change from one stable state to another will
always cause a change of only one binary state variable. Each stable state has two
binary assignments with exactly the same output.For example, if we start with state
a1 and input 01 and then change the input to 11, 01, 00, and back to 01, the
sequence of internal states will be a1, d1 c1,and d2.
Assigning Outputs to Unstable States

The stable states in a flow table have specific output values associated with them
and the unstable states have unspecified output entries designated by a dash. The
output values for the unstable states must be chosen so that no momentary false
outputs occur when the circuit switches between stable states. This means that if an
output variable is not supposed to change as the result of a transition, then an
unstable state that is a transient state between two stable states must have the
same output value as the stable states.

Consider, the flow table fig. A

a ,0 b,-- 0 0

c,-- b,0 x 0

c ,1 d,-- 1 1

a,-- d,1 x 1

fig. A Flow Table fig. B Output assignment

A transition from stable state a to stable state b goes through the unstable state b.
If the output assigned to the unstable b is a 1, then a momentary short pulse will
appear on the output as the circuit shifts from an output of 0 in state a to an output
of 1 for the unstable b and back to 0 when the circuit reaches stable state b.

Thus the output corresponding to unstable state b must be specified as 0 to avoid a

momentary false output. If an output variable is to change value as a result of a
state change, then this variable is assigned a don't-care condition.
Assigning Outputs to Unstable States

For example, the transition from stable state b to stable state c in fig.A, changes the
output from 0 to 1. If a 0 is entered as the output value for unstable c, then the
change in the output variable will not take place until the end of the transition.If a 1
is entered, the change will take place at the start of the transition. Since it makes no
difference when the output change occurs, we place a don't care entry for the
output associated with unstable state c. fig B shows the output assignment for the
flow table. It demonstrates the four possible combinations in output change that can
occur.

The procedure for making the assignment to outputs associated with

unstable states can be summarized as follows:
1. Assign a 0 to an output variable associated with an unstable state that is a
transient state between two stable states that have a 0 in the corresponding output
variable.
2. Assign a 1 to an output variable associated with an unstable state that is a
transient state between two stable states that have a 1 in the corresponding output
variable.
3. Assign a don't-care condition to an output variable associated with an unstable
state that is a transient state between two stable states that have different values (0
and 1 or 1 and 0) in the corresponding output variable

Example: Assign Outputs to Unstable States

a ,0 a ,0 b,-- a ,0
Soln:
b ,1 a,-- b ,1 b ,1

a ,0 a ,0 b,x a ,0

b ,1 a,x b ,1 b ,1
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT
The design of an asynchronous sequential circuit starts from the
statement of the problem and concludes in a logic diagram.
Design Procedure
The design steps are as follows:
Draw the flow diagram or State Diagram from the given design
specifications.
Obtain a primitive flow table from the given design specifications and
specify the outputs associated with the stable states.
Reduce the flow table by merging rows in the primitive flow table.
Assign binary state variables to each row of the reduced flow table to
obtain the transition table. The procedure of state assignment
eliminates any possible critical races.
Assign output values to the dashes associated with the unstable states
to obtain the output maps.
Simplify the Boolean functions of the excitation and output variables
and draw the logic diagram.

Primitive Flow Table

Primitive flow table is a flow table which has exactly one stable state for each row
in the table.

Stable State

For a given values of input variables, the system is stable if the circuit reaches a
steady state condition with yi = Yi , where yi is present state and Yi is the next
state.

Closed covering condition

The condition that must be satisfied for row merging is that the set of chosen
compatibles must cover all the states and must be closed. The set will cover all
the states if it includes all the states of the original state table. A closed set of
compatibles that covers all the states is called a closed covering.
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

1. Design a negative-edge triggered T flip-flop. The circuit has two inputs,

T (toggle) and C (clock), and one output, Q. the output state is
complemented if T= 1 and the clock changes from 1 to 0 (negative-
edge triggering). Otherwise, under any other input condition, the
output Q remains unchanged.

Solution

Step 1: Draw the flow diagram based on the given specifications

Let T and C are the two inputs.

Considering negative edge triggering,

a) If T=1 and C (Changes from 1 to 0), output Q complements.

b) If T=0 or 1 and C (changes from 0 to 1), output Q : No change

Starting with the input condition TC= 11 and assign it to state a. Draw the Flow
Diagram.
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

1. Design a negative-edge triggered T flip-flop. The circuit has two inputs,

T (toggle) and C (clock), and one output, Q. the output state is
complemented if T= 1 and the clock changes from 1 to 0 (negative-
edge triggering). Otherwise, under any other input condition, the
output Q remains unchanged.

Step 2: Draw the state Diagram and the primitive flow table
The state diagram is shown below

The information for the primitive flow table can be obtained directly from the
above state diagram. We first fill in one square in each row belonging to stable
state in that row as given in the state diagram.
Then we enter dashes in those squares whose input differs by two variables from
the input corresponding to the stable state.
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

1. Design a negative-edge triggered T flip-flop. The circuit has two inputs,

T (toggle) and C (clock), and one output, Q. the output state is
complemented if T= 1 and the clock changes from 1 to 0 (negative-
edge triggering). Otherwise, under any other input condition, the
output Q remains unchanged.

The primitive flow table is shown below.

Step 3: Finding Compatible pairs through Implication Table

Implication table
The squares that contain the Tick marks define the compatible pairs: (a,c) (b, g)
(b,d) (c,h) (c,f) (d,g) (e,g) (f,h)
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

1. Design a negative-edge triggered T flip-flop. The circuit has two inputs,

T (toggle) and C (clock), and one output, Q. the output state is
complemented if T= 1 and the clock changes from 1 to 0 (negative-
edge triggering). Otherwise, under any other input condition, the
output Q remains unchanged.

Step 4: Draw the Merger Diagram

The merger diagram is a graph in which each state is represented by a dot placed
along the circumference of a circle. Lines are drawn between any two
corresponding dots that form a compatible pair.

Maximal compatibles are, (b,d,g) (c,f,h) (a,c) (e,g)

Closed Covering:

If we remove any of the pair, we cannot get all the states. Therefore, the closed
condition is satisfied by considering all the maximal compatibles. So, we cannot
remove any of the pairs.
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

1. Design a negative-edge triggered T flip-flop. The circuit has two inputs,

T (toggle) and C (clock), and one output, Q. the output state is
complemented if T= 1 and the clock changes from 1 to 0 (negative-
edge triggering). Otherwise, under any other input condition, the
output Q remains unchanged.

Reduced Flow Table is,

Step 5: State Assignment and reduced table is,

After assigning race free-binary state assignment , the Transition Table is

 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

1. Design a negative-edge triggered T flip-flop. The circuit has two inputs,

T (toggle) and C (clock), and one output, Q. the output state is
complemented if T= 1 and the clock changes from 1 to 0 (negative-
edge triggering). Otherwise, under any other input condition, the
output Q remains unchanged.

Solution

Step 6: Therefore, Transition table and Output Map is,

Fig. Transition Table Fig. Output Map

Step 7: K-Maps for deriving equations using SR Latches using NOR with inputs S1,R1,
S2 and R2
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

1. Design a negative-edge triggered T flip-flop. The circuit has two inputs,

T (toggle) and C (clock), and one output, Q. the output state is
complemented if T= 1 and the clock changes from 1 to 0 (negative-
edge triggering). Otherwise, under any other input condition, the
output Q remains unchanged.

Solution

Step 8: Logic Diagram

 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

2. Develop a state diagram and primitive flow table for a logic system that has
two inputs, X and Y, and a single output X, which is to behave in the
following manner. Initially, both inputs and output are equal to 0.
Whenever X= 1 and Y= 0, the Z becomes 1 and whenever X= 0 and Y= 1,
the Z becomes 0. When inputs are zero, i.e. X= Y= 0 or inputs are one, i.e.
X= Y= 1, the output Z does not change; it remains in the previous state.
The logic system has edge triggered inputs without having a clock. The
logic system changes state on the rising edges of the two inputs. Static
input values are not to have any effect in changing the Z output.

Solution:

The conditions given are, Initially both inputs X and Y are 0.

• When X= 1, Y= 0; Z= 1

• When X= 0, Y= 1; Z= 0

• When X= Y= 0 or X= Y= 1, then Z does not change, it remains in the previous state.

Step 1: Draw State Diagram

The above state transitions are represented in the state diagram as,
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

2. Develop a state diagram and primitive flow table for a logic system that
has two inputs, X and Y, and a single output X, which is to behave in the
following manner. Initially, both inputs and output are equal to 0.
Whenever X= 1 and Y= 0, the Z becomes 1 and whenever X= 0 and Y=
1, the Z becomes 0. When inputs are zero, i.e. X= Y= 0 or inputs are
one, i.e. X= Y= 1, the output Z does not change; it remains in the
previous state. The logic system has edge triggered inputs without
having a clock. The logic system changes state on the rising edges of
the two inputs. Static input values are not to have any effect in
changing the Z output.
Step 2: A primitive flow table is constructed from the state diagram.

Step 3: Implication table

The compatible pairs: (A, B) (A, D) (A, F) (B, D) (C, E) (C, F) (D, E) (E,F)
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

2. Develop a state diagram and primitive flow table for a logic system that
has two inputs, X and Y, and a single output X, which is to behave in the
following manner. Initially, both inputs and output are equal to 0.
Whenever X= 1 and Y= 0, the Z becomes 1 and whenever X= 0 and Y=
1, the Z becomes 0. When inputs are zero, i.e. X= Y= 0 or inputs are
one, i.e. X= Y= 1, the output Z does not change; it remains in the
previous state. The logic system has edge triggered inputs without
having a clock. The logic system changes state on the rising edges of
the two inputs. Static input values are not to have any effect in
changing the Z output.
Step 4: Merger Diagram
The lines form a geometrical pattern consisting of two triangles connecting (A, B,
D) & (C, E, F) .
The maximal compatibles are:(A, B, D) (C,E, F). It has all six states and satisfies
closed covering condition.

The reduced flow table is drawn as below.

Here we assign a common letter symbol to all the stable states in each merged
row. Thus, the symbol B & D is replaced by A; E & F are replaced by C.
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

2. Develop a state diagram and primitive flow table for a logic system that
has two inputs, X and Y, and a single output X, which is to behave in the
following manner. Initially, both inputs and output are equal to 0.
Whenever X= 1 and Y= 0, the Z becomes 1 and whenever X= 0 and Y=
1, the Z becomes 0. When inputs are zero, i.e. X= Y= 0 or inputs are
one, i.e. X= Y= 1, the output Z does not change; it remains in the
previous state. The logic system has edge triggered inputs without
having a clock. The logic system changes state on the rising edges of
the two inputs. Static input values are not to have any effect in
changing the Z output.
Step 5: Find the race-free binary assignment for the four stable states in the
reduced flow table. Assign A= 0 and C= 1.
Substituting the binary assignment into the reduced flow table, the transition
table is obtained. The output map is obtained from the reduced flow table.

Step 6: Draw the Logic Diagram

 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

3. Design a gated latch circuit with two inputs, G (gate) and D (data), and one
output, Q. Binary information present at the D input is transferred to the Q
output when G is equal to I. The Q output will follow the D input as long as
G = I. When G goes to 0, the information that was present at the D input at
the time the transition occurred is retained at the Q output. The gated latch
is a memory element that accepts the value of D when G = I and retains this
value after G goes to O. Once G = 0, a change in D does not change the
value of the output Q.
Solution:
The given design specifications are
• When G=1, Q = D
• When G=0, Q= No change
The flow diagram can be drawn as,

Primitive Flow Table is,

 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

3. Design a gated latch circuit with two inputs, G (gate) and D (data), and one
output, Q. Binary information present at the D input is transferred to the Q
output when G is equal to I. The Q output will follow the D input as long as
G = I. When G goes to 0, the information that was present at the D input at
the time the transition occurred is retained at the Q output. The gated latch
is a memory element that accepts the value of D when G = I and retains this
value after G goes to O. Once G = 0, a change in D does not change the
value of the output Q.
The implication table is,

Maximal Compatibles are,

(a,b,d) (c,e,f) (a,c)

Here, (a,b,d) and (c,e,f) covers all the states and satisfies the closed covering
condition. Therefore, minimal compatibilities are,

(a,b,d) and (c,e,f)

 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

3. Design a gated latch circuit with two inputs, G (gate) and D (data), and one
output, Q. Binary information present at the D input is transferred to the Q
output when G is equal to I. The Q output will follow the D input as long as
G = I. When G goes to 0, the information that was present at the D input at
the time the transition occurred is retained at the Q output. The gated latch
is a memory element that accepts the value of D when G = I and retains this
value after G goes to O. Once G = 0, a change in D does not change the
value of the output Q.
Reduced flow table is,

The above table can be written as,

The binary state assignment is,

Since only two states , a->0 and b->1.

 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

3. Design a gated latch circuit with two inputs, G (gate) and D (data), and one
output, Q. Binary information present at the D input is transferred to the Q
output when G is equal to I. The Q output will follow the D input as long as
G = I. When G goes to 0, the information that was present at the D input at
the time the transition occurred is retained at the Q output. The gated latch
is a memory element that accepts the value of D when G = I and retains this
value after G goes to O. Once G = 0, a change in D does not change the
value of the output Q.
Output Assignment is,

K-maps for Latch inputs and Output,

Logic Diagram with SR Latch is,

 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

4. Design an asynchronous sequential circuit with two inputs X and Y and one
output Z. Whenever Y is 1, input X is transferred to Z. Whenever Y is 0,
output does not change for any change in X.
Solution:

Given design specifications are,

Inputs : X and Y
Output : Z
• If Y = 1, Z= X
• If Y = 0, Z = No change.
The Flow diagram can be drawn as,

The state diagram is,

 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

4. Design an asynchronous sequential circuit with two inputs X and Y and one
output Z. Whenever Y is 1, input X is transferred to Z. Whenever Y is 0,
output does not change for any change in X.
The Primitive table is,

Reduced primitive table is,

 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

4. Design an asynchronous sequential circuit with two inputs X and Y and one
output Z. Whenever Y is 1, input X is transferred to Z. Whenever Y is 0,
output does not change for any change in X.
Therefore, the compatible pairs are,
(a,b) (a,c) (b,c) (b,d) (d,e) (d,f) (e,f)
The Merger graph is,

Therefore, the minimal compatibilities are (a,b,c) (d,e,f) (b,d)

The minimal compatibilities using closed covering is, (a,b,c) (d,e,f)

Now, the Reduced primitive table is,

S0 ->(a,b,c)

S1 -> (d,e,f)
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

4. Design an asynchronous sequential circuit with two inputs X and Y and one
output Z. Whenever Y is 1, input X is transferred to Z. Whenever Y is 0,
output does not change for any change in X.
The Transition table is,

Where, f -> present state and F -> Next State Equation

z -> Output

The K-maps are,

F = XY + f Y’
z=f

The Logic diagram is,

 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

5. Design a circuit with primary inputs A and B to give an output Z equal to

1 when A becomes 1 if B is already 1. Once Z= 1 it will remain so until A
goes to 0. Draw the total state diagram, primitive flow table for
designing this circuit.

Solution:
Step 1: The state diagram can be drawn as,

Step 2:

A primitive flow table is constructed from the state table as,

 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

6. Design an asynchronous sequential circuit that has two inputs X2 and

X1 and one output Z. When X1= 0, the output Z is 0. The first change in
X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z
will remain 1 until X1 returns to 0.
Solution:
Step 1: The state diagram can be drawn as,

Step 2:
A primitive flow table is constructed from the state table as,
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

6. Design an asynchronous sequential circuit that has two inputs X2 and

X1 and one output Z. When X1= 0, the output Z is 0. The first change in
X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z
will remain 1 until X1 returns to 0.
Step3:
The rows in the primitive flow table are merged by obtaining all compatible
pairs of states. This is done by means of the implication table.

The compatible pairs: (A, B) (A, C) (C, E) (D,F)

Step 4:
The merger diagram is obtained from the list of compatible pairs derived from the
implication table. There are four straight lines connecting the dots, one for each
compatible pair. It consists of four lines (A, B), (A, C), (C, E) and (D, F).
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

6. Design an asynchronous sequential circuit that has two inputs X2 and

X1 and one output Z. When X1= 0, the output Z is 0. The first change in
X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z
will remain 1 until X1 returns to 0.
Here, (A, B) (C,E) (D, F) covers all the states and satisfies the closed covering
condition. Therefore, minimal compatibilities are,
(A, B) (C,E) (D, F)
This set of maximal compatible covers all the original states resulting in the
reduced flow table.
The reduced flow table is drawn as below.

Here we assign a common letter symbol to all the stable states in each merged
row. Thus, the symbol B is replaced by A; E is replaced by C and F is replaced by
D.
Step 5:

Now we assign, A-> S0, C -> S1, D -> S2

Now, if we assign S0 = 00, S1 = 01 and S2 = 10, It creates critical race. So we

need one more state S3= 11 to prevent critical race during transition of S2 > S1 or
S1 -> S2. By introducing S3, the transitions S1 -> S2 and S2 -> S1 are routed
through S3.
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT
6. Design an asynchronous sequential circuit that has two inputs X2 and
X1 and one output Z. When X1= 0, the output Z is 0. The first change in
X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z
will remain 1 until X1 returns to 0.
Thus after state assignment the flow table can be given as,

Substituting the binary assignment into the reduced flow table, the transition
table is obtained. The output map is obtained from the reduced flow table.

K- Map simplification:
 13. DESIGN OF ASYNCHRONOUS SEQUENTIAL CIRCUIT

6. Design an asynchronous sequential circuit that has two inputs X2 and

X1 and one output Z. When X1= 0, the output Z is 0. The first change in
X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z
will remain 1 until X1 returns to 0.
Logic Diagram
14. HAZARDS

Hazards are unwanted switching transients that may appear at the output of a
circuit because different paths exhibit different propagation delays.

Hazards occur in combinational circuits, where they may cause a temporary false-
output value. When this condition occurs in asynchronous sequential circuits, it
may result in a transition to a wrong stable state.

Hazards in Combinational Circuits:

A hazard is a condition where a single variable change produces a momentary

output change when no output change should occur.
Types of Hazards:

Static Hazard

Dynamic Hazard

Static Hazard:

In digital systems, there are only two possible outputs, a ‘0’ or a ‘1’. The hazard
may produce a wrong ‘0’ or a wrong ‘1’. Based on these observations, there are
three types,

Static-0 Hazard

Static-1 Hazard

Static-0 Hazard:

When the output of the circuit is to remain at 0, and a momentary 1 output is

possible during the transmission between the two inputs, then the hazard is called
a static 0-hazard.
HAZARDS

Static-1 Hazard:

When the output of the circuit is to remain at 1, and a momentary 0 output is

possible during the transmission between the two inputs, then the hazard is called
a static 1-hazard.

The circuit below demonstrates the occurrence of a static 1-hazard. Assume that
all three inputs are initially equal to 1 i.e., X1X2X3= 111. This causes the output of
the gate 1 to be 1, that of gate 2 to be 0, and the output of the circuit to be equal
to 1.

Now consider a change of X2 from 1 to 0 i.e., X1X2X3 = 101. The output of gate 1
changes to 0 and that of gate 2 changes to 1, leaving the output at 1. The output
may momentarily go to 0 if the propagation delay through the inverter is taken
into consideration.

Circuit with static-1 hazard

HAZARDS

The delay in the inverter may cause the output of gate 1 to change to 0 before
the output of gate 2 changes to 1. In that case, both inputs of gate 3 are
momentarily equal to 0, causing the output to go to 0 for the short interval of
time that the input signal from X2 is delayed while it is propagating through the
inverter circuit.

Thus, a static 1-hazard exists during the transition between the input states
X1X2X3= 111 and X1X2X3 = 101.

Now consider the below network, and assume that the inverter has an appreciably
greater propagation delay time than the other gates. In this case there is a static
0-hazard in the transition between the input states X1X2X3 = 000 and X1X2X3 = 010
since it is possible for a logic-1 signal to appear at both input terminals of the
AND gate for a short duration.

Circuit with static-0 hazard

The delay in the inverter may cause the output of gate 1 to change to 1 before
the output of gate 2 changes to 0. In that case, both inputs of gate 3 are
momentarily equal to 0, causing the output to go to 1 for the short interval of
time that the input signal from X2 is delayed while it is propagating through the
inverter circuit.

Thus, a static 0-hazard exists during the transition between the input states
X1X2X3 = 000 and X1X2X3 = 010.
HAZARDS

A hazard can be detected by inspection of the map of the particular circuit. To

illustrate, consider the map in the circuit with static 0-hazard, which is a plot of
the function implemented.

The change in X2 from 1 to 0 moves the circuit from minterm 111 to minterm 101.
The hazard exists because the change in input results in a different product term
covering the two minterrns.

Maps demonstrating a Hazard and its Removal

The minterm 111 is covered by the product term implemented in gate 1 and
minterm 101 is covered by the product term implemented in gate 2. Whenever
the circuit must move from one product term to another, there is a possibility of a
momentary interval when neither term is equal to 1, giving rise to an undesirable
0 output.

The remedy for eliminating a hazard is to enclose the two minterms in question
with another product term that overlaps both groupings. This situation is shown in
the map above, where the two terms that causes the hazard are combined into
one product term. The hazard- free circuit obtained by this combinational is
shown below.
HAZARDS

Hazard-Free Circuit

The extra gate in the circuit generates the product term X1X4. The hazards in
combinational circuits can be removed by covering any two minterms that may
produce a hazard with a product term common to both. The removal of hazards
requires the addition of redundant gates to the circuit.

Dynamic Hazard

A dynamic hazard is defined as a transient change occurring three or more times

at an output terminal of a logic network when the output is supposed to change
only once during a transition between two input states differing in the value of
one variable.

Now consider the input states X1X2X3= 000 and X1X2X3 = 100. For the first input
state, the steady state output is 0; while for the second input state, the steady
state output is 1.

To facilitate the discussion of the transient behavior of this network, assume there
are no propagation delays through gates G3 and G5 and that the propagation
delays of the other three gates are such that G1 can switch faster than G2 and G2
can switch faster than G4.
HAZARDS

Circuit with Dynamic Hazard

When X1 changes from 0 to 1, the change propagates through gate G1 before

gate G2 with the net effect that the inputs to gate G3 are simultaneously 1 and
the network output changes from 0 to 1. Then, when X1 change propagates
through gate G2, the lower input to gate G3 becomes 0 and the network output
changes back to 0.

Finally, when the X1= 1 signal propagates through gate G4, the lower input to
gate G5 becomes 1 and the network output again changes to 1. It is therefore
seen that during the change of X1 variable from 0 to 1 the output undergoes the
sequence, 0 1 0 1, which results in three changes when it should
have undergone only a single change.
HAZARDS

Essential Hazards

An essential hazard is caused by unequal delays along two or more paths that
originate from the same input. An excessive delay through an inverter circuit in
comparison to the delay associated with the feedback path may cause such a
hazard.

Essential hazards elimination:

Essential hazards can be eliminated by adjusting the amount of delays in the

affected path. To avoid essential hazards, each feedback loop must be handled
with individual care to ensure that the delay in the feedback path is long enough
compared with delays of other signals that originate from the input terminals.

Design of Hazard Free Circuits

1. Design a hazard-free circuit to implement the following function.

F (A, B, C, D) = ∑m (1, 3, 6, 7, 13, 15)

Solution:

K-map Implementation and grouping

F=A’B’D+ A’BC+ ABD

HAZARDS

Hazard- free realization

The first additional product term A’CD, overlapping two groups (group 1 & 2) and
the second additional product term, BCD, overlapping the two groups (group 2 &
3).

F=A’B’D+ A’BC+ ABD+ A’CD+ BCD

2. Design a hazard-free circuit to implement the following function.

F (A, B, C, D) = ∑m (0, 2, 6, 7, 8, 10, 12).

HAZARDS

Solution

K-map Implementation and grouping

F= B’D’+ A’BC+ AC’D’

Hazard- free realization

The additional product term, A’CD’ overlapping two groups (group 1 & 2) for hazard
free realization. Group 1 and 3 are already overlapped hence they do not require
additional minterm for grouping.

F= B’D’+ A’BC+ AC’D’+ A’CD’

HAZARDS

3. Design a hazard-free circuit to implement the following function.

F (I, J, K, L) = ∑m (1, 3, 4, 5, 6, 7, 9, 11, 15).

Solution

K-map Implementation and grouping

F= KL+ I’J+ J’L

HAZARDS

Hazard- free realization

The additional product term, I’L overlapping two groups (group 2 & 3) for hazard
free realization. Group 1 and 2 are already overlapped hence they do not require
additional minterm for grouping.

F= KL+ I’J+ J’L+ I’L

4. Design a hazard-free circuit to implement the following function.

F (A, B, C, D) = ∑m (0, 2, 4, 5, 6, 7, 8, 10, 11, 15).

HAZARDS

Solution:

K-map Implementation and grouping

F= B’D’+ A’B+ ACD

Hazard- free realization

F= B’D’+ A’B+ ACD+ A’C’D’+ BCD+ AB’C

HAZARDS

5. Design a hazard-free circuit to implement the following function.

F (A, B, C, D) = ∑m (0, 1, 5, 6, 7, 9, 11).

Solution

K-map Implementation and grouping

F= AB’D+ A’BC+ A’BD+ A’B’C’

Hazard- free realization:

F= AB’D+ A’BC+ A’BD+ A’B’C’+ A’C’D+ B’C’D

HAZARDS

Hazards in Sequential Circuits

In normal combinational-circuit design associated with synchronous sequential
circuits. Hazards are of no concern, since momentary erroneous signals are not
generally troublesome.

However, if a momentary incorrect signal is fed back in an asynchronous

sequential circuit, It may cause the circuit to go to the wrong stable state. This
situation is illustrated in the following diagram.

If the circuit is in total stable state y x l x2 = 111 and input X2 changes from I to 0,
the next total stable stale should be 110.

However, because of the hazard, output Y may go to 0 momentarily. If this false

signal feeds back into gate 2 before the output of the inverter goes to 1, the output
of gate 2 will remain at 0 and the circuit will switch to the incorrect total stable stale
010. This malfunction can be eliminated by adding an extra gate.

Transition Table Map for Y

HAZARDS

Implementation with SR Latches

Another way to avoid static hazards in asynchronous sequential circuits is 10

implement the circuit with SR latches, A momentary 0 signal applied to the S or R
inputs of a NOR latch will have no effect on the state of the circuit.

Similarly, a momentary 1 signal app lied to the S and R inputs of a NAND latch will
have no effect on the state of the latch. We know that a two-level sum-of-products
expression implemented with NAND gates may have a static 1 hazard if both inputs
of gate 3 go to 1, changing the output from 1 to 0 momentarily. But if gate 3 is part
of a latch, the momentary 1 signal will have no effect on the output, because a third
input to the gate will come from the complemented side of the latch that will be
equal to 0 and thus maintain the output at 1.

To clarify what was just said, consider a NAND SR latch with the following Boolean
functions for S and R:

S = AB + CD

R = A'C

Since this is a NAND latch, we must apply the complemented values to the inputs:

S = (AB + CD)' = (AB)'(CD)'

R = (A'C)'

S is generated with IWO NAND gates and one AND gate. The Boolean function for
output Q is

Q = (Q'S)' = [Q' (AB)'(CD)']'

HAZARDS

This function is generated using the following diagram with two levels of NAND
gates. If output Q is equal to 1. then Q' is equal to O. If two of the three inputs go
momentarily to 1, the NAND gate associated with output Q will remain at 1 because
Q' is maintained at 0.

The following diagram shows a typical circuit that can be used to construct
asynchronous sequential circuits.

The two NAND gates forming the latch normally have two inputs. However, if the
or R functions contain two or more product terms when ex pressed as a sum of
products , then the corresponding NAND gate of the SR latch will have three or
more inputs .

Thus, the two terms in the original sum-of-products expression for S are AD and
CD, and each is implemented with a NAND gate whose output is applied to the input
of the NAND latch. In this way, each slate variable requires a two- level circuit of
NAND gates.
HAZARDS

The first level consists of NAND gates that implement each product term in the
origin al Boolean expression of S and R. The second level forms the cross -coupled
connection of the SR latch with inputs that come from the outputs of each NAND
gate in the first level.

Click Here for Quiz

List of Experiments
1. Design and implement a 4-bit synchronous counter
2. Construct a 4-bit binary ripple counter
3. Write a HDL code to implement a Ripple counter .
Video Links
Sl. Topic Video Link
No.
Asynchronous Sequential https://www.youtube.com/watch?v=xX
1
Circuit L8oYmktqM
Analysis of Synchronous https://www.youtube.com/watch?v=hri
2
Sequential Circuits c4h80PDc
Asynchronous Sequential https://www.youtube.com/watch?v=nsPhv
3 W16lek
Circuits (Part II)
State Assignment in https://www.youtube.com/watch?v=PdY0yD
4 MC2pg
Asynchronous Circuit
Assignment Questions
Assignment
1. An asynchronous sequential circuit is described by the
excitation function
Y = x1x2’+ (x1 + x2’) y
and the output function Z=y (CO4, K6)
(a) Draw the logic diagram of the circuit.
(b) Derive the transition table and output map.
(c) Obtain a two-state flow table.
(d) Describe in words the behavior of the circuit.
2. An asynchronous sequential circuit has two internal states
and one output. The two excitation functions and one
output function describing the circuit are, respectively.
(CO4, K6)
Y1 = x1x2 + x1y2’ + x2’y1
Y2 = x2 + x1y1’y2 + x1’y1
Z = x2 + y1
(a) Draw the logic diagram of the circuit.
(b) Derive the transition table and output map.
(c) Obtain a flow table for the circuit.
 Part A Q & A (with K level and CO)

PART – A

1. What is flow table? (CO4, K1)

During the design of synchronous sequential circuits, it is more convenient to name
the states by letter symbols without making specific reference to their binary values.
Such table is called Flow table.
2. What is primitive flow table? (CO4, K1)
A flow table is called Primitive flow table because it has only one stable state in each
row.
3. Define fundamental mode . (CO4, K1)
Only one input variable can change at any one time and the time between two
inputs changes must be longer than the time it takes the circuit to reach a stable
state.
4. Mention the application areas of asynchronous sequential circuits. (CO4,
K1)
i. Used where speed is important,(i.e.) where the digital system must respond
quickly without the need to wait for clock pulse.
ii. Require only few components (i.e) no need for additional clock pulses.
iii. Used where the input change at any time independent of clock.
iv. Communication between two units where each has own independent clock.

5. Define secondary variables of asynchronous sequential circuits. (CO4,

K1)
The present state and the next state variables in asynchronous sequential circuits
are called Secondary / excitation variables.

6. Mention the excitation function for SR latch using NOR & NAND gates.
(CO4, K1)
Nor gate :Y = S+R‟y When SR = 0
NAND gate :Y = S‟ + Ry

7. What is a flow table & primitive flow table? (CO4, K1)

During the design of asynchronous sequential circuits, it is more convenient to name
the states by letter symbols without making specific reference to their binary values.
Such a table is called a flow table. primitive flow is the flow table that has only one
stable state in each row
 Unit - IV

PART – B

1. Explain Asynchronous Sequential Circuits. (CO4, K1)

2. Explain Fundamental mode and Pulse mode in sequential circuits. (CO4, K1)
3. An asynchronous sequential circuit is described by the following excitation and
output function. (CO4, K6)
B = (A1’ B2) B + (A1+B2)
C=B
1. Draw the logic diagram of the circuit.
2. Derive the transition table and output map.
3. Describe the behavior of the circuit.
4. An asynchronous sequential circuit is described by the following excitation and
output functions (CO4, K6)
Y = x1x2'+(x1 + x2')y
Z=y
1. Draw the logic diagram of the circuit.
2. Derive the transition table and output map.
3. Obtain 2 state flow table.
4. Describe in words the behavior of the circuit.
 Part A Q & A (with K level and CO)
1) Define a Transition Table (CO4, k1)

Transition table is useful to analyze an asynchronous circuit from the circuit diagram „

Procedure to obtain transition table:

1. Determine all feedback loops in the circuits

2. Mark the input (yi ) and output (Yi ) of each feedback loop

3. Derive the Boolean functions of all Y’s

4. Plot each Y function in a map and combine all maps into one table

5. Circle those values of Y in each square that are equal to the value of y in the
same row

2) Define a Flow Table (CO4, k1)

During the design of asynchronous sequential circuits, it is more convenient to

name the states by letter symbols without making specific reference to their
binary values. Such a table is called a flow table.

A flow table is similar to a transition table except that the internal states are
symbolized with letters rather than binary numbers.

The flow table also includes the output values of the circuit for each stable state.

3) What is a primitive flow table? (CO4, k1)

A primitive Flow table contains only one stable state in each row.

(i) Flow table with 4 states and 1 input (ii)Flow table with 2 states, 2 inputs and 1 output
 Part A Q & A (with K level and CO)

4) What is a race condition in asynchronous sequential circuit? (CO4, k1)

A race condition is said to exist in an asynchronous sequential circuit when two or

more binary state variables change value in response to a change in an input
variable.

When unequal delays are encountered, a race condition may cause the state
variables to change in an unpredictable manner.
5) Define a Non critical race. Give example (CO4, k2)

If the final stable state that the circuit reaches does not depend on the order in
which the state variables change, the race is called as Noncritical race.

Example

(a) Possible Transitions (b) Possible Transitions

00 -> 11 00->11-> 01

00 -> 01 -> 11 00->01

00 -> 10 -> 11 00->10->11->01

Final total state y1y2 x =111 Final total state y1y2 x =011

The final stable state does not depend on the change order of state variables
 Part A Q & A (with K level and CO)

6) Define a Critical race. Give example (CO4, k2)

If the circuit ends up in two or more different stable states, depending on the
order in which the state variables change, then it is a Critical race.

Critical races must be avoided to ensure proper operation of the Asynchronous

Sequential Circuit.

Example

In the transition table (a), if Y2 changes to 1 before Y1 because of unequal

propagation delay, then the circuit goes to the total stable state 011 and remains
there.

On the other hand, if Y1 changes first, the internal state becomes 10 and the
circuit will remain in the stable total state 101.

Hence, the race is critical because the circuit goes to different stable states
depending on the order in which the state variables change.

7) Define a cycle in asynchronous sequential circuit (CO4, k1)

Races can be avoided by directing the circuit through intermediate unstable states
with a unique state-variable change. When a circuit goes through a unique
sequence of unstable states, it is said to have a cycle.
REDUCTION OF STATE AND FLOW TABLES

2 marks

Define primitive flow table. [CO4,k1]

It is defined as a flow table which has exactly one stable state for each row in the
table. The design process begins with the construction of primitive flow table.

How to reduce the number of internal states in an asynchronous

sequential circuit?[CO4,k2]

• Implication Table

• Merging of the Flow Table

• Maximal Compatibles

• Closed Covering

What are the steps for the design of asynchronous sequential

circuit?[CO4,k2]

Construction of primitive flow table -reduction of flow table State assignment is

made -realization of primitive flow table

Define compatibility. [CO4,k1]

States Si and Sj said to be compatible states, if and only if for every input sequence
that affects the two states, the same output sequence, occurs whenever both
outputs are specified and regardless of whether Si on Sj is the initial state.

Define closed covering. [CO4,k1]

A Set of compatibles is said to be closed if, for every compatible contained in the
set, all its implied compatibles are also contained in the set. A closed set of
compatibles, which contains all the states of M, is called a closed covering.
REDUCTION OF STATE AND FLOW TABLES

Define state table. [CO4,k1]

For the design of sequential counters we have to relate present states and next
states. The table, which represents the relationship between present states and next
states, is called state table.
Give the comparison between state Assignment Synchronous circuit and
state assignment asynchronous circuit. [CO4,k2]
In synchronous circuit, the state assignments are made with the objective of circuit
reduction. In asynchronous circuits, the objective of state assignment is to avoid
critical races.
What are races? [CO4,k1]
When 2 or more binary state variables change their value in response to a change in
an input variable, race condition occurs in an asynchronous sequential circuit. In
case of unequal delays, a race condition may cause the state variables to change in
an unpredictable manner.
Define non critical race. [CO4,k1]
If the final stable state that the circuit reaches does not depend on the order in
which the state variable changes, the race condition is not harmful and it is called a
non critical race.
Define critical race.[CO4,k1]
If the final stable state depends on the order in which the state variable changes,
the race condition is harmful and it is called a critical race.
What is a cycle? [CO4,k1]
A cycle occurs when an asynchronous circuit makes a transition through a series of
unstable states. If a cycle does not contain a stable state, the circuit will go from
one unstable to stable to another, until the inputs are changed.

List the different techniques used for state assignment. [CO4,k1]

1. Shared row state assignment

2. One hot state assignment

 Part A Q & A (with K level and CO)

1) Define Flow Table. (CO4, k1)

During the design of asynchronous sequential circuits, it is more convenient to name the
states by letter symbols without making specific reference to their binary values. Such a
table is called a flow table. A flow table is similar to a transition table except that the internal
states are symbolized with letters rather than binary numbers. The flow table also includes
the output values of the circuit for each stable state.

2) Define primitive flow table. (CO4, k1)

Primitive flow table is a flow table which has exactly one stable state for each row in the
table. A primitive flow table is obtained from the design specifications.

3) Define Transition Table. (CO4, k1)

The transition table is obtained from the maps by combining the binary values in
corresponding squares of the reduced flow table. The entries in the transition table where Y
= y are circled to indicate a stable condition. An un-circled entry represents an unstable
state.

4) What is Implication Table? (CO4, k1)

The implication table is a chart that consists of squares, one for every possible pair of
states, that provide spaces for listing any possible implied states. Through implication table,
it is possible to determine all pairs of equivalent states.

5) What is Merger diagram? What is the use of it? (CO4, k1)

The merger diagram is a graph in which each state is represented by a dot placed along the
circumference of a circle. Lines are drawn between any two corresponding dots that form a
compatible pair. All possible compatibles can be obtained from the merger diagram by
observing the geometrical patterns in which states are connected to each other. An isolated
dot represents a state that is not compatible to any other state. A line represents a
compatible pair. A triangle constitutes a compatible with three states.
 Part A Q & A (with K level and CO)

6) What is meant be Closed covering (CO4, k1)

The condition that must be satisfied for row merging is that the set of chosen
compatibles must cover all the states and must be closed. The set will
cover all the states if it includes all the states of the original state table.
A closed set of compatibles that covers all the states is called a closed
covering.

7) Define stable state. (CO4, k1)

For a given values of input variables, the system is stable if the circuit reaches a
steady state condition with yi = Yi , where yi is present state and Yi is
the next state.

8) What are the steps needed to design an asynchronous circuit.

(CO4,K1)

Design Procedure:
• Draw the flow diagram or State Diagram from the given design
specifications.
•Obtain a primitive flow table from the given design specifications and
specify the outputs associated with the stable states.
•Reduce the flow table by merging rows in the primitive flow table.
•Assign binary state variables to each row of the reduced flow table to
obtain the transition table. The procedure of state assignment
eliminates any possible critical races.
•Assign output values to the dashes associated with the unstable states
to obtain the output maps.
•Simplify the Boolean functions of the excitation and output variables
and draw the logic diagram.
HAZARDS-PART-A QUESTIONS AND ANSWERS

1. What are hazards?

Hazards are unwanted switching transients that may appear at the output of a
circuit because different paths exhibit different propagation delays.
2. What are the types of hazards?
The 3 types of hazards are
a) Static hazards
Static – 0 hazards
Static – 1 hazard
b) Dynamic hazards.
3. How does an essential hazard occur?
An essential hazard occurs due to unequal delays along two or more paths that
originate from the same input. An excessive delay through an inverter circuit in
comparison to the delay associated with the feedback path causes essential
hazard.
4. Define Static 0-Hazard and Static 1-Hazard
In a combinational circuit, If the output goes momentarily 1 when it should
remain a 0, the hazard is known as static-0 hazard.

In a combinational circuit, if output goes momentarily 0 when it should remain

a1, the hazard is known as static-1 hazard.
HAZARDS-PART-A QUESTIONS AND ANSWERS

5. Define Dynamic Hazard

When the output changes three or more times when it should change from 1 to
0 or from 0 to 1 is known as dynamic hazard.

6. What are the hazards in combinational circuits?

The unwanted switching transients that may appear at the output of a circuit
are called hazards. The hazards cause the circuit to malfunction. The main
cause of hazards is the different propagation delays at different paths. Hazards
occur in the combinational circuits, where they may cause a temporary false
output value. When such combinational circuits are used in the asynchronous
sequential circuits, they may result in a transition to a wrong stable state.

7. How can the hazards in combinational circuit be removed?

Hazards in the combinational circuits can be removed by covering any two min
terms that may produce a hazard with a product term common to both. The
removal of hazards requires the addition of redundant gates to the circuit.
8. Does Hazard occur in sequential circuit? If so what is the problem caused?
Yes, Hazards occur in sequential circuit that is Asynchronous sequential circuit.
It may result in a transition to a wrong state.
Part B Questions
1) Explain in detail about cycles, critical and non critical race conditions with
suitable examples. (CO4, K2)

2) Explain the procedure to obtain transition table and flow table with suitable
example. (CO4, K2)

3) Write in detail about the procedure for analyzing an asynchronous sequential

circuit with SR latch. (CO4, K2)

4) Design a asynchronous sequential circuit with two inputs X and Y and with one
output Z. Whenever Y is one, input X is transferred to Z. When Y is zero, the
output does not change for any change in X. [CO4,k3]

5) Write short notes on shared row state assignment with an example.(7)

[CO4,k2]
6) Discuss a method used for race free assignments with example.(6) [CO4,k2]

7) Describe with reasons the effect of races in asynchronous sequential circuit

design. Explain its type with illustrations. Show the method of race – free state
assignments with examples. (13)[CO4,k2]

8) Design an asynchronous sequential circuit that has 2 inputs x2 and x1, and one
output z. the output is to remain 0 as long as an X1 is 0. The first change in x2
that occurs while x1 is 1 will cause z to be 1. Z is to remain 1 until x1 returns to
0. Construct a state diagram and flow table. Determine the output equations.
(13) [CO4,k3]

9) Design a circuit with inputs A and B to give an output z=1 when AB=11 but
only if A becomes 1 before B, by drawing total state diagram, primitive flow
table and output map in which transient state is included. (13)[CO4,k3]
REDUCTION OF STATE AND FLOW TABLES

Part B

10) Obtain the primitive flow table for an asynchronous circuit that has 2 input’s x, y
and output z. an output z=1, is to occur only during the input state xy=01 and then
if and only if the input state xy=01 is preceded by the input sequence xy=01, 00,
10, 00, 10, 00 (13) [CO4,k3]

11) Design a circuit with input a and b to give an output z=1 when AB =11 but only
if A becomes 1 before B, by drawing total state diagram, primitive flow table and
output map in which transient state is included. (13)[CO4,k3]

12) Design an asynchronous sequential circuit that has two inputs and and one
output Z. When , the output Z is 0.The first change in that occurs while is 1 will
cause output Z to be 1. The output Z will remain 1 until returns to 0.(15)[CO4,k3]
 Part B Q & A (with K level and CO)

13. Design a negative-edge triggered T flip-flop. The circuit has two inputs,
T (toggle) and C (clock), and one output, Q. the output state is
complemented if T= 1 and the clock changes from 1 to 0 (negative-
edge triggering). Otherwise, under any other input condition, the
output Q remains unchanged. (CO4,K5)

14. Design a gated latch circuit with two inputs, G (gate) and D (data), and
one output, Q. Binary information present at the D input is transferred
to the Q output when G is equal to I. The Q output will follow the D
input as long as G = I. When G goes to 0, the information that was
present at the D input at the time the transition occurred is retained at
the Q output. The gated latch is a memory element that accepts the
value of D when G = I and retains this value after G goes to O. Once G
= 0, a change in D does not change the value of the output Q.
(CO4,K5)

15. Design an asynchronous sequential circuit that has two inputs X2 and
X1 and one output Z. When X1= 0, the output Z is 0. The first change
in X2 that occurs while X1 is 1 will cause output Z to be 1. The output
Z will remain 1 until X1 returns to 0. (CO4,K5)
 Part B Q & A (with K level and CO)

16. Design an asynchronous sequential circuit with two inputs X and Y and
one output Z. Whenever Y is 1, input X is transferred to Z. Whenever Y
is 0, output does not change for any change in X. .
(CO4,K5)

17. Develop a primitive flow table for a circuit with two inputs, x1 and x2,
and two outputs, z1 and z2, that satisfy the following four conditions:

(CO4,K3)

(a)When x1 x2 = 00, the output is z1 z2 = 00.

(b)When x1 = 1 and x2 changes from a to 1, the output is z1 z2 = 01.

(c) When x2 = 1 and x1 changes from a to 1, the output is z1 z2 = 10.

(d) Otherwise, the output does not change.

HAZARDS-PART-B QUESTIONS
1. Explain the hazards in combinational and sequential logic circuit with suitable
examples.
2. Give hazard – free realization for the following Boolean function
f (A, B, C, D) = Σm(0, 2, 6, 7, 8, 10, 12)
3. Implement the switching function F=Σm(1,3,5,7,8,9,14,15) by a static hazard
free two level AND-OR gate network
4. What are Essential hazards and find a Static and Dynamic free realization for
the following function using NAND and NOR gates. F(a,b,c,d)= Σm(1,5,7,14,15)
5. What is a Hazard? Explain the types? Check whether the following circuit
contains a hazard or not Y = x1x2 + x2′x3. If the hazard is present, demonstrate
its removal.
6. Discuss about static, dynamic and essential hazards in asynchronous sequential
circuits

7. Design a hazard-free circuit to implement the following function.

F (A, B, C, D) = ∑m (1, 3, 6, 7, 13, 15)

8. Design a hazard-free circuit to implement the following function.

F (A, B, C, D) = ∑m (0, 2, 6, 7, 8, 10, 12).

9. Design a hazard-free circuit to implement the following function.

F (I, J, K, L) = ∑m (1, 3, 4, 5, 6, 7, 9, 11, 15).

10. Design a hazard-free circuit to implement the following function.

F (A, B, C, D) = ∑m (0, 2, 4, 5, 6, 7, 8, 10, 11, 15).

11. Design a hazard-free circuit to implement the following function.

F (A, B, C, D) = ∑m (0, 1, 5, 6, 7, 9, 11).
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Real time Applications

ARTS (Asynchronous Logic in Real-

Time Systems)
The aim of the ARTS (Asynchronous Logic in Real-Time Systems)
research project is to investigate the temporal predictability and
stability of asynchronous (QDI, quasi delay insensitive) hardware
designs. More specifically, we want to compile models for the timing
uncertainties of hardware execution times and extend these to make
quantitative statements on the timing behavior of self-timed circuits.
Our hope is that the theoretical and experimental analyses will also
provide indications for improving the temporal stability of self-timed
circuits.
The central concern for the project is the predictability of
asynchronous logic with respect to its temporal properties.
Content Beyond Syllabus
 Design at the Register Transfer Level
A digital system is represented at the register transfer level (RTL) when it is
specified by the following three components:

1. The set of registers in the system.

2. The operations that are performed on the data stored in the registers.

3. The control that supervises the sequence of operations in the system.

A register is a connected group of flip‐flops that stores binary information and has
the capability of performing one or more elementary operations. A register can load
new information or shift the information to the right or the left. A counter is a
register that increments a number by a fixed value (e.g., 1). A flip‐flop is a one‐bit
register that can be set, cleared, or complemented. In fact, the flip‐flops and
associated gates of any sequential circuit can be called registers by this definition.

The operations executed on the information stored in registers are elementary

operations that are performed in parallel on the bits of a data word during one clock
cycle. The data produced by the operation may replace the binary information that
was in the register before the operation executed. Alternatively, the result may be
transferred to another register (i.e., an operation on a register may leave its
contents unchanged).
Prescribed Text Books & Reference
TEXT BOOK:
M. Morris R. Mano, Michael D. Ciletti, “Digital Design: With an Introduction to the Verilog
HDL, VHDL, and System Verilog” , 6th Edition, Pearson Education, 2017.
REFERENCES:
1. G. K. Kharate, Digital Electronics, Oxford University Press, 2010
2. John F. Wakerly, Digital Design Principles and Practices, Fifth Edition, Pearson Education,
2017.
3. Charles H. Roth Jr, Larry L. Kinney, Fundamentals of Logic Design, Sixth Edition, CENGAGE
Learning, 2013
4. Donald D. Givone, Digital Principles and Design‖, Tata Mc Graw Hill, 2003.
Mini Project Suggestions
LAMP HANDBALL

In this experiment, you will construct an electronic game of handball,

using a single light to simulate the moving ball. The experiment
demonstrates the application of a bidirectional shift register with
parallel load. It also shows the operation of the asynchronous inputs
of flip‐flops. We will first introduce an IC that is needed for the
experiment and then present the logic diagram of the simulated lamp
handball game.
 Thank you

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