UNIT IV

Asynchronous Circuits
In synchronous sequential circuits, memory elements are clocked flip-flops. In
asynchronous sequential circuits, memory elements are either unclocked flip-
flops or time delay elements. Therefore, in asynchronous sequential circuits
change in input signals can affect memory element at any instant of time. In
synchronous circuits, the designer has to consider the time delays involved to
determine the maximum operating speed of the clock. In asynchronous circuits,
clock is absent and state change occurs according to delay times of the logic.
Due to this, asynchronous circuits are more difficult to design. However,
because of absence of clock, asynchronous circuits are faster than synchronous
circuits.

Types of Asynchronous Circuits

Block diagram of an asynchronous sequential circuit. It consists of a
combinational circuit and delay elements connected to form feedback loops. As
shown in the Fig. there are n input variables, m output variables, and k internal
states. The delay elements provide a short term memory for the sequential
circuit. The present state and next state variables in asynchronous sequential
circuits are called secondary variables and excitation variables, respectively.
 When an input variable changes in value, the secondary variables, i.e. y 1 y2, …
yr do not change instantaneously. Certain amount of time is required for the
input signal to propagate from the input terminals through the combinational
circuit and the delay elements. The combinational circuit generates Y excitation
variables which gives the next state of the circuit. The excitation variables are
propagated through delay elements to become the new present state for the
secondary variables, i.e. y1 y2, … yr In the steady state condition excitation and
secondary variables are same, but during transition they are different. In other
words we can say that, for a given value of input variables, the system is stable
if the circuit reaches a steady state condition with y i = Yi. for i = 1,2,-”,r;
otherwise the circuit is in a continuous transition and is said to be unstable.

• To ensure proper operation, it is necessary for asynchronous sequential circuit

to attain a stable state before the input is changed to a new value. Because of
unequal delays in the wires and gate circuits, it is impossible to have two or
more input variables change at exactly same instant. Therefore, simultaneous
changes of two or more input variables are usually avoided. In other words, we
can say that only one input variable is allowed to change at any one time and the
time between two input changes is kept longer than the time it takes the circuit
to reach a stable state.

• According to how input variables are to be considered, there are two types of
asynchronous circuits :

* Fundamental mode circuits and

* Pulse mode circuits.

Fundamental mode circuit

It assumes that :

• Input changes should be spaced in time by at least At, the time needed for the
circuit to settle into a stable state following an input change. That is, the input
variables should change only when the circuit is stable.

• Only one input variable can change at a given instant of time and

• Inputs are levels and not pulses.

• Delay lines are used as memory elements.

Pulse mode circuit

It assumes that :

• The input variables are pulses instead of levels.

• The width of the pulses is long enough for the circuit to respond to the input.

• The pulse width must not be so long that it is still present after the new state is
reached.

• Pulses should not occur simultaneously on two or more input lines.

• Flip-flops are commonly used as a memory elements.

• Memory element transitions are initiated only by input pulses.

• Input variables are used only in the uncomplemented or the complemented

forms, but not both.

Analyse the given pulsed asynchronous sequential circuit

Sol. :

Step 1 : Determine the circuit excitation and output equations.

For given circuit excitation and output equations are :

Step 2 : Determine the next state equation of state variable.

The characteristic equation for SR flip-flop is

Using the characteristic equation and excitation equations we have the state
variable next state equation is as follows :

Step 3 : Construct the state variable transition table.

From next state and output equations we can construct the state variable
transition table indicating state variables, input variables, next state values and
the output value.

Step 4: Derive the flow table and state diagram.

From the state variable transition table we can derive the flow table and from
flow table we can derive the state diagram as shown in the Fig. 7.3.3. The flow
diagram can be constructed by replacing next state and state variable values by
actual states S1 = 0 and S1 = 1.

Step 5 : Draw the timing diagram.

The Fig. 7.3.4 shows the timing diagram for the pulse mode circuit shown in the
Fig. 7.3.1. As shown in the timing diagram, the inputs are the pulses and they
occur one at a time.
Ex. 7.3.2 Consider the asynchronous sequential circuit which is driven by the
pulses, as shown in the Fig. 7.3.5. Analyze the circuit.

Sol. : The circuit has two NAND gate latches that generate the state variables, A
and B. The circuit has four input variables W, X, Y and Z and one output
variable C.

Step 1 : Determine the circuit excitation and output equations.

From the given sequential circuit we can have excitation and output equations
as follows :

Step 2 : Determine next state equations for state variables.

The characteristic equation for SR flip-flop is

Using the characteristic equation and excitation equations we have the state
variable next-state equations as follows

Step 3 : Construct the state variable transition table. From these next state and
output equations we can construct the state variable transition table indicating
state variables, input variables, next state values and the output-state.

Step 4: Derive the flow table and state diagram.

From the state variable transition table we can derive the flow table and from
flow table we can derive the state diagram as shown in the Fig. 7.3.5 (b) and (c).
The flow diagram can be constructed by replacing next state and state variable
values by actual states

(S0 = 00, S1 = 01, S2 = 11 and S3 = 10).

Design of Pulse Mode Circuit
When designing pulse-mode circuits, remember that no clock pulse is present,
inputs occur on only one line at a time and only uncomplemented forms of input
signals may be used.

The absence of a clock pulse indicates that latch or flip-flop triggering must be
accomplished by utilizing the pulses on the input signals and therefore all circuit
timing information must be obtained from the input pulses. Hence, the input
pulses not only provide input information but also assume the functions
performed by the clock pulse in synchronous circuits.

The steps involved in the design of pulse-mode asynchronous sequential circuits

are :

1. Define states and draw a state diagram and/or state table of the circuit.

2. Minimize the state table.

3. Do state assignment.

4. Choose the type of latch or flip-flop to be used and determine excitation

equations.

5. Construct excitation table for the circuit.

6. Determine the output equation and the flip-flop input equations using k-map
simplification.

7. Draw the logic diagram.

Ex. 7.4.1 Design a pulse-mode circuit having two input lines, x1 and x2 and
one output line, z, as shown in Fig. 7.4.1. The circuit should produce an
output pulse to coincide with the last input pulse in the sequence x 1 - x2 - x2.
No other input sequence should produce an output pulse.
Sol . :

Step 1 : Define states and draw the state diagram and/or state table of the circuit
: S0 : indicates that the last input was x1

S1 : indicates that the sequence x1 – x2 occurred.

S2 : indicates that the sequence x1 – x2- x2 occurred.

The Fig. 7.4.1 (a) shows the state diagram for the given circuit. It is important to
note that the format of the state diagram is similar to that used for synchronous
circuits. However, the transitions are labeled with the input variable and the
output value rather than with both input and output values.

Also, remember that the state transitions are triggered by the occurrence of the
indicated input pulse and not by a clock pulse.
The state table corresponding to the state diagram of Fig. 7.4.1 (a) is as follows :

Step 2 : Minimize state table : State table is minimum.

Step 3 : Assign states : A state assignment of S0 = 00, S1 = 01 and S2 = 10.

Step 4 : Flip-flops to be used : T

Note : For T flip-flop output changes when T = 1.

Step 5 : Construct execution table for the circuit.

Step 6 : K-map simplification for T inputs and Z output.

Note : Only vertical grouping is allowed.

Step 7 : Draw the logic diagram.

In the previous example, the circuit realization took the form of a Mealy-type
circuit since the output was a function of both an input and a state variable. A
next example, will now be presented that describes the realization of a Moore-
type circuit. Recall that Mealy and Moore-type circuits were defined in Chapter
4.
Consider the following asynchronous sequential circuit and draw maps,
transition table and state table.

Sol. : Considering the excitation variables as outputs and the secondary

variables as inputs we have,
Example for Practice

Ex. 7.5.6 Analyse the fundamental mode asynchronous sequential circuit

shown in Fig. 7.5.10.

Hazards
• The unwanted switching transients (glitches) that may appear at the output of a
circuit are called Hazards. The hazards cause the circuit to malfunction. The
main cause of hazards is the different propagation delays at different paths.
Hazards occur in the combinational circuits, where they may cause a temporary
false output value. When such combinational circuits are used in the
asynchronous sequential circuits, they may result in a transition to a wrong
stable state.

• There are two types of hazards : Static hazards and dynamic hazards. A static
hazard exists if a signal is supposed to remain at particular logic value when an
input variable changes its value, but instead the signal undergoes a momentary
change in its required value. According to definition, the static hazards are
further classified as static-0 hazard and static-1 hazard.

In a combinational circuit, if output goes momentarily 0 when it should remain

a 1, the hazard is known as static-1 hazard. On the other hand, if output goes
momentarily 1 when it should remain a 0, the hazard is known as static-0
hazard. Another type of hazard is dynamic hazard in which output changes three
or more times when it should change from 1 to 0 or from 0 to 1. The Fig. 8.1.1
shows the three types of hazards.

• The Fig. 8.1.2 shows circuit with hazards. Assume that, initially, inputs x 1 ,
x2 and x3 = 0. This causes the output of gate 1 to be 1, that of gate 2 to be 0, and
the output of the circuit to be equal to 0. Now consider change in x 2 from 0 to 1.
The output of gate 1 changes to 0 and that of gate 2 changes to 1, leaving the
output at 0. However, the output momentarily goes to 1 if the propagation delay
through the inverter is taken into consideration. The delay in the inverter causes
the output of gate 2 to change to 1 before the output of gate 1 changes to 0. In
this situation, both inputs of gate 3 are momentarily equal to 1, causing the
output to go to 1 for the short time equal to the propagation delay of the
inverter. This is illustrated in the Fig. 8.1.3.
1. Eliminating a Hazard
• The hazard exists because of the change of input results in a different product
terms covering two minterms or different sum terms covering two maxterms.
Whenever the circuit move from one product term to another or move one sum
term to another, there is a possibility of a momentary interval when neither term
is equal to 1, giving rise to an undesirable 0 output. Hazards can be eliminated
by enclosing two minterms or maxterms in question. For example, if the circuit

has minterms , then these two minterms must be enclosed by

introducing another minterm x^. This is illustrated in Fig. 8.1.4.
Ex. 8.1.1 Find a way to remove the hazard in product of sums expression
given by

AU : Dec.-12, Marks 4

Sol. :

Thus, we can eliminate hazard by adding one more OR gate as shown in Fig.
8.1.6.
Ex. 8.1.2 Give hazard-free realisation for the following Boolean function,

f (A, B,C,D) = ^m (0, 2, 6, 7, 8, 10, 12)

Sol. : The given function can be implemented using K-map as shown in the Fig.
8.1.7 and Fig. 8.1.8 shows the additional product term, D overlapping
two groups (group 1 and group 2) for hazard free realization. Group 1 and group
3 are already overlapped hence they do not require additional minterm for
grouping.
PROM (Programmable Read Only Memory)
• The Fig. 9.2.1 shows the block diagram of PROM. It consists of n-input lines
and m-output lines. Each bit combination of the input variables is called an
address. Each bit combination that comes out of the output lines is called a
word. The number of bits per word is equal to the number of output lines, m.
The address specified in binary number denotes one of the minterms of n
variables. The number of distinct addresses possible with n-input variables is
2n. An output word can be selected by a unique address and since there are 2n
distinct addresses in PROM, there are 2n distinct words in the PROM. The word
available on the output lines at any given time depends on the address value
applied to the input lines.

• Let us consider 64 × 4 PROM. The PROM consists of 64 words of 4-bits each.

This means that there are four output lines and particular word from 64 words
presently available on the output lines is determined from the six input lines.
There are only six inputs in a 64 × 4 PROM because 26 = 64 and with six
variables, we can specify 64 addresses or minterms. For each address input,
there is a unique selected word. Thus, if the input address is 000000, word
number 0 is selected and applied to the output lines. If the input address is
111111, word number 63 is selected and applied to the output lines.

• The Fig. 9.2.2 shows the internal logic construction of a 64 × 4 PROM. The
six input variables are decoded in 64 lines by means of 64 AND gates and 6
inverters. Each output of the decoder represents one of the minterms of a
function of six variables. The 64 outputs of the decoder are connected through
fuses to each OR gate. Only four of these fuses are shown in the diagram, but
actually each OR gate has 64 inputs and each input goes through a fuse that can
be blown as desired.
• The PROM is a two level implementation in sum of minterms form. Let us see
AND-OR and AND-OR-INVERTER implementation of PROM. Fig. 9.2.3
shows the 4 × 2 PROM with AND-OR and AND-OR-INVERTER
implementations.
1. AND Matrix
• The Fig. 9.2.4 shows the AND matrix. It is used to form product terms. It has
m AND gates with 2n-inputs and m-outputs, one for each AND gate. The Fig.
9.2.4 shows the AND gates formed by diodes and resistors structure. Each AND
gate has all the input variables in complemented and uncomplemented form.
There is a nichrome fuse link in series with each diode which can be bum out to
disconnect particular input for that AND gate. Before programming, all fuse
links are intact and the product term for each AND gate is given by
• The Fig. 9.2.5 shows the simplified and equivalent representation of input
connections for one AND gate. The array logic symbol shown in Fig. 9.2.5 (b)
uses a single horizontal line connected to the gate input and multiple vertical
lines to indicate the individual inputs. Each intersection between horizontal line
and vertical line indicates the fuse connection.
• The Fig. 9.2.6 shows the simplified representation of AND matrix with input
buffer.
2. OR Matrix
• The OR matrix is provided to produce the logical sum of the product term
outputs of the AND matrix. The Fig. 9.2.7 shows the OR gates formed by
diodes and resistors structure. Each OR gate has all the product terms as input
variables. There is a nichrome fuse link in series with each diode which can be
bum out to disconnect particular product term for that OR gate. Before
programming, all fuse link in OR matrix are also intact and the sum term for
each OR gate is given by,

• The Fig. 9.2.8 shows the simplified and equivalent representation of input
connections for one OR gate.
• The Fig. 9.2.9 shows the simplified representation of OR matrix.

3. Invert / Non-invert Matrix

• Invert/Non-invert matrix provides output in the complement or
uncomplemented form. The user can program the output in either complement
or uncomplement form as per design requirements. The typical circuits for
invert/non-invert matrix

is as shown in Fig. 9.2.10. In both the cases if fuse is intact the output is in its
uncomplemented form; otherwise output is in the complemented form.
4. Combinational Logic Implementation using PROM
• Looking at the logic diagram of the PROM, we can realize that each output
provides the sum of all the minterms of n-input variables. We know that any
Boolean function can be expressed in sum of minterms form. By breaking the
links of those minterms not included in the function, each PROM output can be
made to represent the Boolean function of one of the output variables in the
combinational circuit. For an n-input, m-output combinational circuit, we need a
2n × m PROM.

Ex. 9.2.1 Using PROM realize the following expressions.

F1 (a, b, c) = ∑ m (0, 1, 3, 5, 7)

F2 (a, b, c) = ∑ m (1, 2, 5, 6)

Sol. : The given functions have three inputs. They generate 2 3 = 8 minterms and
since there are two functions, there are two outputs. The functions can be
realized as shown in Fig. 9.2.11.
The Fig. 9.2.12 shows the block diagram and truth table of PROM.
Ex. 9.2.2 Design a combinational using a PROM. The circuit accepts 3-bit
binary number and generates its equivalent Excess-3 code.

Sol. : Let us derive the truth table for the given combination circuit. Table 9.2.1
shows the truth table.
• In practice when we are designing combinational circuits with PROM, it is not
necessary to show the internal gate connections of fuses inside the unit, as
shown in the Fig. 9.2.13.
This was shown for demonstration purpose only. The designer has to only
specify the PROM (inputs and outputs) and its truth table, as shown in the Fig.
9.2.14.