Academic Year (AY): 2024-25 (Jan.
-Jun)
Question Bank
Subject- Digital Electronics
Programme: B.Tech. (EEE), Semester-4th
1. (i) State De-Morgan’s theorem.
(ii) Implement NOT, AND, OR, XOR and XNOR gates using NAND
gates.
(iii) Implement NOT, AND, OR, XOR and XNOR gates using NOR
gates.
(iv) Convert (115)10 and (235)10 into hexadecimal numbers.
(v) Simplify the following Boolean expression into one literal.
W’X (Z’+YZ) + X (W+Y’Z).
2. 1. Evaluate 1’s Complement of binary number
a. 1000101
b. 11001100
c. 10101010
d. 10000000
3. (i) Express the function Y = A + B’C in canonical POS.
(ii) Define POS
(iii) What do you mean by SOP
(iv) Illustrate the don’t care condition in logic circuit
(v) Enlist the advantage of digital electronics.
4. Distinguish between combinational logic and sequential logic.
5. (i) 1. What is meant by combinational circuits?
(ii) Define the MUX.
(iii) Enlist the application of Decoder.
(iv) Illustrate the logic diagram.
(v) What is BCD code.
6. Design and explain Half adder and half subtractor
7. (i) Define the excitation table.
(ii) Differentiate between level triggering and edge triggering.
(iii) What is flip flop.
(iv) What do you mean by race out condition in Flip Flop.
(v) Define the propagation time of flip Flop.
8. Differentiate between latch and flip-flop.
9. (i) Enlist the type of digital converter.
(ii) Define the analog converter.
(iii) What do you mean by PLA.
(iv) Differentiate between RAM and ROM.
(v) What is digital converter.
10. Compare Complex Programmable Logic Devices (CPLD) and Field
Programmable Gate Arrays (FPGA).
11. Draw the logic diagram and explain the working of dual slope
ADC.
12. Explain the working principle of successive approximation type
A/D converter.
13. How does the architecture of a PLA differ from a PROM? (or) What
is programmable logic array? How it differs from ROM?
14. A 5-bit DAC has a current output. For a digital input of 101000, an
output current of 10mA is produced. What will IOUT be for a
digital input of 11101?
15. 1. Implement the following function using PLA.
F1(X,Y,Z)= ∑m(1,2,4,6)
F2(X,Y,Z)= ∑m(0,1,2,6,7)
F3(X,Y,Z)= ∑m(2,6)
16. Implement the functions using PAL
W=∑m(2,12,13),
X=∑m(7,8,9,10,11,12,13,14,15),
Y= ∑m(0,2,3,4,5,6,7,8,10,11,15),
Z= ∑m(1,2,8,12,13)
17. Give the excitation table of below flip flops:
(i) SR flip flop (ii) JK flip flop (iii) D flip flop (iv) T flip flop
18. Illustrate the logic diagram for SR, JK, D&T flip flops. Explain
their working
19. With reference to a JK flip-flop, what is racing?
20. Explain the working of the following i) J-K flip-flop ii) S- R flip-
flop iii) D flip-flop
21. Design a mod-6 synchronous counter using JK flip flops.
22. Design a 3-bit synchronous up counter using T flip flops.
23. Design a 4:1 Multiplexer.
24. Sketch the logic diagram of 2 to 4 decoder and explain.
25. Design a BCD to excess-3 code converter
26. Construct a 4-bit parallel adder/subtractor circuit using Full adders
and XOR gates.
27. (i) Design OR and AND function using 2:1 MUX
(ii) Construct 4x16 decoder with two 3x8 decoders.
28. Implement the function using multiplexer F = ∑(0,1,3,4,8,9,15)
