University of Babylon

College of Engineering
Department of Biomedical Engineering

DIGITAL ELECTRONICS II

Fourth Year / Second Semester

Prepared by :

Prof. Dr. Mahmoud Shaker Nasr

Academic year 2020/2021

 DIGITAL ELECTRONICS II
Course Syllabus:
Latches and flip flops, S-R FF, D FF, J-K FF, and T ff, applications; counters, asynchronous
counters (ripple counters), up-down counters, synchronous counters, synchronous counters design,
up- down counters, mod-counters, applications, registers, shift registers, serial in/serial out, serial
in/ parallel out, parallel in/ parallel out, parallel in/ serial out, ring counter, Johnson counters,
applications, square wave generators, one shot, A/D and D/A, memory types, RAM, ROM, flash
RAM.

Books:
Text Book:
1. Thomas L. Floyd "Digital Fundamentals" , Eleventh Edition Global, Edition
2015.
2. M. Morris Mano, "Digital Design", 2015.

References:
1. David Money and Harris' Sarah L. Harris "In Praise of Digital Design and
Computer Architecture", British Library Cataloguing-in-Publication Data,
2013.
2. U.A. Bakshi and A.P Godse, "Analog and digital electronics", technical
publications pune, first edition, 2009.

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 CHAPTER One

Latches and Flp-Flops

Main head lines:

1.1 Difference between combinational and sequential circuits.
1.2 Latches
1.2.1. S-R Latch.
1.2.4. Gated R-S Latch.
1.2.5. Gated D Latch
1.3 Flip-Flops
1.3.1. D Flip Flop.
1.3.2. J-K Flip Flip.
1.3.3. . Master-Slave J-K Flip Flop.
1.4. Edge – Triggered operation.
1.5. Asynchronous Preset and Clear inputs.
1.6. T- Flip Flop.
1.7. Flip Flops applications : Frequency division, counting.
1.8. The 555 timer as oscillator and Astable Multivibrator.

1.1 Difference between combinational and sequential circuits.

Combinational circuits are a basic collection of logic gates. Their outputs

depend only on the current inputs. Combinational circuits are also time-independent.
Along with the absence of concepts like past inputs, combinational circuits also do
not require any clocks. The result of these properties is a simple circuit capable of
implementing complex logic using only logic gates.

Sequential circuits are a collection of memory elements. These memory elements

are flip-flops. These circuits are capable of “remembering” data. Hence, a sequential
circuit’s output depends on the current input, as well as past input.

Combinational Circuit is the type of circuit in which output is independent of time

and only relies on the input present at that particular instant. On other
hand Sequential circuit is the type of circuit where output not only relies on the
current input but also depends on the previous output (memory).
Table 1.1 list the points of comparison between the combinational and sequential
circuits.

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 Table (1.1) Comparison between Combinational and Sequential circuits.

Combinational Logic Circuits Sequential Logic Circuits

Output depends on current, past as well
Output depends only on current inputs
as clock inputs
Hence they are faster They are slower
They are time-independent and don’t need
Time-dependent and thus require clocks
clock inputs
Since there is no clock, they don’t require Since a clock is present, triggering is
triggering required
Made using logic gates Made using flip-flops
Also, easier to design since there are no
More complicated to design
crazy feedbacks or clocks
They can’t store anything. They have no
They have memory
memory.
Main uses are to implement arithmetic and The main use is for storing data and other
logical operations. memory applications
Easier to use and handle Harder to use and handle
Example: Full Adder, Multiplier etc. Example: Counters, Shift-registers

1.2. Latches
The latch is a type of temporary storage device that has two stable states (bistable)
and is normally placed in a category separate from that of flip-flops. Latches are
similar to flip-flops because they are bistable devices that can reside in either of two
states using a feedback arrangement, in which the outputs are connected back to the
opposite inputs. The main difference between latches and flip-flops is in the method
used for changing their state.

Latch is an electronic device that can be used to store one bit of

information.

1.2.1. The S-R (SET-RESET) Latch

A latch is a type of bistable logic device or multivibrator. An active-HIGH input S-
R (SET-RESET) latch is formed with two cross-coupled NOR gates, as shown in
Figure 1.1-(a); an active-LOW input 𝑆 − 𝑅 latch is formed with two cross-coupled
NAND gates, as shown in Figure 1–1(b). Notice that the output of each gate is
connected to an input of the opposite gate. This produces the regenerative feedback
that is characteristic of all latches and flip-flops.

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 Figure (1.1) R-S latch circuit

To explain the operation of the latch, we will use the NAND gate 𝑆 − 𝑅 latch in
Figure 1(b). This latch is redrawn in Figure 2 with the negative-OR equivalent
symbols used for the NAND gates. This is done because LOWs on the 𝑆𝑎𝑛𝑑 𝑅 lines
are the activating inputs.
The latch in Figure 2 has two inputs, 𝑆𝑎𝑛𝑑 𝑅, and two outputs, Q and 𝑄. Let’s start
by assuming that both inputs and the Q output are HIGH, which is the normal latched
state.
Since the Q output is connected back to an input of gate G2, and the 𝑅 input is HIGH,
the output of G2 must be LOW. This LOW output is coupled back to an input of gate
G1, ensuring that its output is HIGH.
When the Q output is HIGH, the latch is in the SET state. It will remain in this state
indefinitely until a LOW is temporarily applied to the 𝑅 input. With a LOW on the 𝑅
input and a HIGH on 𝑆, the output of gate G2 is forced HIGH. This HIGH on the 𝑄
output is coupled back to an input of G1, and since the 𝑆 input is HIGH, the output of
G1 goes LOW.
This LOW on the Q output is then coupled back to an input of G2, ensuring that the
𝑄 output remains HIGH even when the LOW on the 𝑅 input is removed. When the Q
output is LOW, the latch is in the RESET state. Now the latch remains indefinitely in
the RESET state until a momentary LOW is applied to the 𝑆 input.

FIGURE 2 The NAND gate 𝑆 − 𝑅 latch in Figure 7–1(b).

In normal operation, the outputs of a latch are always complements of each other.
When Q is HIGH, 𝑸 is LOW, and when Q is LOW, 𝑸 is HIGH.

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An invalid condition in the operation of an active-LOW input 𝑆 − 𝑅 latch occurs
when LOWs are applied to both 𝑆 and 𝑅 at the same time. As long as the LOW levels
are simultaneously held on the inputs, both the Q and 𝑄 outputs are forced HIGH,
thus violating the basic complementary operation of the outputs. Also, if the LOWs
are released simultaneously, both outputs will attempt to go LOW. Since there is
always some small difference in the propagation delay time of the gates, one of the
gates will dominate in its transition to the LOW output state. This, in turn, forces the
output of the slower gate to remain HIGH. In this situation, you cannot reliably
predict the next state of the latch.
Figure 3 illustrates the active-LOW input 𝑆 − 𝑅 latch operation for each of the four
possible combinations of levels on the inputs. (The first three combinations are valid,
but the last is not.) Table 2 summarizes the logic operation in truth table form.
Operation of the active-HIGH input NOR gate latch in Figure 1(a) is similar but
requires the use of opposite logic levels.

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 FIGURE 3 The three modes of basic 𝑆 − 𝑅 latch operation (SET, RESET, no-
change). and the invalid condition.

Table 2 - Truth table for an active-LOW input 𝑆 − 𝑅 latch.

Logic symbols for both the active-HIGH input and the active-LOW input latches are
shown in Figure 4.

FIGURE 4 Logic symbols for the S-R and 𝑆 − 𝑅 latch.

Example 1, below illustrates how an active-LOW input 𝑆 − 𝑅 latch responds to

conditions on its inputs. LOW levels are pulsed on each input in a certain sequence
and the resulting Q output waveform is observed. The 𝑆 = 0, 𝑅 = 0 , condition is

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avoided because it results in an invalid mode of operation and is a major drawback
of any SET-RESET type of latch.

Example 1.

Solution : See figure 5-b.

1.2.2. An Application
The Latch as a Contact-Bounce Eliminator

A good example of an application of an 𝑆 − 𝑅 latch is in the elimination of

mechanical switch contact “bounce.” When the pole of a switch strikes the contact
upon switch closure, it physically vibrates or bounces several times before finally
making a solid contact. Although these bounces are very short in duration, they
produce voltage spikes that are often not acceptable in a digital system. This situation
is illustrated in Figure 6(a).

Figure 6 The 𝑆 − 𝑅 latch used to eliminate switch contact bounce.

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An 𝑆 − 𝑅 latch can be used to eliminate the effects of switch bounce as shown in
Figure 6(b). The switch is normally in position 1, keeping the 𝑅 input LOW and the
latch RESET. When the switch is thrown to position 2, 𝑅 goes HIGH because of the
pull-up resistor to VCC, and 𝑆 goes LOW on the first contact. Although 𝑆 remains
LOW for only a very short time before the switch bounces, this is sufficient to set the
latch. Any further voltage spikes on the 𝑆 input due to switch bounce do not affect the
latch, and it remains SET. Notice that the Q output of the latch provides a clean
transition from LOW to HIGH, thus eliminating the voltage spikes caused by contact
bounce. Similarly, a clean transition from HIGH to LOW is made when the switch is
thrown back to position 1.

1.2.3. An Application

 Implementation: 𝑆 − 𝑅 Latch

The 74HC279A is a quad 𝑆 − 𝑅 latch represented by the logic diagram of Figure

7(a) and the pin diagram in part (b). Notice that two of the latches each have two 𝑆
inputs.

FIGURE 7 The 74HC279A quad 𝑆 − 𝑅 latch.

1.2.4. The Gated S-R Latch

A gated latch requires an Enable input, EN (G (Gate) is also used to designate an
enable input). The logic diagram and logic symbol for a gated S-R latch are shown in
Figure 8. The S and R inputs control the state to which the latch will go when a HIGH
level is applied to the EN input. The latch will not change until EN is HIGH; but as
long as sit remains HIGH, the output is controlled by the state of the S and R inputs.
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The gated latch is a level-sensitive device. In this circuit the invalid state occurs when
both S and R are simultaneously HIGH and EN is also HIGH.

Example 3.

Solution.

1.2.5. The Gated D Latch

Another type of gated latch is called the D (stand from Data) latch. It differs from the
S-R latch because it has only one input in addition to EN. This input is called the D
(data) input. Figure 10 contains a logic diagram and logic symbol of a D latch. When
the D input is HIGH and the EN input is HIGH, the latch will set. When the D input
is LOW and EN is HIGH, the latch will reset. Stated another way, the output Q
follows the input D when EN is HIGH.

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 Figure 10. A gated D Latch.

Example 4.

Solution.

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Implementation of gated D latch.

1.3. Flip – Flops.

Flip-flops (FFs). are synchronous bistable devices, also known as bistable
multivibrators. In this case, the term synchronous means that the output changes state
only at a specified point (leading or trailing edge) on the triggering input called the
clock (CLK), which is designated as a control input, (C); that is, changes in the
output occur in synchronization with the clock.
Flip-flops are edge-triggered or edge-sensitive whereas gated latches are level-
sensitive.
An edge-triggered flip-flop changes state either at the positive edge (rising edge) or
at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only
at this transition of the clock. Two types of edge-triggered flip-flops are covered: D
and J-K Flip Flops. The logic symbols for these flip-flops are shown in Figure 13.
Notice that each type can be either positive edge-triggered (no bubble at C input) or
negative edge-triggered (bubble at C input). The key to identifying an edge-triggered
flip-flop by its logic symbol is the small triangle inside the block at the clock (C)
input. This triangle is called the dynamic input indicator.

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 Figure 13. Edge-triggered FF logic symbols (top: positive edge-triggered; bottom:
negative edge-triggered).

1.3.1. The D Flip-Flop

The D input of the D flip-flop is a synchronous input because data on the input are
transferred to the flip-flop’s output only on the triggering edge of the clock pulse.
When D is HIGH, the Q output goes HIGH on the triggering edge of the clock pulse,
and the flip-flop is SET. When D is LOW, the Q output goes LOW on the triggering
edge of the clock pulse, and the flip-flop is RESET.
This basic operation of a positive edge-triggered D flip-flop is illustrated in Figure
14, and Table 3 is the truth table for this type of flip-flop. Remember, the flip-flop
cannot change state except on the triggering edge of a clock pulse. The D input can
be changed at any time when the clock input is LOW or HIGH (except for a very
short interval around the triggering transition of the clock) without affecting the
output. Just remember, Q follows D at the triggering edge of the clock.

Figure 14. Operation of a positive edge-triggered D Flip-Flop.

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The operation and truth table for a negative edge-triggered D flip-flop are the same as
those for a positive edge-triggered device except that the falling edge of the clock
pulse is the triggering edge and the change happened at the falling edge of the clock..

Example 4.
Determine the Q and Q output waveforms of the flip-flop in figure 15 for the D and
CLK inputs in figure 16-a. Assume that the positive-edge-triggered FF is initially
RESET.

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 1.3.2. J-K Flip-Flop.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input
circuitry that prevents the illegal or invalid output condition that can occur when both
inputs S and R are equal to logic level “1”.
The inputs are labeled J and K in honor of the inventor of the device, Jack Kilby.
Referring to figure 17, the J and K inputs of the J-K flip-flop are synchronous inputs
because data on these inputs are transferred to the flip-flop’s output only on the
triggering edge of the clock pulse. When J is HIGH and K is LOW, the Q output goes
HIGH on the triggering edge of the clock pulse, and the flip-flop is SET. When J is
LOW and K is HIGH, the Q output goes LOW on the triggering edge of the clock
pulse, and the flip-flop is RESET. When both J and K are LOW, the output does not
change from its prior state. When J and K are both HIGH, the flip-flop changes state.
This called the toggle mode. Toggle means that the Q output will change states on
each active clock edge (if Q was 1 becomes 0 and if Q was 0 becomes 1).
This basic operation of a positive edge-triggered flip-flop is illustrated in Figure 17,
and Table 4 is the truth table for this type of flip-flop. Remember, the flip-flop cannot
change state except on the triggering edge of a clock pulse. The J and K inputs can be
changed at any time when the clock input is LOW or HIGH without affecting the
output.

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Biomedical Engineering - Digital Electronics II - Fourth year – Prof. Dr. Mahmoud Alshemmary -15-
Example 5.

Solution.

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Note:
In "JK Flip Flop", when both the inputs and CLK set to 1 for a long time, then Q
output toggle until the CLK is 1. Thus, the uncertain or unreliable output produces.
This problem is referred to as a race-round condition in JK flip-flop and avoided by
ensuring that the CLK set to 1 only for a very short time.

1.3.3. Master- slave J-K Flip flop

As shown in figure (19 )The master-slave flip flop is constructed by combining
two JK flip flops. These flip flops are connected in a series configuration. In these
two flip flops, the 1st flip flop work as "master", called the master flip flop, and the
2nd work as a "slave", called slave flip flop. The master-slave flip flop is designed in
such a way that the output of the "master" flip flop is passed to both the inputs of the
"slave" flip flop. The output of the "slave" flip flop is passed to inputs of the master
flip flop.
In "master-slave flip flop", apart from these two flip flops, an inverter or NOT gate is
also used. For passing the inverted clock pulse to the "slave" flip flop, the inverter is
connected to the clock's pulse. In simple words, when CP set to false for "master",
then CP is set to true for "slave", and when CP set to true for "master", then CP is set
to false for "slave".

The operation of Master-Slave J-K FF is as follows:

 When the clock pulse is true, the slave flip flop will be in the isolated state, and
the system's state may be affected by the J and K inputs. The "slave" remains
isolated until the Clk is 1. When the Clk set to 0, the master flip-flop passes
the information to the slave flip flop to obtain the output.
 The master flip flop responds first from the slave because the master flip flop is
the positive level trigger, and the slave flip flop is the negative level trigger.

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  The output 𝑄 =1 of the master flip flop is passed to the slave flip flop as an
input K when the input J set to 0 and K set to 1. The clock forces the slave flip
flop to work as reset, and then the slave copies the master flip flop.
 When J=1, and K=0, the output Q=1 is passed to the J input of the slave. The
clock's negative transition sets the slave and copies the master.
 The master flip flop toggles on the clock's positive transition when the inputs J
and K set to 1. At that time, the slave flip flop toggles on the clock's negative
transition.
 The flip flop will be disabled, and Q remains unchanged when both the inputs
of the JK flip flop set to 0.
 When the clock pulse set to 1, the output of the master flip flop will be one
until the clock input remains 0.
 When the clock pulse becomes high again, then the master's output is 0, which
will be set to 1 when the clock becomes one again.
 The master flip flop is operational when the clock pulse is 1. The slave's output
remains 0 until the clock is not set to 0 because the slave flip flop is not
operational.
 The slave flip flop is operational when the clock pulse is 0. The output of the
master remains one until the clock is not set to 0 again.
 Toggling occurs during the entire process because the output changes once in
the cycle.

The Timing diagram of Master-Slave J-K Flip-flop is shown in figure 20,

Figure (20) timing diagram of Master-Slave J-K Flip-flop.

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As shown in figure 21, the TTL 74LS73 is a Dual JK flip-flop IC, which contains two
individual JK type bistable’s within a single chip enabling single or master-slave
toggle flip-flops to be made.

Figure 21. Dual J-K- Flip-Flop 74LS73 pin diagram.

What is difference between latches and flip flops?

Both latches and flip-flops are circuit elements whose output depends not only on
the current inputs, but also on previous inputs and outputs. The difference
between a latch and a flip-flop is that a latch does not have a clock signal, whereas
a flip-flop always does.

1.4. Edge-Triggered Operation

A Pulse transition detector (PTD) is used in flip flops in order to
achieve edge triggering in the circuit. It merely converts the clock signal's rising edge
to a very narrow pulse.
The PTD consists of a delay gate (which delays the clock signal) and the clock signal
itself passed through a NAND gate and then inverted.
The benefit of edge triggering is that it removes the problems of zeroes and ones
catching associated with pulse triggered flip-flops.

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1.5. Asynchronous Preset and Clear Inputs
For the flip-flops just discussed, the D and J-K inputs are called synchronous inputs
because data on these inputs are transferred to the flip-flop’s output only on the
triggering edge of the clock pulse; that is, the data are transferred synchronously with
the clock.
Most integrated circuit flip-flops also have asynchronous inputs. These are inputs
that affect the state of the flip-flop independent of the clock. They are normally
labeled preset (PRE) and clear (CLR), or direct set (SD) and direct reset (RD) by
some manufacturers. An active level on the preset input will set the flip-flop, and an
active level on the clear input will reset it; they can set or reset the flip-flop regardless
of the status of the clock signal. A logic symbol for a D flip-flop with preset and clear
inputs is shown in Figure 22. These inputs are active-LOW, as indicated by the
bubbles. These preset and clear inputs must both be kept HIGH for synchronous
operation. In normal operation, preset and clear would not be LOW at the same time.
Figure 23 shows the logic diagram for an edge-triggered D flip-flop with active-LOW
preset (PRE) and clear (CLR) inputs. This figure illustrates basically how these inputs
work. As you can see, they are connected so that they override the effect of the
synchronous input, D and the clock.

Example 7.
For the positive edge-triggered D flip-flop with preset and clear inputs in Figure 24,
determine the Q output for the inputs shown in the timing diagram in part (a) if Q is
initially LOW.

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Solution.

Implementation: D Flip-Flop
Fixed-Function Device The 74HC74 dual D flip-flop contains two identical D flip-
flops that are independent of each other except for sharing VCC and ground. The flip-
flops are positive edge-triggered and have active-LOW asynchronous preset and clear
inputs. The logic symbols for the individual flip-flops within the package are shown
in Figure 25(a), and an ANSI/IEEE standard single block symbol that represents the
entire device is shown in part (b). The pin numbers are shown in parentheses.

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Implementation: J-K Flip-Flop
Fixed-Function Device The 74HC112 dual J-K flip-flop has two identical flip-flops
that are negative edge-triggered and have active-LOW asynchronous preset and clear
inputs. The logic symbols are shown in Figure 26.

EXAMPLE 8
The 1J, 1K, 1CLK, 1PRE, and 1CLR waveforms in Figure 27(a) are applied to one of
the negative edge-triggered flip-flops in a 74HC112 package. Determine the 1Q
output waveform.

Figure 27. Waveforms for example 8.

Solution.

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1.6. T Flip-flop
While the Data (D) flip-flop is a variation of a clocked SR flip-flop constructed using
either NAND or NOR gates, the Toggle (T) flip-flop is a variation of the clocked JK
flip-flop. The toggle or T-type flip-flop gets its name from the fact that its two
outputs Q and 𝑄 invert from their previous state as it toggles back and forth every
time it is triggered (T = 1). Figure 28 shows the symbol of T flip-flop.

Figure 28 shows the symbol of T Flip-Flop.

That is, the Q and 𝑄 outputs change to a “1” if it was “0”, and “0” if it was previously
a “1” but only when the “T” input changes HIGH, otherwise they do not change, and
its asynchronous toggling action is explained here.
The JK is renamed T for T-type or Toggle flip-flop and is generally represented by
the logic or graphical symbol shown. The Toggle schematic symbol has two inputs
available, one represents the “toggle” (T) input and the other the “clock” (CLK)
input.
Also, just like the 74LS73 JK flip-flop, the T-type can also be configured to have an
enable input called EN or CE (clock enable) allowing it to hold the last data state
stored on its outputs indefinitely. Thus with the clock enable input set, the application
of any new clock pulses prevents toggling of the outputs. But this “enable” feature, if
required, must be implemented using additional logic gates.

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The triangle of chevron on the input of either type of T-type flip-flop indicates that it
is an edge-triggered device. If there is a small bubble or circle at the input, then it
indicates that the flip-flop toggles on the negative falling edge (HIGH-to-LOW) of
each pulse, otherwise, it changes state on the positive or rising transistional edge
(LOW-to-HIGH) of each input pulse.
Then we can create the logic circuit of a single bit toggle flip-flop using the basic JK
flip-flop by connecting the J and K data inputs together where the common point at
the connection of the two inputs is designated T, as shown in figure 29..

Figure 29. The formulation of T- FF from J-K FF and its timing diagram.

Suppose that initially CLK and input T are both LOW (CLK = T = 0), and that
output Q is HIGH (Q = 1). At the rising edge or falling edge of a CLK pulse, the
logic “0” condition present at T prevents the output at Q from changing state. Thus
the output remains unchanged when T = 0.
Now let’s suppose that input T is HIGH (T = 1) and CLK is LOW (CLK = 0). At the
rising edge (assuming positive transition) of a CLK pulse at time t1, the output
at Q changes state and becomes LOW, making Q HIGH. The negative transition of
the clock pulse from HIGH to LOW at time t2 has no effect on the output at Q as the
flip-flop is reset into one stable state.
At the next rising edge of the clock signal at time t3, the logic “1” at T passes to Q,
changing its state making output Q HIGH again. The negative transition of the CLK
pulse at time t4 from HIGH to LOW once again has no effect on the output. Thus
the Q output of the flip-flop “toggles” at each positive going edge (for this example)
of the CLK pulse.

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Note: T-FF’s are not available commercially as a dedicated TTL or CMOS logic
chip, and as we mentioned, they can be easily constructed by connecting together
the J and K inputs of a basic JK flip-flop.

1.7. Flip-Flop Applications

1.7.1. Frequency Division.

An important application of a flip-flop is dividing (reducing) the frequency of a
periodic waveform. When a pulse waveform is applied to the clock input of a D or J-
K flip-flop that is connected to toggle (D = 𝑄 or J = K = 1), the Q output is a square
wave with one-half the frequency of the clock input. Thus, a single flip-flop can be
applied as a divide-by-2 device, as is illustrated in Figure 7–30 for both a D and a J-K
flip-flop. As you can see in part (c), the flip-flop changes state on each triggering
clock edge (positive edge-triggered in this case). This results in an output that
changes at half the frequency of the clock waveform.

FIGURE 30 The D flip-flop and J-K flip-flop as a divide-by-2 device. Q is one-half

the frequency of CLK.

Further division of a clock frequency can be achieved by using the output of one
flipflop as the clock input to a second flip-flop, as shown in Figure 7–31. The
frequency of the QA output is divided by 2 by flip-flop B. The QB output is,
therefore, one-fourth the frequency of the original clock input. Propagation delay
times are not shown on the timing diagrams.

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FIGURE 31 Example of two D flip-flops used to divide the clock frequency by 4. QA
is one-half and QB is one-fourth the frequency of CLK.

By connecting flip-flops in this way, a frequency division of 2n is achieved, where n

is the number of flip-flops. For example, three flip-flops divide the clock frequency
by 23 = 8; four flip-flops divide the clock frequency by 24 = 16; and so on.

1.7.2. Counting
Another important application of flip-flops is in digital counters, the concept is
illustrated in Figure 32. Negative edge-triggered J-K flip-flops are used for
illustration. Both flip-flops are initially RESET. Flip-flop A toggles on the negative-
going transition of each clock pulse. The Q output of flip-flop A clocks flip-flop B, so
each time QA makes a HIGH-to-LOW transition, flip-flop B toggles. The resulting
QA and QB waveforms are shown in the figure.
Observe the sequence of QA and QB in Figure 32. Prior to clock pulse 1, QA = 0 and
QB = 0; after clock pulse 1, QA = 1 and QB = 0; after clock pulse 2, QA = 0 and QB =
1; and after clock pulse 3, QA = 1 and QB = 1. If we take QA as the least significant
bit, a 2-bit sequence is produced as the flip-flops are clocked. This binary sequence
repeats every four clock pulses, as shown in the timing diagram of Figure 7–40. Thus,
the flip-flops are counting in sequence from 0 to 3 (00, 01, 10, 11) and then recycling
back to 0 to begin the sequence again.

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FIGURE 32 J-K flip-flops used to generate a binary count sequence (00, 01, 10, 11).
Two repetitions are shown.

Example 9.
Determine the output waveforms in relation to the clock for QA, QB, and QC in the
circuit of Figure 33 and show the binary sequence represented by these waveforms.

Figure 33
Solution
The output timing diagram is shown in Figure 34. Notice that the outputs change on
the negative-going edge of the clock pulses. The outputs go through the binary
sequence 000, 001, 010, 011, 100, 101, 110, and 111 as indicated.

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 Figure 34.

1.8. The 555 Timer as an Astable Multivibrator (Clock Signal Generator).

The 555 timer is a versatile and widely used IC device because it can be configured in two
different modes as either a monostable multivibrator (one-shot) or as an astable multivibrator
(pulse oscillator).
An astable multivibrator is a device that has no stable states; it changes back and
forth (oscillates) between two unstable states without any external triggering. The
resulting output is typically a square wave that is used as a clock signal in many types
of sequential logic circuits. Astable multivibrators are also known as pulse oscillators
and are normally used as a clock pulse generator.

The 555 Timer Operation

A functional diagram showing the internal components of a 555 timer is shown in
Figure 34. The comparators are devices whose outputs are HIGH when the voltage on
the positive (+) input is greater than the voltage on the negative (-) input and LOW
when the - input voltage is greater than the + input voltage.
The voltage divider consisting of three 5 k_ resistors provides a trigger level of 1/3
VCC and a threshold level of 2/3 VCC. The control voltage input (pin 5) can be used
to externally adjust the trigger and threshold levels to other values if necessary. When
the normally HIGH trigger input momentarily goes below 1/3 VCC, the output of
comparator B switches from LOW to HIGH and sets the S-R latch, causing the output
(pin 3) to go HIGH and turning the discharge transistor Q1 off.
The output will stay HIGH until the normally LOW threshold input goes above 2/3
VCC and causes the output of comparator A to switch from LOW to HIGH. This
resets the latch, causing the output to go back LOW and turning the discharge
transistor on. The external reset input can be used to reset the latch independent of the
threshold circuit. The trigger and threshold inputs (pins 2 and 6) are controlled by
external components connected to produce either monostable or astable action.

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 Figure 34 Internal functional diagram of a 555 timer (pin numbers are in
parentheses).

Monostable (One-Shot) Operation

An external resistor and capacitor connected as shown in Figure 35 are used to set up
the 555 timer as a nonretriggerable one-shot. The pulse width of the output is
determined by the time constant of R1 and C1 according to the following formula:

tw = 1.1R1C1
The control voltage input is not used and is connected to a decoupling capacitor C2 to
prevent noise from affecting the trigger and threshold levels.

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 Figure 35 The 555 timer connected as a one-shot.
Example 10.
What is the output pulse width for a 555 monostable circuit with R1 = 2.2 kΩ and
C1 = 0.01 mF?

Solution
From Equation that applied for one shot connection , the pulse width is
tW = 1.1R1C1 = 1.1(2.2 kΩ)(0.01 mF) = 24.2 ms

Astable Multivibrator
An astable multivibrator is a device that has no stable states; it changes back and
forth (oscillates) between two unstable states without any external triggering. The
resulting output is typically a square wave that is used as a clock signal in many types
of sequential logic circuits. Astable multivibrators are also known as pulse oscillators
and are normally used as a clock pulse generator.

A 555 timer connected to operate as an astable multivibrator is shown in Figure 36.

Notice that the threshold input (THRESH) is now connected to the trigger input
(TRIG).
The external components R1, R2, and C1 form the timing network that sets the
frequency of oscillation. The 0.01 mF capacitor, C2, connected to the control (CONT)
input is strictly for decoupling and has no effect on the operation; in some cases it can
be left off.

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Initially, when the power is turned on, the capacitor (C1) is uncharged and thus the
trigger voltage (pin 2) is at 0 V. This causes the output of comparator B to be HIGH
and the output of comparator A to be LOW, forcing the output of the latch, and thus
the base of Q1, LOW and keeping the transistor off. Now, C1 begins charging
through R1 and R2, as indicated in Figure 37. When the capacitor voltage reaches 1/3
VCC, comparator B switches to its LOW output state; and when the capacitor voltage
reaches 2/3 VCC, comparator A switches to its HIGH output state. This resets the
latch, causing the base of Q1 to go HIGH and turning on the transistor. This sequence
creates a discharge path for the capacitor through R2 and the transistor, as indicated.
The capacitor now begins to discharge, causing comparator A to go LOW. At the
point where the capacitor discharges down to 1/3 VCC, comparator B switches
HIGH; this sets the latch, making the base of Q1 LOW and turning off the transistor.
Another charging cycle begins, and the entire process repeats. The result is a
rectangular wave output whose duty cycle depends on the values of R1 and R2.
The frequency of oscillation is given by the following formula.

And the formula to calculate the duty cycle is,

For duty cycle > 50%

To achieve duty cycles of less than 50 percent, the circuit in Figure 36 can be
modified so that C1 charges through only R1 and discharges through R2. This is

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achieved with a diode, D1, placed as shown in Figure 39. The duty cycle can be made
less than 50 percent by making R1 less than R2. Under this condition, the expression
for the duty cycle is,

For duty cycle < 50%

Example 11.
EXAMPLE 7–14
A 555 timer configured to run in the astable mode (pulse oscillator) is shown in
Figure 38. Determine the frequency of the output and the duty cycle.

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Solution.
Using the appropriate equations to calculate the value of frequency and duty cycle of
the circuit output as follows, (it is obvious that the circuit is for duty cycle )

Note : The 556 is a dual 555 ICs.

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