LM567, LM567C

SNOSBQ4F – MAY 1999 – REVISED JANUARY 2022

LM567x Tone Decoder

1 Features 3 Description
• 20 to 1 Frequency Range With an External The LM567 and LM567C are general purpose tone
Resistor decoders designed to provide a saturated transistor
• Logic Compatible Output With 100-mA Current switch to ground when an input signal is present
Sinking Capability within the passband. The circuit consists of an I and Q
• Bandwidth Adjustable From 0 to 14% detector driven by a voltage controlled oscillator which
• High Rejection of Out of Band Signals and Noise determines the center frequency of the decoder.
• Immunity to False Signals External components are used to independently set
• Highly Stable Center Frequency center frequency, bandwidth and output delay.
• Center Frequency Adjustable from 0.01 Hz to
Device Information(1)
500 kHz
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications SOIC (8) 4.90 mm × 3.91 mm
LM567C
• Touch Tone Decoding PDIP (8) 9.81 mm × 6.35 mm
• Precision Oscillator
(1) For all available packages, see the orderable addendum at
• Frequency Monitoring and Control the end of the datasheet.
• Wide Band FSK Demodulation
• Ultrasonic Controls
• Carrier Current Remote Controls
• Communications Paging Decoders

Simplified Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 9.4 Device Functional Modes..........................................10
2 Applications..................................................................... 1 10 Application and Implementation................................ 12
3 Description.......................................................................1 10.1 Application Information........................................... 12
4 Revision History.............................................................. 2 10.2 Typical Applications................................................ 12
5 Device Comparison......................................................... 3 11 Power Supply Recommendations..............................18
6 Pin Configuration and Functions...................................3 12 Layout...........................................................................18
7 Specifications.................................................................. 4 12.1 Layout Guidelines................................................... 18
7.1 Absolute Maximum Ratings........................................ 4 12.2 Layout Example...................................................... 18
7.2 Recommended Operating Conditions.........................4 13 Device and Documentation Support..........................19
7.3 Thermal Information....................................................4 13.1 Receiving Notification of Documentation Updates..19
7.4 Electrical Characteristics.............................................5 13.2 Support Resources................................................. 19
7.5 Typical Characteristics................................................ 6 13.3 Trademarks............................................................. 19
8 Parameter Measurement Information............................ 8 13.4 Electrostatic Discharge Caution..............................19
9 Detailed Description........................................................8 13.5 Glossary..................................................................19
9.1 Overview..................................................................... 8 14 Mechanical, Packaging, and Orderable
9.2 Functional Block Diagram........................................... 8 Information.................................................................... 19
9.3 Feature Description.....................................................9

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (October 2014) to Revision F (January 2022) Page
• Changed the pin number of 5 and 6 in the Pin Functions table..........................................................................3
• Changed Equation 1 .......................................................................................................................................... 9
• Changed Equation 2 ........................................................................................................................................ 13

Changes from Revision D (March 2013) to Revision E (October 2014) Page

• Added Pin Configuration and Functions section, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ........... 1

Changes from Revision C (March 2013) to Revision D (March 2013) Page

• Changed layout of National Data Sheet to TI format.......................................................................................... 9

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5 Device Comparison
Table 5-1. Device Comparison
DEVICE NAME DESCRIPTION
LM567, LM567C General Purpose Tone Decoder
LMC567 Same as LM567C, but lower power supply current consumption and double oscillator frequency

6 Pin Configuration and Functions

Figure 6-1. 8-Pin PDIP (P) and SOIC (D) Package Top View

Table 6-1. Pin Functions

PIN
TYPE DESCRIPTION
NAME NO.
GND 7 P Circuit ground.
IN 3 I Device input.
LF_CAP 2 I Loop filter capacitor pin (LPF of the PLL).
OUT 8 O Device output.
OF_CAP 1 I Output filter capacitor pin.
T_CAP 6 I Timing capacitor connection pin.
T_RES 5 I Timing resistor connection pin.
VCC 4 P Voltage supply pin.

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7 Specifications
7.1 Absolute Maximum Ratings
See (1) (2)
MIN MAX UNIT
Supply Voltage Pin 9 V
Power Dissipation(1) 1100 mW
V8 15 V
V3 −10 V
V3 V4 + 0.5 V
LM567CM, LM567CN 0 70 °C
PDIP Package Soldering (10 s) 260 °C
Operating Temperature Range
Vapor Phase (60 s) 215 °C
SOIC Package
Infrared (15 s) 220 °C
Storage temperature range, Tstg −65 150 °C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions
indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC
and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device
is within the Recommended Operating Conditions. Specifications are not ensured for parameters where no limit is given, however, the
typical value is a good indication of device performance.
(2) See http://www.ti.com for other methods of soldering surface mount devices.

7.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply Voltage 3.5 8.5 V
VIN Input Voltage Level –8.5 8.5 V
TA Operating Temperature Range –20 120 °C

7.3 Thermal Information

LM567C
THERMAL METRIC(1) D (SOIC) P (PDIP) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 107.5 53.0
RθJC(top) Junction-to-case (top) thermal resistance 54.6 42.3
RθJB Junction-to-board thermal resistance 47.5 30.2 °C/W
ψJT Junction-to-top characterization parameter 10.0 19.6
ψJB Junction-to-board characterization parameter 47.0 30.1

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, (SPRA953).

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7.4 Electrical Characteristics

AC Test Circuit, TA = 25°C, V+ = 5 V
LM567 LM567C/LM567CM
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
Power Supply Voltage Range 4.75 5.0 9.0 4.75 5.0 9.0 V
Power Supply Current Quiescent RL = 20k 6 8 7 10 mA
Power Supply Current Activated RL = 20k 11 13 12 15 mA
Input Resistance 18 20 15 20 kΩ
Smallest Detectable Input Voltage IL = 100 mA, fi = fo 20 25 20 25 mVrms
Largest No Output Input Voltage IC = 100 mA, fi = fo 10 15 10 15 mVrms
Largest Simultaneous Outband Signal to
6 6 dB
Inband Signal Ratio
Minimum Input Signal to Wideband Noise Bn = 140 kHz
−6 −6 dB
Ratio
Largest Detection Bandwidth 12 14 16 10 14 18 % of fo
Largest Detection Bandwidth Skew 1 2 2 3 % of fo
Largest Detection Bandwidth Variation with
±0.1 ±0.1 %/°C
Temperature
Largest Detection Bandwidth Variation with 4.75 – 6.75 V
±1 ±2 ±1 ±5 %V
Supply Voltage
Highest Center Frequency 100 500 100 500 kHz
Center Frequency Stability (4.75 – 5.75 V) 0 < TA < 70 35 ± 60 35 ± 60 ppm/°C
−55 < TA < +125 35 ± 140 35 ± 140 ppm/°C
Center Frequency Shift with Supply Voltage 4.75 V – 6.75 V 0.5 1.0 0.4 2.0 %/V
4.75 V – 9 V 2.0 2.0 %/V
Fastest ON-OFF Cycling Rate fo/20 fo/20
Output Leakage Current V8 = 15 V 0.01 25 0.01 25 µA
Output Saturation Voltage ei = 25 mV, I8 = 30 mA 0.2 0.4 0.2 0.4
V
ei = 25 mV, I8 = 100 mA 0.6 1.0 0.6 1.0
Output Fall Time 30 30 ns
Output Rise Time 150 150 ns

(1) The maximum junction temperature of the LM567 and LM567C is 150°C. For operating at elevated temperatures, devices in the DIP
package must be derated based on a thermal resistance of 110°C/W, junction to ambient. For the SOIC package, the device must be
derated based on a thermal resistance of 160°C/W, junction to ambient.

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7.5 Typical Characteristics

Figure 7-1. Typical Frequency Drift Figure 7-2. Typical Bandwidth Variation

Figure 7-3. Typical Frequency Drift Figure 7-4. Typical Frequency Drift

Figure 7-5. Bandwidth vs Input Signal Amplitude Figure 7-6. Largest Detection Bandwidth

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7.5 Typical Characteristics (continued)

Figure 7-7. Detection Bandwidth as a Function of C2 and C3 Figure 7-8. Typical Supply Current vs Supply Voltage

Figure 7-9. Greatest Number of Cycles Before Output Figure 7-10. Typical Output Voltage vs Temperature

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8 Parameter Measurement Information

All parameters are measured according to the conditions described in the Specifications section.

9 Detailed Description
9.1 Overview
The LM567C is a general purpose tone decoder. The circuit consists of I and Q detectors driven by a voltage
controlled oscillator which determines the center frequency of the decoder. This device is designed to provide
a transistor switch to ground output when the input signal frequency matches the center frequency pass band.
Center frequency is set by an external timing circuit composed by a capacitor and a resistor. Bandwidth and
output delay are set by external capacitors.
9.2 Functional Block Diagram

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9.3 Feature Description

9.3.1 Center Frequency
The center frequency of the LM567 tone decoder is equal to the free running frequency of the voltage controlled
oscillator. In order to set this frequency, external components should be placed externally. The component
values are given by:

fo ≃ 1 / (1.1 × R1 × C1) (1)

where
• R1 = Timing Resistor
• C1 = Timing Capacitor
9.3.2 Output Filter
To eliminate undesired signals that could trigger the output stage, a post detection filter is featured in the
LM567C. This filter consists of an internal resistor (4.7K-Ω) and an external capacitor. Although typically external
capacitor value is not critical, it is recommended to be at least twice the value of the loop filter capacitor. If the
output filter capacitor value is too large, the turn-on and turn off-time of the output will present a delay until the
voltage across this capacitor reaches the threshold level.
9.3.3 Loop Filter
The phase locked loop (PLL) included in the LM567 has a pin for connecting the low pass loop filter capacitor.
The selection of the capacitor for the filter depends on the desired bandwidth. The device bandwidth selection
is different according to the input voltage level. Refer to the Operation With Vi < 200m – VRMS section and the
Operation With Vi > 200m – VRMS section for more information about the loop filter capacitor selection.
9.3.4 Logic Output
The LM567 is designed to provide a transistor switch to ground output when the input signal frequency matches
the center frequency pass band. The logic output is an open collector power transistor that requires an external
load resistor that is used to regulate the output current level.
9.3.5 Die Characteristics

Figure 9-1. Die Layout (C - Step)

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Table 9-1. Die and Wafer Characteristics

Fabrication Attributes General Die Information
Physical Die Identification LM567C Bond Pad Opening Size (min) 91µm x 91µm
Die Step C Bond Pad Metalization 0.5% COPPER_BAL.
ALUMINUM
Physical Attributes Passivation VOM NITRIDE
Wafer Diameter 150mm Back Side Metal BARE BACK
Dise Size (Drawn) 1600µm x 1626µm Back Side Connection Floating
63.0mils x 64.0mils
Thickness 406µm Nominal
Min Pitch 198µm Nominal
Special Assembly Requirements:
Note: Actual die size is rounded to the nearest micron.

Die Bond Pad Coordinate Locations (C - Step)

(Referenced to die center, coordinates in µm) NC = No Connection, N.U. = Not Used
X/Y COORDINATES PAD SIZE
SIGNAL NAME PAD# NUMBER
X Y X Y
OUTPUT FILTER 1 -673 686 91 x 91
LOOP FILTER 2 -673 -419 91 x 91
INPUT 3 -673 -686 91 x 91
V+ 4 -356 -686 91 x 91
TIMING RES 5 673 -122 91 x 91
TIMING CAP 6 673 76 91 x 91
GND 7 178 686 117 x 91
OUTPUT 8 -318 679 117 x 104

9.4 Device Functional Modes

9.4.1 Operation With Vi < 200m – VRMS
When the input signal is below a threshold voltage, typically 200m-VRMS, the bandwidth of the detection band
should be calculated Equation 2.

where
• Vi = Input voltage (volts rms), Vi ≤ 200mV
• C2 = Capacitance at Pin 2(μF)

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9.4.2 Operation With Vi > 200m – VRMS

For input voltages greater than 200m-VRMS, the bandwidth depends directly from the loop filter capacitance and
free running frequency product. Bandwidth is represented as a percentage of the free running frequency, and
according to the product of f0∙C2, it can have a variation from 2 to 14%. Table 9-2 shows the approximate values
for bandwidth in function of the product result.
Table 9-2. Detection Bandwidth in Function of fo × C2
fo × C2 (kHzµF) Bandwidth (% of fo)
62 2
16 4
7.3 6
4.1 8
2.6 10
1.8 12
1.3 14
< 1.3 14

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10 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

10.1 Application Information

The LM567 tone decoder is a device capable of detecting if an input signal is inside a selectable range of
detection. The device has an open collector transistor output, so an external resistor is required to achieve
proper logic levels. When the input signal is inside the detection band, the device output will go to a LOW state.
The internal VCO free running frequency establishes the detection band central frequency. An external RC filter
is required to set this frequency. The bandwidth in which the device will detect the desired frequency depends
on the capacitance of loop filter terminal. Typically a 1µF capacitor is connected to this pin. The device detection
band has a different behavior for low and high input voltage levels. Refer to the Operation With Vi < 200m –
VRMS section and the Operation With Vi > 200m – VRMS section for more information.
10.2 Typical Applications
10.2.1 Touch-Tone Decoder

Component values (typ) R1 6.8 to 15k R2 4.7k R3 20k C1 0.10 mfd C2 1.0 mfd 6V C3 2.2 mfd 6V C4 250 mfd 6V

Figure 10-1. Touch-Tone Decoder

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10.2.1.1 Design Requirements

PARAMETERS VALUES
Supply Voltage Range 3.5 V to 8.5 V
Input Voltage Range 20 mVRMS to VCC + 0.5
Input Frequency 1 Hz to 500 kHz
Output Current Max. 15 mA

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Timing Components
To calculate the timing components for an approximated desired central detection frequency (f0), the timing
capacitor value (C1) should be stated in order to calculate the timing resistor value (R1). Typically for most
applications, a 0.1-µF capacitor is used.

fo = 1 / (1.1 × R1 × C1) (2)

10.2.1.2.2 Bandwidth
Detection bandwidth is represented as a percentage of f0. It can be selected based on the input voltage levels
(Vi). For Vi < 200 mVRMS,

(3)

For Vi > 200 mVRMS, refer to Table 9-2 or Figure 7-5.

10.2.1.2.3 Output Filter
The output filter selection is made considering the capacitor value to be at least twice the Loop filter capacitor.

C3 ≥ 2C2 (4)

10.2.1.3 Application Curve

IN (PIN 3)
OUT (PIN 8)

Figure 10-2. Frequency Detection

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10.2.2 Oscillator with Quadrature Output

Connect Pin 3 to 2.8V to Invert Output

Figure 10-3. Oscillator with Quadrature Output

10.2.2.1 Design Requirements

Refer to the previous Design Requirements section.
10.2.2.2 Detailed Design Procedure
Refer to the previous Detailed Design Procedure section.
10.2.2.3 Application Curve

OUT 1 (PIN 3)
OUT 2 (PIN 8)

Figure 10-4. Quadrature Output

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10.2.3 Oscillator with Double Frequency Output

Figure 10-5. Oscillator with Double Frequency Output

10.2.3.1 Design Requirements

Refer to the previous Design Requirements section.
10.2.3.2 Detailed Design Procedure
Refer to the previous Detailed Design Procedure section.
10.2.3.3 Application Curve

OUT 1 (PIN 5)
OUT 2 (PIN 8)

Figure 10-6. Double Frequency Output

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10.2.4 Precision Oscillator Drive 100-mA Loads

Figure 10-7. Precision Oscillator Drive 100-mA Loads

10.2.4.1 Design Requirements

Refer to the previous Design Requirements section.
10.2.4.2 Detailed Design Procedure
Refer to the previous Detailed Design Procedure section.
10.2.4.3 Application Curve

OUT (PIN 8)

Figure 10-8. Output for 100-mA Load

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10.2.5 AC Test Circuit

fi = 100 kHz + 5 V
*Note: Adjust for fo = 100 kHz.

10.2.5.1 Design Requirements

Refer to the previous Design Requirements section.
10.2.5.2 Detailed Design Procedure
Refer to the previous Detailed Design Procedure section.
10.2.5.3 Application Curve
Refer to the previous Application Curve section.

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11 Power Supply Recommendations

The LM567C is designed to operate with a power supply up to 9 V. It is recommended to have a well regulated
power supply. As the operating frequency of the device could be very high for some applications, the decoupling
of power supply becomes critical, so is required to place a proper decoupling capacitor as close as possible to
VCC pin.

12 Layout
12.1 Layout Guidelines
The VCC pin of the LM567 should be decoupled to ground plane as the device can work with high switching
speeds. The decoupling capacitor should be placed as close as possible to the device. Traces length for the
timing and external filter components should be kept at minimum in order to avoid any possible interference from
other close traces.
12.2 Layout Example

Figure 12-1. LM567 Layout Example

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13 Device and Documentation Support

13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

13.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

LM567CM/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM 0 to 70 LM

567CM
LM567CM/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM 0 to 70 LM
567CM
LM567CMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM 0 to 70 LM
567CM
LM567CMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM 0 to 70 LM
567CM
LM567CN/NOPB Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LM
567CN
LM567CN/NOPB.B Active Production PDIP (P) | 8 40 | TUBE Yes NIPDAU Level-1-NA-UNLIM 0 to 70 LM
567CN

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM567CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM567CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

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 PACKAGE MATERIALS INFORMATION

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TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LM567CM/NOPB D SOIC 8 95 495 8 4064 3.05
LM567CM/NOPB.B D SOIC 8 95 495 8 4064 3.05
LM567CN/NOPB P PDIP 8 40 502 14 11938 4.32
LM567CN/NOPB.B P PDIP 8 40 502 14 11938 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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