Microcontrollers 4Sem ECE/TCE

MODULE-2
2.1 INSTRUCTION SYNTAX.
General syntax for 8051 assembly language is as follows.
LABEL: OPCODE OPERAND ;COMMENT
LABEL:(THIS IS NOT NECESSARY UNLESS THAT SPECIFIC LINE HAS TO BE ADDRESSED). The label is a
symbolic
address for the instruction. When the program is assembled, the label will be given specific
in which that address
instruction is stored. Unless that specific line of instruction is needed by a branching
instruction in the program, it is not necessary to label that line.
OPCODE: Opcode is the symbolic representation of the operation. The assembler converts the
opcode to a unique binary code (machine language).
OPERAND: While opcode specifies what operation to perform, operand specifies where to perform
that action. The operand field generally contains the source and destination of the data. In some
cases only source or destination will be available instead of both. The operand will be either
address of the data, or data itself.

COMMENT: Always comment will begin with ; or I/symbol. To improve the programn quality,
programmer may always use comments in the program.

2.2 ADDRESSING MODES

Various methods of accessing the data are called addressing modes.

8051 addressing modes are classified as follows.

1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
5. Relative addressing.
6. Absolute addressing.
7. Long addressing.
8. Indexed addressing.
9. Bit inherent addressing.
10. Bit direct addressing.
1. Immediate addressing.
In thís addressing mode the data is provided as a part of instruction itself. In other words
data immediately follows the instruction.
Eg. MOV A,#30H
ADD A, #83 # Symbol indicates the data is immediate.
14
 Microcontrollers
4Sem ECE/ICE

2. Register addressing.
In this addressing mode the register will hold the data. One of the eight general registers
(ROto R7) can be used and specified as the operand.
Eg. MOV A,RO
ADD A,R6
RO - R7 will be selected from the current selection of register bank. The default register bank will be hank 0.
3. Direct addressing
There are two ways to access the internal memory. Using direct address and indirect address, Using
direct addressing mode we can not only address the internal memory but SFRs also. In direct addressing, an 8
bit internal data memory address is specified as part of the instruction and hence, it can specify the address
only in the range of 00H to FFH. In this addressing mode, data is obtained directly from the memory.
Eg. MOV A,60h
ADD A,30h
4. Indirect addressing
The indirect addressing mode uses a register to hold the actual address that will be used in data
movement. Registers RO and R1 and DPTR are the only registers that can be used as data pointers. Indirect
addressing cannot be used to refer to SFR registers, Both RO and R1 can hold8 bit address and DPTR can hold
16 bit address.
Eg. MOV A,@RO
ADD A,@R1
MOVX A,@DPTR
5. Indexed addressing.
In indexed addressing either the program counter (Pg, or the data pointer (DTPR)-s
used to hold the base address, and the Ais used to hold the offset address. Adding the value of the
base address to the value of the offset address forms the effective address. Indexed addressing is
used with JMP or MOvCinstructions, Look up tables are easily implemented with the help of index
addressing.
Eg. MOVC A, @A+DPTR I/ copies the contents of memory location pointed by the sum of the
accumulator A and the DPTR into accumulator A.
MOVC A, @A+PC 1/copíes the contents of memorylocation pointed bythe sum of the
accumulator Aand the program counter into accumulator A.
6. Relative Addressing.
Relative addressing is used only with conditional jump instructions. The relative address,
(offset), is an 8 bit signed number, which ís automatically added to the PC to make the address of
the next instruction. The 8 bít signed offset value gíves an address range of +127 to -128 locations.
The jump destination is usually specified using a label and the assembler calculates the jump offset
accordingly. The advantage of relative addressing ís that the programn code is easy to relocate and
the address ís relatíve to posítion in the memory.
Eg SJMP LOOP1
JC BACK
7. Absolute addressing
Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute Call)
instructions. These are 2 bytes ínstructions. The absolute addressing mode specifies the lowest 11
bit of the memory address as part of the instruction. The upper 5 bit of the destination address are

15
Microcontrollers 4 Sem ECE/TCE

the upper 5 bit of the current program counter. Hence, absolute

addressing allows branching only
within the current 2 Kbyte page of the program
Eg. AJMP LOOP1 mémory.
ACALL LOOP2

8. Long Addressing
The long addressing mode is used with the instructions LJMP and LCALL. These are 3byte
instructions. The address specifiesa full 16 bit destination address so that ajump or acallcan be
made to a location within a 64 Kbyte code memory space.
Eg. LÊMP FINISH
LCALL DELAY

9. Bit Inherent Addressing

In thisaddressing, the address of the flag which contains the operand, is implied in the opcode
of the instruction.
Eg. CLRC ; Clears the carry flag to 0

10. Bit Direct Addressing

In this addressing mode the direct address of the bit is specified in the instruction. The RAM
space 20H to 2FH and most of the special function registers are bit addressable. Bit address values
are between 00H to 7FH.
Eg. CLR 07h Clears the bit 7 of20h RAM space
SETB 07H Sets the bit 7 of 20H RAM space.
2.3 INSTRUCTION SET.
1. Instruction Timings
The 8051internal operations and external read/write operations are controlled by the oscillator
clock.
T-state, Machine cycle and Instruction cycle are terms used in instruction timings.
T-state is defined as one subdivision of the operation performed in one clock period. The terms "T
state' and 'clock period' are often used synonymously.
Machine cycle is defined as 12 oscillator periods. Amachine cycle consists of six states and each
state lasts for twooscillator periods. An instruction takes one to four machiñe cycles to execute an
instruction. Instruction cycle is defined as the time required for completing the execution of an
instruction. The 8051 instruction cycle consists of one to four machine cycles.
Eg. If 8051 microcontroller is operated with 12 MHz oscillator, find the execution time for the
following four instructions.
1. ADDA, 45H
2. SUBB A, #55H
3. MOV DPTR, #2000H
4. MUL AB
Since the oscillator frequency is 12 MHz, the clock period is, Clock period =1/12 MHz =0.08333 uS.
Time for1machine cycle = 0.08333 uSx 12 =1 uS.
Instruction No. of machine cycles Execution time
1. ADDA, 45H 1 1us

16
 instructions.
transfer
Data
In Instructions
The 8051 2. Microcontrollers
this
instructions
instructions
Logical
5. 4. 3. 2. 1. MULAB
4. 3. 2.
6.Branch instructions
h. g. d. C b. a.
group, instructions
Subroutine Arithmetic Data
Bit instructions #2000H
DPTR,
MOV SUBB
Move Moveaddressing
indirectMoveaddressing MoveaddressingindirectMove indirect) Move Move Move manipulation
transfer A,
iii. i . R1,A
MOV i.
the
i . i.@R0,A MOVX
MOVXA,@R1
i . i. i . i. i . i. MOVA,i . 65H i. MOVA,
#45H i. R4,A MOV i. i.
MOV i. A,R7 #55H
the the the the the an the
the instructions of
@A+DPTR
MOVC MOVC
A, MOV MOV MOV MOV MOV MOV #51HMOVR6, MOVA,R2
contents contents contents 8051
contents contents immediate contents contents instructions
A, 45H, 47H, 45H, R3, A, 30H,
@RO instructions can
@A+PC 65H
@RO 65H R2 #44H
of of of of ofa of
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program an memory a 8 broadly
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to to a or of
an to the 2
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MOVX@DPTR,Aexternal
iv. iii. memory iv. iii. vi. a
location memory following headings.
A,@DPTR
MOVX MOV #0F5A2H
MOVDPTR,
MOV
#0E8H
@RO,
MOV
MOVlocation
memory location @R1, 45H, DPTR,
using location types.
A Ausing
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direct ECE/TCESem 4
using (direct
direct
and direct
and or
17
 Microcontrollers

instructions
withExchange i.
Exchange
digit.k. contentThe of j.
4 PUSH
POP 4POP 1POP 6 PUSH PUSH 1 6#OF3H
MOVR4, #12H MOVR6,
MOVR1, #25H Push
order the
A,54h
XCHii. . DPTR +
A RO
R1
or A
A,@RO
XCHDA,@R1
i XCHD
. i. contents
A,XCHR3 i. and PC
+
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níbble XCHA,@R1
Pop
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Exchange FIG. A,
MOVORI A,
Instructions
MOVAddressing
destination [01]=[09]=12H
[04]=[08]=25H |SP]l=08 (SP]=09
[SP]=08[R4]=F3H[R6]=25H
[R1]=12H (SP]=07
internal , (SP]l=07 (SPl=09 [SP]=0A
ie.[06]=[0A]=F3H
register, Addressing MOVX A,
MOVC MOVC @DPTR
the
RAM ie., A. A,
lower @A+ Internal
@A+ RAM
location accumulator.direct [08]=|06]=25H
[0A]=[04]-F3H
[09]=[01]=121 //CONTENT
//CONTENT
//CONTENT//CONTENT
OF //CONTENT Using
order PCDPTR
memory MOV,
whichnibble
OFOFOFOF MOVX
or
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25H 12H F3H F3H 25H1 ROM and
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register.lower

18
 Dívision Eg
register.
Multiplication
byteAfter MUL Subtraction Addition instructions.
Arithmetic
Innumbers.8051TheMicrocontrollers
CYACand In CYAC
iii. i. this iii. this
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MUL AB
B,#OF5HA,#45H
MOV iv. addressing
ii. indirect and
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i. Subtract
i . i. Subtract
i . i.group, iv. addressing
ii. indirect
i . i. Add i. i.Add i . i.group, Add
This OVflags SUBBSUBBSUBB SUBB SUBB SUBB SUBBSUBB A, ADD ADDC ADD ADD can
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Ins
 Microcontrollers
DIV
Eg.
unsigned
DA accumulator
LogicalOR Logical
AND Logical Decrement: Increment:
A AB.
(Decimal A,#45H
B,#OFSHMOV MOV
DIVAB
destination,
source:
ORL destination,
source:
ANL leaving
ANL ANLlogically ANL instructions DEC A initial In will INC INC A Eg
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reset decrements cause
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MOVR1, DA
A,ADDA
R1 MOV MOV A
two Adjust instruction
DA
A,ADDA If If
instruction
AND the to it upper lower BCD remainder
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[A]B]=1BH
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 4 Sem ECE/TCE
Microcontrollers

affected. " OR " instruction

leaving the resulting value in destination. The value in source is not
logically OR the bits of source and destination.
ORL A, #DATA ORL A, Rn
ORL A,DIRECT ORL A,@R0
ORL DIRECT,A ORL DIRECT, #DATA

Logical Ex-OR
XRL destination, source: XRL does a bitwise "EX-OR"operation between source and
destination, leaving the resulting value in destination. The value in source is not affected. " XRL "
instruction logically EX-OR the bits of source and destination.
XRL A,#DATA XRL A,Rn
XRL A,DIRECT XRL A,@Ri
XRL DIRECT,A XRL DIRECT, #DATA

Logical NOT

CPL complements operand, leaving the result in operand. If operand is a single bit then the state of
the bit willbe reversed. If operand is the Accumulator then allthe bits in the Accumulator will be
reversed.

CPL A, CPL C, CPL bit address

SWAP A- Swap the upper nibble and lower nibble of A.

Rotate Instructions

RRA
This instruction is rotate right the accumulator. Its operation is illustrated below. Each bit is shifted one
location to the right, with bit 0 going to bit 7.

765 4 3 2 1 0
ACC

RLA
Rotate left the accumulator. Each bit is shifted one location to the left, with bit 7 going to bit 0

765 4 3 2 1
ACC

RRCA
Rotate right through the carry. Each bit is shifted one location to the right, with bit Ogoing into the carry bit in
thePSW, while the carry was at goes into bit 7

C765 43 210
ACC

RLC A
Rotate left through the carry. Each bit is shifted one location to the left, with bit 7 going into the carry bit in
the PSW, while the carry goes into bit 0.

C 765 4 3 2 1 0
ACC

21
Microcontrollers 4 Sem ECE/TCE

Branch (jUMP) Instructions

Jump and Call Program Range

There are 3 types of jump instructions. They are:
1. Relative Jump
2. Short Absolute Jump
3. Long Absolute Jump

Relative Jump
Jump that replaces the PC (program counter) content with a new address that is greater than (the
address following the jump instruction by 127 or less) or less than (the address following the jump
by 128 or less) is called a relative jump. Schematically, the relative jump can be shown as follows:

128

Relatlve
Jump Next Jump instruction
range Instruction KXX X

127

The advantages of the relative jump are as follows:

1. Only 1byte of jump address needs to be specified in the 2's complement form, ie. For
jumping ahead,the range is 0 to 127 and for jumping back, the range is -1 to-128.
2. Specifying only one byte reduces the size of the instruction and speeds up program
execution.
3. The program with relative jumps can be relocated without reassembling to generate
absolute jump addresses.

Disadvantages of the absolute jump: -

1. Short jump range (-128 to 127 from the instruction following the jump instruction)
Instructions that use Relative Jump

SJMP <relative address>; this is unconditional jump

The remaining relative jumps are conditional jumps
JC<relative address>
JNC <relative address>
JB bit, <relative address>
JNB bit, <relative address>
JBC bit, <relative address>
CJNE <destination byte>, <source byte>, <relative address>
DJNZ <byte>, <relative address>
JZ <relative address>
JNZ <relative address>

Short Absolute Jump

In this case only 11bits of the absolute jump address are needed. The absolute jump address is
calculated in the following manner.

22
 4Sem ECE/TCE
Microcontrollers
each. The
space is divided into 32 pages of 2 kbyte
menory
o0S 64 kbyte of program
hexadecimal addresses of the pages are given as follows:

Page (Hex) Address (Hex)

00 0000- 07FF
01 0800 - 0FFF
02 1000 - 17FF
03 1800 - 1FFF

1E FO00 - F7FF
1F F800- FFFF

counter (PC) hold the page number and the lower

It can be seen that the upper 5bits of the program absolute address is formed by taking
11bits of the PC hold the address within that page. Thus, an and attaching the
the jump
page numbers of the instruction (from the program counter) following
specified 11bits to it to form the 16-bit address.
Advantage: The instruction length becomes 2 bytes.

Example of short absolute jump:

ACALL <address 11>
AJMP <address 11>

Long Absolute Jump/Call

Applications that need to access the entire program memory from 0000H to FFFFH use long
absolute jump. Since the absolute address has to be specified in the op-code, the instruction length
is 3bytes (except for JMP @A+DPTR), This jump is not re-locatable.

Example: -
LCALL <address 16>
LJMP <address 16>
JMP @A+DPTR

Another classification ofjump instructions is

1. Unconditional Jump
2. Conditional Jump

1. The unconditional jump is a jump in which control is transferred unconditionally to the target location.
a. LJMP (long jump). This is a 3-byte instruction. First byte is the op-code and second and third
bytes represent the 16-bit target address which is any memory location from 0000 to FFFFH
eg: LJMP 3000H
b. AJMP: this causes unconditional branch to the indicated address, by loading the 11 bit address to
0-10 bits of the program counter. The destination must be therefore within the same 2K blocks.
C. SJMP (short jump). This is a 2-byte instruction. First byte is the op-code and second byte is the
relative target address, 00 to FFH (forward +127 and backward -128 bytes from the current PC
value), To calculate the target address of a short jump, the second byte is added to the PC value
which is address of the instruction immediately below the jump.

23
 4SemHCE/TCE
Microcontrollers

2. Conditional Jump instructions.

JBC Jump ifbit 1and clear bit
Jump if bit 0
INB
Jump ifbit 1
|B
Jump ifcY 0
JNC
Jump ifCY 1
JC Jump ifbyte ldata
CJNE reg, #data
byte
CJNE A,byte Jump ifADecrement and Jump ifA 0
DÊNZ Jump ifA 0
JNZ Jump ifA0

All conditional jumps are short jumps.

Bit level jump instructions:
true, it jurmps to the
the conditions of thebit and if condition is
Bit level JUMP instructions will check jumps are relative jumnps.
address specified in the instruction.All the bit
address specified.
JB bit, rel ;jump if the direct bit is set to the relative
relative address specified.
ijump if the direct bit is clear to the
JNB bit, rel relative specified and then clear the bit.
address
JBC bit, rel ijump if the direct bit is set to the

Subroutine CALL And RETURN Instructions

Subroutines are handled by CALL and RET instructions

There are two types of CALL Ínstructions

1. LCALL address(16 bit)

located at the indicated 16 bít
This is long call instruction which unconditionally calls the subroutine
address. This is a 3 byte instruction. The lCALL instruction works as follows.
LCALL resides is say, 0x3254;
a. During execution of LCALL, [PC] =(PC]+3; (if address where
during execution of this instruction (PC]= 3254h+ 3h = 3257h
b. [SP]=[SP]+1; (if SPcontains default value 07, then SP increments and [SPl=08
C. [SPJ] =[PC7-o]; (lower byte of PC content ie, 57 will be stored in memory location 08.
d. [SP]=(SP]+1; (SP increments again and [SPl-09)
e. [SPIj =[PCisl: (higher byte of PC content ie., 32 will be stored in memory location 09.
With these the address (0x3254) which was in PCis stored in stack.
f. [PC]= address (16 bit); the new address of subroutine is loaded to PC. No flags are affected.
2. ACALL address(11bit)
This is absolute call instruction which unconditionally calls the subroutine located at the indicated 11
bit address. This is a 2 byte instruction, The SCALL 0nstruction works as follows.
a. during
During execution
execution ofof this
SCALL, (PC] =(PC|+2: (Ifaddress where LCALL. resides is say, Ox8549;
instruction [PC] =8549h+ 2h 854Bh
b. (SPl=(SP]+1;(if SP contains default value 07, then SP increments and (SP]=08
C. [SPJ] =(PCol; (lower byte of PC content le., 4B willbe stored in memory location 08,
d. (SP]=(SP]+1;(SP increments again and [SP]=09)
e. [(SPIJ] =(PCiso); (higher byte of PC content ie., 85 will be stored in
memory location 09.
With these the address (0x854B)which was in PC is stored in stack.

24
Microcontrollers 4 Sem ECE/TCE

f. [PC1oo]= address (11 bit); the new address of subroutine is loaded to PC. No flags are
affected.
RET instruction
RET instruction pops top two contents from the stack and load it to PC.
B. [PC1sa] = [[SP]] ;content of current top of the stack will be moved to higher byte of PC.
h. [SP]=[SP]-1; (SP decrements)
1. [PC7-0] = [SP]l :content of bottom of the stack will be moved to lower
/. [SP]=[SP]-1; (SP decrements again) byte of PC.

Bit manipulation instructions.

8051 has 128 bit addressable memory. Bit
addressable SFRs and bit addressable PORT pins. It is possible to
perform following bit wise operations for these bit addressable locations.
1 LOGICAL AND
a. ANL C,BIT (BIT ADDRESS) LOGICALLY AND' CARRY AND CONTENT OF BIT ADDRESS, STORE
b. ANLC, /BIT; RESULT IN CARRY
;LOGICALLY AND' CARRY AND COMPLEMENT OF
CONTENT OF BIT ADDRESs, STORE RESULT IN CARRY
2. LOGICAL OR
ORL C,BIT (BIT ADDRESS) LOGICALLY OR CARRY AND CONTENT OF BIT ADDRESS, STORE RESULT IN
b ORL C, /BIT; CARRY
3. CLR bit ;LOGICALLY OR' CARRY AND COMPLEMENT OF CONTENT OF BIT ADDRESS,
STORE RESULT IN CARRY
a CLR bit
b. CLRC CONTENT OF BIT ADDRESS SPECIFIED WILL BE
CLEARED.
4. CPL bít :CONTENT OF CARRY WILLBE CLEARED.
CPL bit
b CPLC
;CONTENT OF BIT ADDRESS SPECIFIED WILL BE
; CONTENT OF CARRY WILL BE COMPLEMENTED.
COMPLEMENTED.

25
 $1 inshrchon Synt
Emha.
Module-9
Microcontrollers
4 Sem ECE/TCE

UNIT 3
3.1 ASSEMBLER DIRECTIVES.

Assembler directives tell the assembler to do something other than

an instruction. In assembly language creating the machine code for
to programming, the assembler directives instruct the assembler
1. Process subsequent assembly
2. Define program constants language instructions
3. Reserve space for variables
The following are the widely used 8051
assembler directives.
ORG (origin)
The ORG directive is used to indicate the
starting address. It can be used only when the
program counter needs to be changed. The number that comes after ORG can be either in
hex or in decimal.
Eg: ORG 0000H ;Set PC to 0000.

EQUand SET
EQUand SET directives assign numerical value or
name. register name to the specified symbol
EQUis used to define a constant without storing
defined with EQU should not be redefined. information in the memory. The symbol
SET directive allows redefinition of
symbols at a later stage.
DB (DEFINE BYTE)
The DB directive is used to define an 8 bit data.
DB directive initializes memory with 8
values. The numbers can be in decimal, binary, hex bit
after the decimal number is optional, but for or in ASCII formats. For decimal, the 'D'
requíred. For ASCII, the number is written in binary and hexadecimal, 'B' and "H are
quotation marks (LIKE This).
DATA1: DB 40H ;hex
DATA2: DB 01011100B
DATA3: DB 48 ;binary
;decimal
DATA4: DB 'HELLOW" ; ASCII
END

The END directive signals the end of

program to the assembler. Any text in thetheassembly
assembly module. It indicates the end of the
file that
is ignored. If the END
statement is missing, the assembler willappears after the END directive
generate an error message.
Microcontrollers 4 Sem ECE/TCE

3.2 ASSEMBLY LANGUAGE PROGRAMS.

1. Write a program to add the values of lo cations 50H and 51H and
store the result in locations
in 52h and 53H.

ORG 0000H ; Set program counter 000OH

MOV A.50H ; Load the contents of Memory location 50H into A
ADD ADD A,51H
;Add the contents of memory 51H with CONTENTS A
MOV 52HA :Save the LS byte of the result in 52H
MOV A. #00 ;Load 00H into A
ADDC A #00 ;Add the immediate data and carry to A
MOV 53HA ;Save the MS byte of the result in location 53h
END

2. Write a program to store data FFH into RAM memory locations 50H to
58H using direct
addressing mode
ORG 0000H ;Set program counter 0000H
MOV A, #OFFH ; Load FFH into A
MOV 50H, A Store contents of Ain location 50H
MOV 51H, A ;Store contents of A in location 5IH
MOV 52H, A ;Store contents of Ain location 52H
MOV53H, A ;Store contents of A in location 53H
MOV 54H, A ;Store contents of A in location 54H
MOV 55H, A ;Store contents of A in lo cation 55H
MOV 56H, A ;Store contents of A in location 56H
MOV 57H, A ;Store contents of A in location 57H
MOV 58H, A ;Store contents of A in location 58H
END

3. Write a program to subtract a 16 bit

store the result in locations 40H and number stored at locations 51H-52H from
41H. Assume that the least significant byte55H-56H and
result is stored in low address. If the result is of data or the
ORG 000OH positive, then store 00H, else store 01H in 42H.
;Set program counter 0000H
MOV A, 55H ;Load the contents of memory location 55 into A
CLRC ;Clear the borrow flag
SUBB A,5 1H ;Sub the contents of
MOV 40H, A
memory 51H from contents of A
;Save the LSByte of the result in
MOV A, 56H ;Load the contents of location 40H
SUBB A, 52H memory location 56H into A
;Subtract the content of
memory 52H from the
MOV 41H, :Save the MSbyte of the result in location 415. content A
MOV A, #00 ;Load 005 into A
ADDC A, #00 ;Add the immediate data
and the carry flag to A
MOV 42H, A ;If result is positive,
END store00H, else store OlH in 42H

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Microcontrollers 4Sem ECE/TCE

4. Write a program to add two 16 bit numbers stored at locations 51H-52H and 55H-56H and
store the result in locations 40H, 41H and 42H. Assume that the least significant byte of
data and the result is stored in low address and the most significant byte of data or the result
is stored in high address.

ORG 0000H ;Set program counter 0000H

MOV A,51H ;Load the contents of memory location 51H into A
ADD A,55H ;Add the contents of 55H with contents of A
MOV40H,A ;Save the LS byte of the result in location 40H
MOV A,52H ; Load the contents of 52H into A
ADDC A,56H ; Add the contents of 56H and CY flag with A
MOV 41H,A ;Save the second byte of the result in 41H
MOVA,#00 ; Load 0OH into A
ADDC A, #00 ; Add the immediate data 00H and CY to A
MOV 42H,A ; Save the MS byte of the result in location 42H
END

5. Write a program to store data FFH into RAM memory locations 50H to 58H using indirect
addressing mode.
ORG 0000H ;Set program counter 0000H
MOVA, #0FFH ;Load FFH into A
MOV RO, #50H ;Load pointer, R0-50H
MOV R5, #08H ;Load counter, R5-08H
Start:MOV @R0, A :Copy contents of A to RAM pointed by RO
INCR0 ;Increment pointer
DJNZ R5, start ;Repeat until R5 is zero
END
6. Write a program to add two Binary Coded Decimal (BCD) numbers stored at locations 60 H
and 61H and store the result in BCD at memory locations 52H and 53H. Assume that the
least significant byte of the result is stored in low address.

ORG O000H ;Set program counter 00004

MOV A,60H ; Load the contents of memory location 6,0 Hinto A
ADD A,61H ;Add the contents of memory location 61H with contents of A
DA A ;Decimal adjustment of the sum in A
MOV 52H, A ;Save the least significant byte ofthe result in location 52H
MOV A,#00 ; Load00H into .A
ADDC A,#00H ;Add the immediate data and the contents of carryflag to A
MOV 53H,A ;Save the most significant byte of the result in location 53:,
END

7. Write a program to clear 10 RAM locations starting at RAM address 1000H.

ORG 0000H ;Set program counter 0000H
MOVDPTR, #100OH ;Copy address 1000H to DPTR
CLRA ;Clear A
MOV R6, #0AH ;Load 0AH to R6
again: MOVX @DPTR,A ;Clear RAM location pointed by DPTR
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4 Sem ECE/TCE
Microcontrollers

INC DPTR ;Increment DPTR

DÊNZ R6, again ;Loop untlcounter lR6=0
END
8. Write a programto compute 1+2 +3+N(say Nu15)and save the sum at70H
ORG 0000H Set program counter 0000H
NEQU15
MOV RO, #00 ;Clear R0
CLR A ; Clear A
again: INC RO ;Increment RO
ADD A, RO ;Add the contents of RO with A
CJNE RO, #N, again ; Loop until counter, R0, N
MOV 70H,A ; Savethe result in location 7OH END
9. Write a program to multiply two 8 bit numbers stored at locations 70H and 71H and store the
result at nmemory locations 52H and 53H. Assume that the least significant byte of the result is
stored in low address.
ORG 0000H; Set program counter 00 OH
MOV A, 70H; Load the contents of memory location 70h into A
MOV B, 71H; Load thecontents of memory location 71H into B
MUL AB ;Perform multiplication
MOV 52H,A; Save the least significant byte of the result in location 52H MOV 53H,B ; Save the most
significant byte of the result in location 53
END
10. Ten 8bit numbers are stored in internal data memory from location 5oH. Write a
program to increment the data.
Assume that ten 8 bit numbers are stored in in tern al data memory from location 50H, hence
RO or R1 must be used as a pointer.
The program is as follows.
L OPT 0000H
MOV RO,#50H
MOV R3,#0AH
Loopl: INC@RO
INC RO
DJNZ R3, 1oopl END
END
11. Write a program to find the average of five 8bit numbers. Store the result in H.
(Assume that after adding five 8 bit numbers, the result is 8 bit only).
ORG 0000H
MOV 40H,#05H
MOV 41H,#55H
MOV 42H,#06H
MOV 43H,#1AH
MOV 44H,#09H
MOV RO,#40H
MOV R5,#05H
MOV B,R5
CLRA
Loop: ADD A,@RO
INC RO

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Microcontrollers 4Sem ECE/TCE

DÊNZ RS,Loop
DIV AB
MOV 55H,A END
12. Write a program to find the cube of an 8 bit number program is as follows
ORG 0000H
MOV R1,#N
MOV A,RI
MOV B,RI
MUL AB //SQUARE IS COMPUTED
MOV R2, B
MOV B, RI
MUL AB
MOV 50,A
MOV 51,B
MOV A,R2
MOV B, R1
MUL AB
ADD A, 51H
MOV 51H, A
MOV 52H, B
MOVA, # 00H
ADDC A, 52H
MOV 52H, A //CUBEIS STORED IN 52H,51H,50H
END

13. Write a program to exchange the lower nibble of data present in external memory 6000H and
6001H

ORG 0000H ; Set program counter 00h

MOV DPTR, #6000H ; Copy address 600OH to DPTR
MOVX A, @DPTR ; Copy contents of 60008 to A
MOV RO, #45H ; Load pointer, R0=45H
MOV @RO, A ; Copy cont of A to RAM pointed by 80
INC DPL ; Increment pointer
MOVX A, @DPTR ;Copy contents of 60018 to A
XCHD A, @RO : Exchange lower nibble of A with RAM pofnted by RO
MOVX @DPTR, A ; Copy contents of A to 60018
DEC DPL ; Decrement pointer
MOV A, @RO ; Copy cont of RAM pointed by RO to A
MOVX @DPTR, A ; Copy cont of A to RAM pointed by DPTR
END

14. Write a program to count the number of and o's of 8 bit data stored in
location 6000H.
ORG 00008 ; Set program counter 00008
MOV DPTR, #6000h ;Copy address 6000H to DPTR
MOVX A, @DPTR ;Copy number to A
MOV RO, #08 ; Copy 08 in RO
MOV R2, #00 Copy 00 in R2
MOV R3, #00 ; Copy 00 in R3
CLR C ;Clear carry flag
BACK: RLC A ; Rotate A through carry fla8

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Microcontrollers 4 Sem ECE/TCE

JC NEXT ; If CF = 1, bran ch to next

INC R2 ; 1f CF = 0, increment R2 AJMP NEXT2
NEXT: INC R3 ; 1f CF = 1, increment R3
NEXT2: DJNZ RO,BACK ; Repeat until RO is zero
END

15. Write a program to shift a 24 bit number stored at 57H-55H to the left logically four places.
Assume that the least significant byte of data is stored in lower address.
ORG 0000H ;Set program counter 0000h
MOV R1,#04 ;Set up loop count to 4
again: MOV A,55H ;Place the least significant byte of data in A
CLRC ;Clear tne carry flag
RLC A ;Rotate contents of A(55h) left through
MOV 55H,A carry
MOV A,56H
RLC A ;Rotate contents of A(56H) left
MOV 56H,A through carry
MOVA,57H
RLC A ; Rotate contents of A
MOV 57H,A (57H) left through carry
DJNZ R1,again ; Repeat until R1 is
END zero
16. Two 8 bit numbers are
stored in location 1000h and
Write a program to find the GCD of 1001h of
the nunbers and store the external data memory.
ALGORITHM result in 2000h.
Step 1 :Initialize external data
Step 2 :Load Aand TEMP with the memory with data and DPTR with address
Step 3 :Are the two operands operands
Step 4 :Is (A) greater equal?Ifyes, go to step 9
than (TEMP) ?Ifyes, go to step
Step 5
Step 6 :Exchange
(A) with (TEMP) such that A
:Perform contains the bigger
Step 7 :If the division operation (contents of Awith contents of number
remainder
Step 8 :Move the
is zero, go to step 9 TEMP)
Step 9 :Save the remainder into Aand go to step 4
ORG 0000H contents ;TEMP in memory and terminate the program
'of
Set program counter
TEMP EQU 70H 0000H
TEMPI EQU71H
MOV DPTR, #1000H ;Copy
MOVX A,@DPTR address 100011 toDPTR
;Copy First
MOV TEMP, A ;Copy First number to A
MOVX A, @DPTR number to temp INC
LOOPS:CjNE A, TEMP,LOOP1 :(A) /= ;Copy Second number to A DPTR
AJMP LOOP2 (TEMP) branch to LOOP1
LOOP1: JNC LOOP3 :(A)= (TEMP) branch to L00P2
NOV TEMPI, A :(A)>
MOV A, TEMP :(A)<(TEMP) (TEMP) branch to LOOP3
LOOP3: MOV TEMP, TEMPI exchange (A) with (TEMP)
MOV B, TEMP
DIV AB
MOV A, B ;Divide (A) by
CJNE A,#00, LOOPS ; Move (TEMP)
LOOP2:
MOV A,TEMP :(A)/=00 remainder to A
MOV DPTR, #2000H
branch LOOPS
to
MOVX @DPTR, A
END ;Store the result in 2000H

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