Chapter 2 • Digital Logic 71
6. Given the following Karnaugh map, which one of the 9. Consider the circuit shown below. The output of a 2:1
following represents the minimal Sum-Of-Products of MUX is given by the function ( ac + bc).
the map?
1 a a
wx 00 01 11 10 2:1 g 2:1
yz MUX MUX f
00 0 × 0 × 0 b
c
01 × 1 × 1 b c
11 0 × 1 0 x1
x2
10 0 1 × 0
Which of the following is true?
(a) xy + yz (b) wx y + xy + xz
(a) f = x1 + x2 (b) f = x1 x2 + x1 x2
(c) wx + yz + xy (d) xz + y
(c) f = x1 x2 + x1 x2 (d) f = x1 + x2
(GATE 2001: 1 Mark)
(GATE 2001: 2 Marks)
7. Consider the following circuit with initial state Q0 =
Q1 = 0. The D flip–flops are positive edged triggered and 10. Consider the circuit given below with initial state Q0 = 1,
have set up times 20 nanosecond and hold times 0. Q1 = Q2 = 0. The state of the circuit is given by the value
4Q2 + 2Q1 + Q0
D1 Q1 Y
X D0
D0 Q0 D1 Q1 D2 Q2
Q0
Clock Clock
Consider the following timing diagrams of X and C; the
clock period of C ≥ 40 nanosecond. Which one is the LSB MSB
correct plot of Y ?
Clock
C Which one of the following is the correct state sequence
of the circuit?
(a) 1,3,4,6,7,5,2 (b) 1,2,5,3,7,6,4
X
(c) 1,2,7,3,5,6,4 (d) 1,6,5,7,2,3,4
(a) (GATE 2001: 2 Marks)
11. Minimum sum of product expression for f (w, x, y, z)
(b)
shown in Karnaugh-map below is
(c)
wx 00 01 11 10
yz
(d)
00 0 1 1 0
(GATE 2001: 2 Marks) 01 × 0 0 1
8. The 2’s complement representation of ( −539)10 in hexa- 11 × 0 0 1
decimal is 10 0 1 1 ×
(a) ABE (b) DBC (a) xz + yz (b) xz + zx
(c) DE5 (d) 9E7
(c) xy + zx (d) None of the above
(GATE 2001: 2 Marks)
(GATE 2002: 1 Mark)
Ch wise GATE_CSIT_CH02_Digital Logic.indd 71 11/13/2018 9:43:02 AM
72 GATE CS AND IT Chapter-wise Solved Papers
12. The decimal value 0.25 17. Consider the following multiplexor where 10, 11, 12,
(a) is equivalent to the binary value 0.1 13 are four data input lines selected by two address line
(b) is equivalent to the binary value 0.01 combinations A1A0 = 00, 01, 10, 11 respectively and f is
the output of the multiplexor. EN is the Enable input.
(c) is equivalent to the binary value 0.00111…
(d) cannot be represented precisely in binary 10 4 to 1
(GATE 2002: 1 Mark) 11 Multiplexor
12
13. The 2’s complement representation of the decimal value 13 Output f(x, y, z) = ?
−15 is A1
(a) 1111 (b) 11111 A0
(c) 111111 (d) 10001 EN
(GATE 2002: 1 Mark)
The function f (x, y, z) implemented by the above circuit is
14. Sign extension is a step in (a) xyz (b) xy + z
(a) floating point multiplication (c) x + y (d) None of the above
(b) signed 16 bit integer addition (GATE 2002: 2 Marks)
(c) arithmetic left shift
18. Let f ( A, B ) = A + B. Simplified expression for function
(d) converting a signed integer from one size to another
f ( f (x + y, y), z) is
(GATE 2002: 1 Mark)
(a) x+z (b) xyz
15. In 2’s complement addition, overflow (c) xy + z (d) None of the above
(a) is flagged whenever there is carry from sign bit (GATE 2002: 2 Marks)
addition
19. Assuming all numbers are in 2’s complement
(b) cannot occur when a positive value is added to a
representation, which of the following numbers is divis-
negative value
ible by 11111011?
(c) is flagged when the carries from sign bit and previ-
ous bit match (a) 11100111 (b) 11100100
(d) None of the above (c) 11010111 (d) 11011011
(GATE 2002: 1 Mark) (GATE 2003: 1 Mark)
16. Consider the following logic circuit whose inputs are 20. Consider an array multiplier for multiplying two n bit
functions f1, f2, f3 and output is f. numbers. If each gate in the circuit has a unit delay, the
total delay of the multiplier is
f1(x, y, z) (a) Θ(1) (b) Θ(log n)
(c) Θ(n) (d) Θ(n2)
f2(x, y, z) f(x, y, z)
(GATE 2003: 1 Mark)
f3(x, y, z) = ? 21. The following is a scheme for floating point number rep-
resentation using 16 bits.
Given that
Bit position 15 14.....9 8.....0
f1 ( x, y, z ) = ∑ (0,1, 3, 5) , s e m
f 2 ( x, y, z ) = ∑ (6, 7) , and sign exponent mantissa
f ( x, y, z ) = ∑ (1, 4, 5) , Let s, e, and m be the numbers represented in binary
in the sign, exponent, and mantissa fields, respectively.
f3 is Then the floating point number represented is
(a) ∑ (1, 4, 5) (b) ∑ (6, 7) ⎧( −1) s (1 + m × 2 −9 )2e − 31 if the exponent ≠ 111111
⎨
⎩ 0 otherwise
(c) ∑ (0,1, 3, 5) (d) None of the above
What is the maximum difference between two succes-
(GATE 2002: 2 Marks)
sive real numbers representable in this system?
Ch wise GATE_CSIT_CH02_Digital Logic.indd 72 11/13/2018 9:43:05 AM
