UNIT-3

DIGITAL ELECTRONICS:
Overview of Number Systems:

A system that is used for representing numbers is called the number system. In digital
electronics, the numbers are used to represent the information. Hence, it is important to learn
and understand different types of number systems so we can easily represent and interpret the
information in the form of numbers.
There are several types of number systems and the basis of this classification is
the base or radix of the number system. The base or radix of the number system is the total
number of symbols used to denoted the numbers in the number system.

Types of Number Systems:

Depending on the base or radix, number systems can be classified into the following four major
types –
 Decimal Number System
 Binary Number System
 Octal Number System
 Hexadecimal Number System

Decimal Number System

The system of numbers which has base or radix 10, i.e. uses total 10 symbols to represent
numbers of the system is called decimal number system. The symbols used in the decimal
number system are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9; where each of these symbols assigned a specific
value.
The decimal number system is a position value system, which means the value of the digit
depends on the position in the number. To understand the concept of position value system,
consider the following example.
Let a decimal number 1234 which has total four digits, this number can also be written as
follows −

Hence, from this example, we can see that the value of different digits of the number
depends on their respective position in the number.

Binary Number System

A number system with base or radix 2 is called binary number system. The binary number
system uses only 2 symbols (0 and 1) to represent binary numbers. All modern digital devices
like computers, combinational circuits, sequential circuits, etc. use the binary number system
to operate.
We can convert a binary number into its equivalent decimal number as follows −
Let a binary number 1101 and we have to convert it into an equivalent decimal number, then −

Octal Number System

A number system which has base 8 is called an octal number system. Therefore, the octal
number system uses 8 symbols, (0, 1, 2, 3, 4, 5, 6, 7) to represent the number.
An octal number can be converted into an equivalent decimal number as follows −
Let an octal number 124 and we need to find its equivalent in decimal, then

Hexadecimal Number System

The number system with base or radix 16 is called as hexadecimal number system. Thus, the
hexadecimal number system uses 16 symbol to represent numbers. These symbols are 0, 1, 2,
3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. Where, A = 10; B = 11; C = 12; D = 13; E = 14; F = 15.
The hexadecimal number system is extensively used in microprocessors and microcontrollers.
The most significant advantage of hexadecimal number system over binary number system is
that the hexadecimal numbers are much shorter in size than the binary numbers, which makes
these hexadecimal numbers more readable.
Though, just like binary and octal numbers, we may convert the hexadecimal numbers into
decimal numbers. To understand the conversion process, consider the following example.
Let 1AF is a hexadecimal number, we can convert it into the equivalent decimal number as
follows −

Conversion Table
The following table shows the decimal numbers from 0 to 15 and their equivalent binary, octal
and hexadecimal numbers –

Logic gates Including Universal Gates:

Logic gates are an important concept if you are studying electronics. These are important
digital devices that are mainly based on the Boolean function. Logic gates are used to carry out
logical operations on single or multiple binary inputs and give one binary output. In simple
terms, logic gates are the electronic circuits in a digital system.

Types of Basic Logic Gates

There are several basic logic gates used in performing operations in digital systems. The
common ones are

 OR Gate
 AND Gate
 NOT Gate
 XOR Gate
Additionally, these gates can also be found in a combination of one or two. Therefore, we get
other gates, such as NAND Gate, NOR Gate, EXOR Gate and EXNOR Gate.
OR gate:
In an OR gate, the output of an OR gate attains state 1 if one or more inputs attain state 1.
The Boolean expression of the OR gate is Y = A + B, read as Y equals A ‘OR’ B.
The truth table of a two-input OR basic gate is given as
A B Y

0 0 0
0 1 1
1 0 1
1 1 1
AND gate
In the AND gate, the output of an AND gate attains state 1 if and only if all the inputs are in
state 1.

The Boolean expression of AND gate is Y = A.B

The truth table of a two-input AND basic gate is given as
A B Y

0 0 0
0 1 0
1 0 0
1 1 1
NOT gate:
In a NOT gate, the output of a NOT gate attains state 1 if and only if the input does not attain
state 1.

The Boolean expression is

̅
𝒀=𝑨
It is read as Y equals NOT A.
The truth table of NOT gate is as follows

A Y
0 1
1 0
When connected in various combinations, the three gates (OR, AND and NOT) give us basic
logic gates, such as NAND and NOR gates, which are the universal building blocks of digital
circuits.
NAND gate:
This basic logic gate is the combination of AND and NOT gates.

The Boolean expression of the NAND gate is

𝒀 = ̅̅̅̅̅̅
𝑨∙𝑩
The truth table of a NAND gate is given as
A B Y

0 0 1
0 1 1
1 0 1
1 1 0

NOR Gate:

This gate is the combination of OR and NOT gates.

𝒀 = ̅̅̅̅̅̅̅̅
𝑨+𝑩
The truth table of a NOR gate is as follows
A B Y

0 0 1
0 1 0
1 0 0
1 1 0
Exclusive –OR gate:
In an XOR gate, the output of a two-input XOR gate attains state 1 if one adds only input and
attains state 1.

The Boolean expression of the XOR gate is

𝑌 = 𝐴. 𝐵̅ + 𝐴̅. 𝐵 or
𝒀 =𝑨⊕𝑩
The truth table of an XOR gate is
A B Y

0 0 0
0 1 1
1 0 1
1 1 0
Exclusive –NOR gate:
In the XNOR gate, the output is in state 1 when both inputs are the same, that is, both 0 or both
1.

The Boolean expression of the XNOR gate

𝒀 = ̅̅̅̅̅̅̅̅̅
𝑨 ⊕ 𝑩=𝑨 ⊙ 𝑩
̅∙𝑩
𝒀 = (𝑨 ∙ 𝑩) + 𝑨 ̅
The truth table of an XNOR gate is given below
A B Y

0 0 1
0 1 0
1 0 0
1 1 1

Application of Logic Gates

Logic gates have a lot of applications, but they are mainly based on their mode of operations
or their truth table. Basic logic gates are often found in circuits such as safety thermostats,
push-button locks, automatic watering systems, light-activated burglar alarms and many other
electronic devices.
One of the primary benefits is that basic logic gates can be used in various combinations if the
operations are advanced. Besides, there is no limit to the number of gates that can be used in a
single device. However, it can be restricted due to the given physical space in the device. In
digital integrated circuits (ICs), we will find an array of the logic gate area unit.
BCD Codes:
Digital Codes or Binary Codes: A group of binary digits is known as a binary code or a
digital code.
Numeric Code:
Digital code represented by the number is known as a numeric code
Classification:
The codes are broadly classified into
1. Weighted code
2. Non-weighted code
3. Reflective code
4. Sequential code
5. Error detecting and correcting codes

Weighted codes: The weighted codes are those where the position of each number represent a
specific weight. In these codes each decimal digit is represented by a group of four bits. In
weighted codes, each digit is assigned a specific weight according to its position. For example,
in 8421/BCD code, 1001 the weights of 1, 1, 0, 1 (from left to right) are 8, 4, 2 and 1
respectively. Examples:8421, 2421

Non-weighted codes: The non-weighted codes are not positionally weighted. In other words,
codes that are not assigned with any weight to each digit position. Example: Excess-3(XS-3)
and Gray Codes.
Excess-3 code: Excess-3 codes are Non-weighted and can be obtained by adding 3 to each
decimal digit then it can be represented by using 4 bit binary number for each digit. An
Excess-3 equivalent of a given binary number is obtained using the following steps:
  Find the decimal equivalent of the given binary number.
 Add +3 to each digit of decimal number.
 Convert the newly obtained decimal number back to binary number to get required excess-3
equivalent.
 These are following excess-3 codes for decimal digits –

Gray code: Gray code is non weighted code, which means there is no specific weight
assigned to the bit position.
Applications:
 It is used in analog to digital conversion, input / output devices.
 It is used to reduce errors that occur in data transmission.
Binary to gray code conversion :
 The MSB of the gray code is the MSB of the binary number.
 Perform XOR operation between the MSB and the second significant bit of the binary
number.
 XOR the second and third significant bits of the binary, the result is the third significant
bit of the gray code.
 Repeat the process till the end of the LSB of the binary number
Reflective codes:
A code is said to be reflective when the code for 9 is the complement for the code 0, 8 for 1, 7
for 2, 6 for 3 and 5 for 4.

Eg: 2421 code and Excess-3 code

Sequential codes:
A code is said to be sequential when each succeeding code is binary number greater than its
preceding code.

Eg: 8421 code and Excess-3 code

Parity codes:
The parity code is used for the purpose of detecting errors during the transmission of binary
information. The parity code is a bit that is included with the binary data to be transmitted.
The inclusion of a parity bit will make the number of 1’s either odd or even. Based on the
number of 1’s in the transmitted data, the parity code is of two types.
 Even parity code
 Odd parity code
Even parity code:
If the total number of 1 bits in the word including parity bit is Even, then such a parity code is
said to be even parity code.
Odd parity code:
If the total number of 1 bits in the word including parity bit is odd, then such a parity code is
said to be odd parity code.
The following table shows the even and odd parity bits for 4 bit data word
The simple parity will not detect two errors within the same word. To detect and correct error
in the word Hamming code is used.
Hamming code:
Hamming code is a set of error-correction codes that can be used to detect and correct the
errors that can occur when the data is moved or stored from the sender to the receiver. It is
technique developed by R.W. Hamming for error correction.
Selecting the number of parity bits:
The number of parity bits to be chosen depends on word length.
Let n be the number of information or data bits, then the number of parity bits P is
determined from the following formula,
2𝑃 ≥ 𝑛 + 𝑃 + 1
Example:
If 4-bit information is to be transmitted, then n=4. The number of parity bits is determined by
the trial and error method
Let P=2, we get,
22 ≥ 4 + 2 + 1
The above equation implies 4 not greater than or equal to 7. So let’s choose another value of
P=3.
23 ≥ 4 + 3 + 1

Now, the equation satisfies the condition. So number of parity bits, P=3.

The bit designation is

Problem:
Data bits 1011 must be transmitted. Construct the even parity, seven bit Hamming code for
this data

P1 checks for even parity of bit positions 1,3,5 and 7. For even parity P1 must be 1

P2 checks for even parity of bit positions 2,3,6 and 7. For even parity P2 must be 0

P3 checks for even parity of bit positions 4,5,6 and 7. For even parity P3 must be 0
BOOLEAN ALGEBRA:
Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol
used to represent a logical quantity. Any single variable can have a 1 or a 0 value. The
complement is the inverse of a variable and is indicated by a bar over variable (overbar). For
example, the complement of the variable A is A. If A = 1, then A = 0. If A = 0, then A = 1. The
complement of the variable A is read as "not A" or "A bar." Sometimes a prime symbol rather
than an over bar is used to denote the complement of a variable; for example, B' indicates the
complement of B. A literal is a variable or the complement of a variable.
Boolean Addition
Recall from part 3 that Boolean addition is equivalent to the OR operation. In Boolean algebra,
a sum term is a sum of literals. In logic circuits, a sum term is produced by an OR operation
with no AND operations involved. Some examples of sum terms are A + B, A + B, A +
B + C, and A + B + C + D.
A sum term is equal to 1 when one or more of the literals in the term are 1. A sum term is equal
to 0 only if each of the literals is 0.
Example
Determine the values of A, B, C, and D that make the sum term

A + B + C + D equal to 0.
Boolean Multiplication
Also recall from part 3 that Boolean multiplication is equivalent to the AND operation. In
Boolean algebra, a product term is the product of literals. In logic circuits, a product term is
produced by an AND operation with no OR operations involved. Some examples of product
terms are AB, A𝐵̅, ABC, and ABCD.
A product term is equal to 1 only if each of the literals in the term is 1. A product term is equal
to 0 when one or more of the literals are 0.
Example
Determine the values of A, B, C, and D that make the product term ABCD equal to 1.

LAWS AND RULES OF BOOLEAN ALGEBRA

■ Laws of Boolean Algebra:
The basic laws of Boolean algebra-the commutative laws for addition and multiplication, the
associative laws for addition and multiplication, and the distributive law-are the same as in
ordinary algebra.
Commutative Laws
The commutative law of addition for two variables is written as
A+B = B+A
This law states that the order in which the variables are ORed makes no difference. Remember,
in Boolean algebra as applied to logic circuits, addition and the OR operation are the same.
Fig.(1) illustrates the commutative law as applied to the OR gate and shows that it doesn't
matter to which input each variable is applied. (The symbol ≡ means "equivalent to.").
 Fig: 1: Application of commutative law of addition:
The commutative law of multiplication for two variables is A.B = B.A This law states that the
order in which the variables are AND ed makes no difference. Fig.(2), il1ustrates this law as
applied to the AND gate.

Fig:(2)Application of Commutative law

Associative Laws :
►The associative law of addition is written as follows for three variables:
A + (B + C) = (A + B) + C
This law states that when ORing more than two variables, the result is the same regardless of
the grouping of the variables. Fig.(3), illustrates this law as applied to 2-input OR gates.

Fig:(3):Application of associative law

The associative law of multiplication is written as follows for three variables:
A(BC) = (AB)C
This law states that it makes no difference in what order the variables are grouped when
ANDing more than two variables. Fig.(4) illustrates this law as applied to 2-input AND gates

Fig: 4: Application of associative law of multiplication:

Distributive Law:
The distributive law is written for three variables as follows:
A(B + C) = AB + AC
This law states that ORing two or more variables and then ANDing the result with a single
variable is equivalent to ANDing the single variable with each of the two or more variables
and then ORing the products. The distributive law also expresses the process of factoring in
which the common variable A is factored out of the product terms, for example,
AB + AC = A(B + C).
Fig.(5) illustrates the distributive law in terms of gate implementation.
X=A(B+C) X=AB+AC
Fig:(5) Application of distributive law
Rules of Boolean Algebra
Table:1 lists 12 basic rules that are useful in manipulating and simplifying Boolean
expressions. Rules 1 through 9 will be viewed in terms of their application to logic gates. Rules
10 through 12 will be derived in terms of the simpler rules and the laws previously discussed.

Table:1
Rule 1. A + 0 = A
A variable ORed with 0 is always equal to the variable. If the input variable A is 1, the output
variable X is 1, which is equal to A. If A is 0, the output is 0, which is also equal to A. This
rule is illustrated in Fig.(6), where the lower input is fixed at 0.

A+0=A
Fig:6:
Rule 2. A + 1 = 1
A variable ORed with 1 is always equal to 1. A 1 on an input to an OR gate produces a 1 on
the output, regardless of the value of the variable on the other input. This rule is illustrated in
Fig.(7), where the lower input is fixed at 1.

X=A+1=1
 Fig:7:
Rule 3. A . 0 = 0
A variable ANDed with 0 is always equal to 0. Any time one input to an AND gate is 0, the
output is 0, regardless of the value of the variable on the other input. This rule is illustrated in
Fig.(8), where the lower input is fixed at 0.

Fig:(8)
Rule 4. A . 1 = A
A variable ANDed with 1 is always equal to the variable. If A is 0 the output of the AND gate
is 0. If A is 1, the output of the AND gate is 1 because both inputs are now 1s. This rule is
shown in Fig.(9), where the lower input is fixed at 1.

Fig:(9)
Rule 5. A + A = A
A variable ORed with itself is always equal to the variable. If A is 0, then 0 + 0 = 0; and if A
is 1, then 1 + 1 = 1. This is shown in Fig.(10), where both inputs are the same variable.

Fig:(10)
̅
Rule 6. A + 𝐴 = 1
A variable ORed with its complement is always equal to 1. If A is 0, then 0 + 0 = 0 + 1 = 1. If
A is l, then 1 + 1 = 1+ 0 = 1. See Fig.(11), where one input is the complement of the other.

Fig:(11)
Rule 7. A . A = A
A variable ANDed with itself is always equal to the variable. If A = 0, then 0.0 = 0; and if A =
1. then 1.1 = 1. Fig.(12) illustrates this rule

.
Fig:(12)
Rule 8. A . 𝐴̅ = 0
A variable ANDed with its complement is always equal to 0. Either A or 𝐴̅ will always be 0:
and when a 0 is applied to the input of an AND gate. The output will be 0 also. Fig.(13)
illustrates this rule.
 Fig:(13)
Rule 9 A =𝐴 ̿
The double complement of a variable is always equal to the variable. If you start with the
variable A and complement (invert) it once, you get 𝐴̅. If you then take 𝐴̅ and complement
(invert) it, you get A, which is the original variable. This rule is shown in Fig.(14) using
inverters.

Fig:(14)
Rule 10. A + AB = A
This rule can be proved by applying the distributive law, rule 2, and rule 4 as follows:
A + AB = A( 1 + B) Factoring (distributive law)
= A . l Rule 2: (1 + B) = 1
= A Rule 4: A .1 = A
The proof is shown in Table -2, which shows the truth table and the resulting logic circuit
simplification.

Table:2
Rule 11. ̅
𝐴 + 𝐴𝐵 = 𝐴 + 𝐵
This rule can be proved as follows:
𝐴 + 𝐴̅𝐵 = (𝐴 + 𝐴𝐵) + 𝐴̅𝐵 Rule10: A=A+AB
= (𝐴𝐴 + 𝐴𝐵 + 𝐴̅𝐵 Rule7:A=AA
= 𝐴𝐴 + 𝐴𝐵 + 𝐴𝐴̅ + 𝐴̅𝐵 Rule8: adding 𝐴𝐴̅ = 0
̅
= 𝐴(𝐴 + 𝐵)+ 𝐴(𝐴 + 𝐵)
= (𝐴 + 𝐴̅)(𝐴 + 𝐵) Rule6:𝐴 + 𝐴̅ = 0
=𝐴+𝐵
The proof is shown in Table-3, which shows the truth table and the resulting logic circuit
simplification.
 Table-3.
Rule 12. (A + B)(A + C) = A + BC
This rule can be proved as follows:
(A + B)(A + C) = AA + AC + AB + BC Distributive law
= A + AC + AB + BC Rule 7: AA = A
= A( 1 + C) + AB + BC Rule 2: 1 + C = 1
= A. 1 + AB + BC factoring (distributive law)
= A(1 + B) + BC Rule 2: 1 + B = 1
= A. 1 + BC Rule 4: A . 1 = A
= A + BC
The proof is shown in Table -4, which shows the truth table and the resulting logic circuit
simplification:

Table -4
DEMORGAN'S THEOREMS
De-Morgan, a mathematician who knew Boolean, proposed two theorems that are an important
part of Boolean algebra. In practical terms. De-Morgan's theorems provide mathematical
verification of the equivalency of the NAND and negative-OR gates and the equivalency of the
NOR and negative-AND gates, which were discussed in part 3. One of De-Morgan's theorems
is stated as follows
One of De-Morgan's theorems is stated as follows:
The complement of a product of variables is equal to the sum of the complements of the
variables,
Stated another way,
The complement of two or more ANDed variables is equivalent to the OR of the complements
of the individual variables.
The formula for expressing this theorem for two variables is
̅̅̅̅ = 𝑋̅ + 𝑌̅
𝑋𝑌
De-Morgan's second theorem is stated as follows:
The complement of a sum of variables is equal to the product of the complements of the
variables.
Stated another way,
The complement of two or more ORed variables is equivalent to the AND of the
complements of the individual variables,
The formula for expressing this theorem for two variables is
̅̅̅̅̅̅̅̅
𝑋 + 𝑌 = 𝑋̅𝑌̅
Fig.(15) shows the gate equivalencies and truth tables for the two
equations above.

Fig:15 Gate equivalencies and the corresponding truth tables that illustrate De-Morgan's
theorems.
As stated, De-Morgan's theorems also apply to expressions in which there are more than two
variables. The following examples illustrate the application of De-Morgan's theorems to 3-
variable and 4-variable expressions
Example
Apply De-Morgan's theorems to the expressions XYZ and X + Y + z.
𝑋𝑌𝑍 = 𝑋̅ + 𝑌̅ + 𝑍̅
̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑋 + 𝑌 + 𝑍 = 𝑋̅ 𝑌̅𝑍̅
Example
Apply De-Morgan's theorems to the expressions WXYZ and W + X + y + z.
𝑊𝑋𝑌𝑍 = 𝑊 ̅ + 𝑋̅ + 𝑌̅ + 𝑍̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑊+𝑋+𝑌+𝑍 =𝑊 ̅ 𝑋̅𝑌̅𝑍̅
Applying De-Morgan's Theorems
The following procedure illustrates the application of De-Morgan's theorems and Boolean
algebra to the specific expression
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵𝐶̅ ) + 𝐷(𝐸 + 𝐹̅ )
Step l. Identify the terms to which you can apply De-Morgan's theorems, and think of each
term as a single variable. Let 𝐴 + ̅̅̅̅𝐵𝐶 = 𝑋 and 𝐷(𝐸 + 𝐹̅ ) = 𝑌.
Step:2. Since ̅̅̅̅̅̅̅̅̅̅̅
𝑋 + 𝑌 += 𝑋̅ 𝑌̅,
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵𝐶̅ ) + 𝐷(𝐸 + 𝐹̅ ) = (𝐴 + 𝐵𝐶̅ )𝐷(𝐸 + 𝐹̅ )
Step 3. Use rule 9 (A = A) to cancel the double bars over the left term (this is not part of De-
Morgan's theorem).
(𝐴 + 𝐵𝐶̅ )𝐷(𝐸 + 𝐹̅ ) = (𝐴 + 𝐵𝐶̅ )(𝐷(𝐸 + 𝐹̅ ))
Step 4. Applying De-Morgan's theorem to the second term
(𝐴 + 𝐵𝐶̅ )(𝐷(𝐸 + 𝐹̅ )) = (𝐴 + 𝐵𝐶̅ )(𝐷 + (𝐸 + 𝐹̅ ))
Step 5. Use rule 9 (𝐴 = 𝐴̿) to cancel the double bars over the 𝐸 + 𝐹̅ part of the term.
(𝐴 + 𝐵𝐶̅ )(𝐷 + ̅̅̅̅̅̅̅̅
𝐸 + 𝐹̅ ) = (𝐴 + 𝐵𝐶̅ )(𝐷
̅ + 𝐸 + 𝐹̅ )

Simple combinational Circuits:

Half Adder:
An adder is a digital circuit that performs addition of numbers. Adders are classified into two
types. One is Half Adder, and another one is known as Full Adder .The half adder adds two
binary digits and produces two outputs as sum and carry. It consists of one XOR logic gate
producing “SUM” and one AND gate producing “CARRY” as outputs.

Fig: Block Diagram of Half-Adder:

There are two inputs and two outputs in a Half Adder. Inputs are named as A and B, and the
outputs are named as Sum (S) and Carry (C).

Fig: Half-Adder Logic Circuit diagram:

Equation for Sum and Carry:
̅+𝐀
𝐒𝐮𝐦 = 𝐀 ⊕ 𝐁 = 𝐀𝐁 ̅𝐁
𝐂𝐚𝐫𝐫𝐲 = 𝐀 ∙ 𝐁
Half-Adder Truth Table

Limitations of Half-Adder:
The major drawback of HALF ADDER circuit is that it can only add two inputs and if there is
any carry it is neglected. Thus, the process is incomplete. To overcome this drawback Full
Adder is designed.
Full-Adder:
A full adder is a combinational circuit that performs an addition operation on three binary
digits. It consists of three inputs and two outputs. The first two inputs are A and B and the third
input is an input carry designated as Cin . The output carry is designated as Cout and the normal
output is designated as S.

Fig: Block Diagram of Full-Adder:

A full adder circuit can be implemented using two half adders and one OR gate. The first half
adder will be used to add A and B to produce a partial Sum and the second half adder can be
used to addCin to the Sum produced by the first half adder to get the final S output. If any of
the half adder produces a carry, there will be an output carry. So, Cout will be an OR function
of the half adder Carry outputs.
Since a full adder has the previous carry as an input, it can be used to add multi-digit binary
numbers. The multi-digit binary numbers are added by a cascading connection of multiple full
adders. The number of full adders in cascade connection is equal to the number of digits to be
added.
Since a full adder has the previous carry as an input, it can be used to add multi-digit binary
numbers. The multi-digit binary numbers are added by a cascading connection of multiple full
adders. The number of full adders in cascade connection is equal to the number of digits to be
added.

Fig: Logic Circuit diagram of Full-Adder:

Full-Adder logic equation for Sum and Carry:
𝐒𝐮𝐦 = 𝐀 ⊕ 𝐁 ⊕ 𝐂𝐢𝐦
𝐂𝐨𝐮𝐭 = 𝐀𝐁 + (𝐀 + 𝐁)𝐂𝐢𝐦

Truth Table of Full-Adder

Applications of Half-Adder and Full-Adder:
There are many applications of Half Adder and Full Adder. These circuits are used basically
in building of any digital electronics device. Half adder and Full adder can be used to make
other arithmetical and logical circuits like ALU. These circuits are mainly designed for the
addition of binary number, but they can be used in various other applications like binary code
decimal, address decoding, table index calculation, etc.
Sequential Circuits:
Classification of digital circuits: The digital circuits are broadly classified into two types
(1) Combinational Circuits
(2) Sequential Circuits
Combinational Circuits:
In combinational circuits output at any point of time depends on the output at that point of
time.
The logic gate is the basic building block of combinational circuits.
There is no memory requirement in combinational circuits.

Eg: Adders , Subactors, Multipliers, Multiplexers, Encoders, Decoders, DE multiplexers

etc.
2) Sequential Circuits:
In sequential circuits the output depends on the present input as well as past output.
Memory is a basic building block of sequential circuits. Memory is used to store the past
outputs.
The sequential is combination of combinational circuit and memory
Eg: Latches, Flip-Flops, registers and counters.
Difference between combinational and sequential circuits.
 Combinational circuits Sequential Circuits
1)Combinational circuits are faster 1)Sequential Circuits are slower than
combinational
2)Combinational circuits are easy to design 2) Sequential Circuits are comparatively
difficult to design
3)Memory unit is not required 3) Memory is unit is required to store the
past outputs.

4)For Combinational circuits the output 5)In Sequential Circuits the output depends
depends on the input at instant of time on present input and past output

Classification of Sequential Circuits:

Sequential circuits are classified into two types
(1) Synchronous sequential circuits.
(2) Asynchronous sequential circuits
Difference between Synchronous sequential circuits and Asynchronous sequential circuits
Synchronous sequential circuits Asynchronous sequential circuits

1)In Synchronous sequential circuits the 1) In Asynchronous sequential circuits the

change in input can affect the memory change in input can affect the memory at
elements upon activation of clock signal any point of time.

2)Memory elements are clocked flip-flops 2)Memory elements are un-clocked flip-
flop
3) Speed of the clock is the maximum 3) Since Clock is not present the circuits are
speed of circuit. faster than synchronous.
4) These circuits are easy to design. 5) Asynchronous circuits are difficult to
design

Flip-Flop:
A Flip-Flop is a memory element that is capable of storing one bit of information.
A Flip-Flop has two outputs as shown:

A Flip-Flop can maintain a binary state for an unlimited period of time as long as-
 Power is supplied to the circuit
  Or until it is directed by an input signal to switch states.
A Flip-Flop is also called as Bistable Multivibrator because it has two stable states either 0 or
1.
A Flip-Flop is an edge triggered device

Flip-Flop Types:
Flip-Flop are different types depending on how their inputs and clock pulses cause transition
between states.
There are 4 types of Flip-Flops
1) SR Flip-Flop.
2) JK Flip-Flop
3) D Flip-Flop
4) T Flip-Flop
SR Flip-Flop:
 SR Flip-Flop is the simplest type of SR Flip-Flops.
 It stands for Set Reset Flip-Flop.
 It is a clocked Flip-Flop.
Construction of SR Flip-Flop By using NOR Latch.
This method of constructing SR Flip-Flop uses-
 NOR Latch
 Two AND gates
Logic Circuit:
The logic circuit for SR Flip-Flop constructed using NOR latch is shown below.
 Logic Symbol:
The logic symbol for SR flip-flop as shown below.

Logic Operation of the SR Flip-Flop is as shown below:

The above Truth Table can be reduced as:

INPUTS OUTPUTS REMARKS
CLK S R 𝑸𝒏 𝑸𝒏+𝟏 State and condition
(Present State) (Next State)
1 0 0 X 𝑄𝑛 (No Change) Hold State Condition
S=R=0
1 0 1 X 0(Reset) Reset State Condition
S=0,R=1
1 1 0 X 1(Set) Set State S=1,R=0
1 1 1 X Intermediate Indeterminate state
S=R=1
 Characteristic Equation:
𝑸𝒏+𝟏 = 𝐒 + 𝑸𝒏 𝑹|

Excitation Table:
The excitation table of any flip-flop is drawn using its truth table.
What is excitation table?
For a given combination of present state 𝑄𝑛 and the next state𝑄𝑛+1 , excitation table tell the
inputs required.
Excitation Table:

𝑸𝒏 𝑸𝒏+𝟏 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
JK-Flip-Flop:
JK-Flip-Flop is a refined & improved version of SR-Flip-Flop that has been introduced to
solve problems of indeterminate state that occur in SR-Flip-Flop when both inputs are 1.
In JK-Flip-Flop
 Input J behaves like input S of SR-Flip-Flop which was meant to set the flip-flop.
 Input K behaves like input R of SR-Flip-Flop which was meant to reset the flip-flop.
Construction of JK-Flip-Flop by using SR-Flip-Flop Constructed from NOR Latch-
This method of constructing JK-Flip-Flop uses-
 SR-Flip-Flop constructed from NOR Latch.
 Two other connections
Logic Circuit:-
The logic circuit for JK-Flip-Flop constructed using SR Flip-Flop constructed from NOR
Latch is as shown below-
Logic Symbol:-
The logic symbol of JK flip-flop is as shown below:

Operation of JK flip-flop:
Operation of JK flip-flop is shown below:-
INPUTS OUTPUTS
CLK J K 𝑸𝒏 𝑸𝒏+𝟏
(Present State) (Next State)
1 0 1, 0 0
1 0 1 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

The above truth may be reduced as-

INPUTS OUTPUTS REMARKS
CLK J K 𝑸𝒏 𝑸𝒏+𝟏 State and condition
(Present State) (Next State)
1 0 0 X 𝑄𝑛 (No Hold State Condition
Change) J=K=0
1 0 1 X 0(Reset) Reset State Condition
J=0,K=1
1 1 0 X 1(Set) Set State J=1,K=0
1 1 1 X 𝑄𝑛′ Toggle State J=K=1

Characteristic Equation:
𝑸𝒏+𝟏 = 𝑄𝑛′ + 𝑄𝑛′ 𝐾 ′
Excitation Table:
 𝑸𝒏 𝑸𝒏+𝟏 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

D-Flip-Flop:
D Flip –Flops are used are used as a part of memory storage element and data processors as
well.
D Flip-Flop can be built using NOR gates or with NAND gates.
Due to its versatility they are available as IC packages.
The major applications of D-Flip-Flop are to introduce delay in timing circuit, as a buffer,
sampling data at specific intervals.
D Flip-Flop is simpler in terms of wiring connection compared to JK flip-flop. Here we are
using NAND gates for demonstrating the D flip flop.
Operation of D Flip-Flop:
Whenever the clock signal is LOW, the input is never going to affect the output state.
The clock has to be high for inputs to get active. Thus, D Flip-Flop is a controlled Bi-stable
latch where the clock signal is the control signal. Again, this gets divided into positive edge
triggered D flip-flop and negative edge triggered D Flip-Flop. Thus, the output has two stable
states based on the inputs which have been discussed below.

Truth Table of D-Flip-Flop:-

The D(Data) is the input state for the D-Flip-Flop. The Q and 𝑄′ represents the output stages
of the flip-flop. According to the table, based on the inputs the output changes its state. But,
the important thing to consider is all these can occur only in the presence of the clock signal.
This, works exactly like SR flip-flop for the complimentary inputs alone.
D Flip-Flop Circuit:
D-Flip-Flop is a better alternative that is very popular with digital electronics. They are
commonly used for counters and shift registers and input synchronization.

In the D Flip-Flops, the output can only be changed at the clock edge, and if the input
changes at other times, the output will be unaffected.
Registers:
A flip-flop is used to store single digital data.
For storing a large number of bits, the storage capacity is increased by grouping more than
one flip-flops. A Register is collection of flip-flop.
The group of flip-flops, which are used to hold or store the binary data is known as register.
If we want to store an n-bit word, we have to use n-bit bit register containing n number of
flip-flops.
The registers are used to perform different types of operations. For performing the operations,
the CPU uses these registers.
The input to the system will be stored into the registers. The result returned by the system
will be stored in the registers.
The registers which will shift the bits to the left are called “Shift left registers”. The registers
which will shift the bits to the right are called “Shift right registers”. Shift registers are
basically of following types.
These are the following operations which are performed by the registers:
1) Fetch : It is used
 To make the instructions given by users.
 To fetch the instructions stored into the main memory.
2) Decode: The decode operation is used to interpret the instructions, In decode, the
operation performed on the instructions is identified by CPU. In a simple word, the
decode operation is used to decode the operations.
3) Execute: The execution operation is used to store the result produced by the CPU into
the memory. After storing this result, it is displayed on the user screen.
Shift Registers:
Types of Shift Registers
 Serial In Serial Out shift register
 Serial In parallel Out shift register
 Parallel In Serial Out shift register
 Parallel In parallel Out shift register
 Bidirectional Shift Register
 Universal Shift Register
 Shift Register Counter
Serial In Serial Out shift register:
The shift register, which allows serial input (one bit after the other through a single data line)
and produces a serial output is known as a Serial-In Serial-Out shift register. Since there is
only one output, the data leaves the shift register one bit at a time in a serial pattern, thus the
name Serial-In Serial-Out Shift Register. The logic circuit given below shows a serial-in
serial-out shift register. The circuit consists of four D flip-flops which are connected in a
serial manner. All these flip-flops are synchronous with each other since the same clock
signal is applied to each flip-flop.

The above circuit is an example of a shift right register, taking the serial data input from the
left side of the flip flop. The main use of a SISO is to act as a delay element.
Serial In parallel Out shift register:
The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as the Serial-In Parallel-Out shift register. The logic
circuit given below shows a serial-in-parallel-out shift register. The circuit consists of four
D flip-flops which are connected. The clear (CLR) signal is connected in addition to the clock
signal to all 4 flip flops in order to RESET them. The output of the first flip-flop is connected
to the input of the next flip flop and so on. All these flip-flops are synchronous with each
other since the same clock signal is applied to each flip-flop.

The above circuit is an example of a shift right register, taking the serial data input from the
left side of the flip-flop and producing a parallel output. They are used in communication
lines where de- multiplexing of a data line into several parallel lines is required because the
main use of the SIPO register is to convert serial data into parallel data.
Parallel In Serial Out shift register:
The shift register, which allows parallel input (data is given separately to each flip flop and
in a simultaneous manner) and produces a serial output is known as a Parallel-In Serial-Out
shift register. The logic circuit given below shows a parallel-in-serial-out shift register. The
circuit consists of four D flip-flops which are connected. The clock input is directly connected
to all the flip-flops but the input data is connected individually to each flip-flop through
a multiplexer at the input of every flip-flop. The output of the previous flip-flop and parallel
data input are connected to the input of the MUX and the output of MUX is connected to the
next flip-flop. All these flip-flops are synchronous with each other since the same clock signal
is applied to each flip-flop.

A Parallel in Serial out (PISO) shift register is used to convert parallel data to serial data
Parallel In parallel Out shift register:
The shift register, which allows parallel input (data is given separately to each flip flop and
in a simultaneous manner) and also produces a parallel output is known as Parallel-In
parallel-Out shift register. The logic circuit given below shows a parallel-in-parallel-out shift
register. The circuit consists of four D flip-flops which are connected. The clear (CLR) signal
and clock signals are connected to all 4 flip-flops. In this type of register, there are no
interconnections between the individual flip-flops since no serial shifting of the data is
required. Data is given as input separately for each flip flop and in the same way, output is
also collected individually from each flip flop.
A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like
SISO Shift register it acts as a delay element.
Application of Shift Register:
 The shift registers are used for temporary data storage.
 The shift registers are also used for data transfer and data manipulation.
 The serial-in serial-out and parallel-in parallel-out shift registers are used to produce time
delay to digital circuits.
 The serial-in parallel-out shift register is used to convert serial data into parallel data thus
they are used in communication lines where demultiplexing of a data line into several
parallel lines is required.
 A Parallel in Serial out shift register is used to convert parallel data to serial data.
Counters:
A Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. Counters are used in
digital electronics for counting purpose, they can count specific event happening in the
circuit. For example, in UP counter a counter increases count for every rising edge of clock.
Not only counting, a counter can follow the certain sequence based on our design like any
random sequence 0,1,3,2… .They can also be designed with the help of flip flops. They are
used as frequency dividers where the frequency of given pulse waveform is divided. Counters
are sequential circuit that count the number of pulses can be either in binary code or BCD
form. The main properties of a counter are timing, sequencing, and counting. Counter works
in two modes
Up counter
Down counter
Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter
Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main
clock and the clock input of rest of the following flip flop is driven by output of previous flip
flops. We can understand it by following diagram-
It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock
pulse is encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is
like clock pulse for second flip flop) and so on. In this way ripples are generated through
Q0,Q1,Q2,Q3 hence it is also called RIPPLE counter and serial counter. A ripple counter is
a cascaded arrangement of flip flops where the output of one flip flop drives the clock input
of the following flip flop

2)Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives
each flip flop so output changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it
does not have cumulative delay because of same clock is given to each flip flop. It is also
called as parallel counter.
From circuit diagram we see that Q0 bit gives response to each falling edge of clock while
Q1 is dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.
Decade Counter
A decade counter counts ten different states and then reset to its initial states. A simple decade
counter will count from 0 to 9 but we can also make the decade counters which can go through
any ten states between 0 to 15 (for 4 bit counter).

Clock
Q3 Q2 Q1 Q0
pulse

0 0 0 0 0

1 0 0 0 1
 2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0

We see from circuit diagram that we have used nand gate for Q3 and Q1 and feeding this to
clear input line because binary representation of 10 is—
1010
And we see Q3 and Q1 are 1 here, if we give NAND of these two bits to clear input then
counter will be clear at 10 and again start from beginning.
Important point: Number of flip flops used in counter are always greater than equal to
(log2 n) where n=number of states in counter.