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Subject Title: DIGITAL ELECTRONICS

Subject Code: RTS302T
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1.0 Introduction to digital electronics

2.0 Number systems and codes

3.0 Logic gates and Boolean algebra

4.0 Combinational logic circuits

5.0 Latches and flip-flops

6.0 Sequential Logic Circuits

7.0 Types of memory

 1.0 INTRODUCTION TO DIGITAL ELECTRONICS
Introduction:

Digital electronics is the branch of electronics that deals with the study of digital signals
and the components that use or create them.

Digital electronics:

1. Digital electronics, or digital (electronic) circuits, represent signal by discrete bands of analog
levels, rather than by a continuous range. All levels within a band represent the same signal
state.

2. Digital electronic circuits are usually made from large assemblies of logic gates,
simple electronic representations of Boolean logic functions.

Electronics System:

Analog System Digital System

1.1 Difference b/w Analog and Digital system:

Analog system Digital system

Values are continuous Values are discrete

Nonlinear operation Linear operation

For small signals For large signals

E.g: Sound waves E.g: Digital watch

NOTES:

2
 Applications of Digital Circuits

Digital electronics or digital circuits are an integral part of electronic devices, and here are
the uses of digital circuits:

 The display of digital watches is designed based on digital circuits.

 Rocket science and quantum computing use digital electronics.

 The automatic doors work on the principle of digital electronics.

 Everyday encounters with traffic lights are based on digital circuits.

2.0 NUMBER SYSTEMS AND CODES

 Decimal
 Binary
 Octal
 Hexadecimal system
2.1 Decimal Numbers:
 Decimal notation is the writing of numbers in a base-10 numeral system.
 Decimal numbers are 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9
Binary numbers:
 Binary – 0, 1
 In computer or mathematics, the binary numeral system or base-2 numeral system
represents numeric values using two symbols: 0 and 1. More specifically, the usual base-
2 system is a positional notation with a radix of 2. Numbers represented in this system are
commonly called binary numbers
 It is denoted as 1010112
Octal numbers
 It is base 8 numeral system.
 0,1,2,3,4,5,6,7
 Octal number is denoted as 148

NOTES:

3
 Hexadecimal numbers
 It is base 16 numeral system
 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
 Hexadecimal number is denoted as 6F16
Binary Coded Decimal
Binary Coded Decimal, or BCD, is another process for converting decimal numbers into
their binary equivalents.

In the BCD numbering system, the given decimal number is segregated into chunks of four
bits for each decimal digit within the number. Each decimal digit is converted into its direct
binary form (usually represented in 4-bits).

DECIMAL NUMBER BCD

0 0000

1 0001

2 0010

3 0011

4 0100

5 0101

6 0110

7 0111

8 1000

9 1001

NOTES:

4
 2.2 1’s Complement
 Complement all the other bits

 Example

1010112 1’s complement is 0101002

2’s complement
 1’s complement plus one

 Example

1010112 1’s complement is 0101012

2.3 Base Conversion

NOTES:

5
Binary to Decimal Conversion

101102 = (1×24)+(0×23)+(1×22)+(1×21)+(0×20

0×20 = 0x1 = 0

1×21 = 1x2 = 2

1×22 = 1x4 = 4

1×23 = 1x8 = 8

1×24 = 1x16 = 16

22

NOTES:

6
 Octal to Decimal Conversion

578 = (5×81)+(7×80)

7×80 = 7x1 = 7
5×81 = 5x8 = 40
47
Hexa Decimal to Decimal Conversion

2A16 = (2×161)+(10×160)

10×160 = 10x1 = 7
2×161 = 2x16 = 16
23
Binary to Octal Conversion
The base numbers of binary and octal are 2 and 8, respectively. In a binary number, the pair of
three bits is equal to one octal digit. There are only two steps to convert a binary number into an
octal number which are as follows:

1. We have to make the pairs of three bits on both sides of the binary point. If there will be one
or two bits left in a pair of three bits pair, we add the required number of zeros on extreme sides.
2. We write the octal digits corresponding to each pair.

Example : 11101012

001 110 101

1 6 5 = Ans : 165 8

NOTES:

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 Binary to Hexa decimal Conversion
1. We have to make the pairs of four bits on both sides of the binary point. If there will be one,
two, or three bits left in a pair of four bits pair, we add the required number of zeros on extreme
sides.

2. We write the hexadecimal digits corresponding to each pair.

Example : 11111012

0111 1101

7 D = Ans : 7D 16

2.4 BCD Code:

Decimal 0 through 9 are represented by their natural binary equivalents using four bits and
each decimal digit is represented by this four-bit code individually. This code is also known as 8-
4-2-1 code where 8, 4, 2, & 1 are the weights of the four bits of the binary code of each decimal
digit to the straight binary system.

EXCESS-3 Codes

This is another form of BCD code, in which each decimal is coded into a 4-bit binary
code. The code for each decimal digit is obtained by adding decimal 3 to the natural BCD code of
the digit. For ex- decimal 2 is coded as 0010+0011=0101 in Excess-3 code.

Gray Code

It is a very useful code in which a decimal number is represented in binary form in such a

way so that each gray code number differs from preceding & the succeeding number by a

single bit. For ex- the gray code for decimal number 5 is 0111 & for
6 is 0101

– The MSB in the Gray code is the same as corresponding MSB in

the binary number.

– Going from left to right, add each adjacent pair of binary code
bits to get the next gray code bit. Discard carries.

NOTES:

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ASCII Code:

NOTES:

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 A char variable in C++ is a one-byte memory location where a single character value can
be stored. Because one byte can hold values between 0 and 255 that means there are up to 256
different characters in the ASCII character set. These are usually broken down into two groups.
The first, with values from 0 to 127 are considered the "Standard" ASCII character set. Characters
with values from 128 to 255 are the "Extended" character set.

NOTES:

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 EBCDIC Code:

Extended Binary Coded Decimal Interchange Code (EBCDIC) is an eight-bit encoding

scheme that standardizes how alphanumeric characters, punctuation and other symbols are
interpreted by a computer's operating system (OS) and applications.

3. Logic gates and Boolean Algebra

3.1 BASIC LOGIC GATES:

A logic gate is an elementary building block of a digital circuit. Most logic gates have two
inputs and one output. At any given moment, every terminal is in one of the two binary conditions
low (0) or high (1), represented by different voltage levels. The logic state of a terminal can, and
generally does, change often, as the circuit processes data. In most logic gates, the low state is
approximately zero volts (0 V), while the high state is approximately five volts positive (+5 V).

There are seven basic logic gates:

AND, OR, XOR, NOT, NAND, NOR, and XNOR.

NOTES:

11
 AND GATE: Truth Table

The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate
acts in the same way as the logical "and" operator. The output is "true" when both inputs are
"true." Otherwise, the output is "false.

OR GATE:

Truth Table

A
A+B
B

The OR gate gets its name from the fact that it behaves after the fashion of the logical
inclusive "OR." The output is "true" if either or both of the inputs are "true." If both inputs are
"false," then the output is "false."

NOTES:

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 NOT GATE:

Truth Table
A

A’ or A

logical inverter , sometimes called a NOT gate to differentiate it from other types of
electronic inverter devices, has only one input. It reverses the logic state.

NAND & NOR GATES:

NAND

NOR

The NAND gate operates as an AND gate followed by a NOT gate. It acts in the manner
of the logical operation "and" followed by negation. The output is "false" if both inputs are "true."
Otherwise, the output is "true."

The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if
both inputs are "false." Otherwise, the output is "false."

NOTES:

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 XOR AND XNOR GATES:

The XOR (exclusive-OR) gate acts in the same way as the logical "either/or." The output
is "true" if either, but not both, of the inputs are "true." The output is "false" if both inputs are
"false" or if both inputs are "true.

The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter. Its
output is "true" if the inputs are the same and "false" if the inputs are different.

3.2 Boolean operation

1. A system having two states is called “ binary system” or “digital system”.

2. Digital system exactly has two states , i.e. 0 & 1.These are usually called ‘logic states’.

3. Digital system consists of ‘Positive logic system and Negative logic system’.

4. In positive logic system,

+5V dc = High = 1 = True

+0V dc = Low = 0 = False

5. In negative logic system,

+5V dc = Low = 1 = False

+0V dc = High = 0 = True

NOTES:

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 Binary Addition:

A+B SUM CARRY

0+0 0 0

0+1 1 0

1+0 1 0

1+1 0 1

Binary Subtraction:

A-B DIFFERENCE BORROW

0- 0 0 0

0-1 1 1

1-0 1 0

1-1 0 0

Commutative Law

(a) A + B = B + A

(b) A B = B A

Associate Law

(a) (A + B) + C = A + (B + C)
(b) (A B) C = A (B C)

NOTES:

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 3.3 De Morgan's Theorem

(a) NOT A or B = NOT A NOT B (Breaking the Overbar changes the OR to an AND)

(b) NOT A = NOT A + NOT B (Breaking the Overbar changes the AND to an OR)

Note: NOT A NOT B is not the same as NOT A

4. Combinational circuits
4.1 NAND & NOR AS UNIVERSAL LOGIC GATES

1. Any logic circuit can be built using only NAND gates, or only NOR gates. They are the only
logic gate needed.
2. Here are the NAND equivalents
4.2 Half Adder:

1. Half adder is a combinational logic circuit with two inputs and two outputs.
2. The half adder circuit is designed to add two single bit binary numbers.
3. The circuit has two outputs carry and sum.

NOTES:

16
 Implementation of a Half Adder:

Truth Table:

NOTES:

17
 Full Adder:

1. Full adder is a combinational logic circuit with three inputs and two output.
2. The full adder circuit is designed to add three single bit binary numbers.
3. The circuit has two outputs carry and sum.

Implementation of Full Adder:

S = x’y’z + x’yz’ + xy’z’ + xyz,

C = xy + xz + yz

Truth Table:

Carry Input Input B Input A Carry Sum

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

NOTES:

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 Half – Subtractor:

1. Half Subtractor is a combinational logic circuit with two inputs and two outputs.
2. The half Subtractor circuit is designed to subtract two single bit binary numbers.
3. The circuit has two outputs Difference and Borrow.

Implementation of Half Subtractor:

D = A’B + AB’

B = A’B

Truth Table:

NOTES:

19
 Full – Subtractor:

1. Full Subtractor is a combinational logic with three input and two output.
2. The half Subtractor circuit is designed to subtract three single bit binary number.
3. The circuit has two outputs Difference and Borrow.

Implementation of Full Subtractor:

D = A’B’C + A’BC’ + AB’C’ + ABC

B = A’B + A’C + BC

Truth Table:

NOTES:

20
 4.3 Encoder:

1. An Encoder is a combinational circuit which has 2n input lines and n output lines.

4 to 2 Encoder

The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0, and two outputs A1 & A0.
At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the
output. The figure below shows the logic symbol of the 4 to 2 encoder.

The Truth table of 4 to 2 encoders is as follows.

INPUTS OUTPUTS

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

NOTES:

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 INPUTS OUTPUTS

0 1 0 0 1 0

1 0 0 0 1 1

Logical expression for A1 and A0:

A1 = Y3 + Y2
A0 = Y3 + Y1
The above two Boolean functions A1 and A0 can be implemented using two input OR gates :

Application of Encoder:

1. Data communication
2. Digital broadcast network

2- to-4 Binary Decoder

NOTES:

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 Decoder:

 A Decoder is a combinational circuit which has n input lines and 2n output lines.

Applications of Decoder:

1. Decoder is used in wireless remote-control system.

2. Microprocessor memory system.
3. Memory Chips.
4. Microprocessor input / output system.
5. Data multiplexing
6. Seven segment display
7. Memory address decoding.

NOTES:

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BCD to Seven Segment Decoder:

1. BCD stands for “ Binary Coded Decimal”.

2. A standard 7-segment LED display generally has 8 input connections, one for each LED
segment and one common terminal .
3. Two types 7-Segment Display are
1. Common Cathode Display (CCD)
2. Common Anode Display (CAD)
4.4 Multiplexer:
1. A multiplexer is a combinational circuit that selects one of the 2n input signals to be passed to
the single output line.
2. The selection of a particular input line is controlled by a set of selection lines.

NOTES:

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 Application of Multiplexer:

1. Telephony
2. Video Processing
3. Digital Broadcasting
4. Analog broadcasting

Demultiplexer:

1. Demultiplexer is a combinational circuit that receives information in single line and transmits
this information on one of 2n output lines.
2. The selection of a particular input line is controlled by a set of selection lines.

Application of Demultiplexer:

1. Internet
2. Computer
3. Electronics switching Board

NOTES:

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 5. LATCHES AND FLIP- FLOPS
5.1 Introduction:
1. A latch is binary storage element
2. It can store a 0 or 1
3. The most basic memory
4. Easy to build
5. Latches are built using Logic Gates (NORs, NANDs, NOT)

DEFINITION OF LATCH
The latch is a type of temporary storage device that has two stable states (bistable). It
is called as a latch, since it will hold, or latch, in either stable state. Latches are similar to
flip- flops because they are bistable devices that can reside in either of two states using a
feedback arrangement, in which the outputs are connected back to the opposite inputs. The
main difference between latches and flip-flops is in the method used for changing their state.
When a latch is enabled, its state changes immediately when its input changes. When a latch
is disabled, its state remains constant, thereby, remembering its previous value.

The types of Latches are:

1. SR Latch
2. Gated S’R’ Latch
3. D Latch
4. Gated D Latch

SR LATCH:
An active-HIGH input SR (SET-RESET) latch is formed with two cross-coupled NOR
gates, as shown in fig. The output of each gate is connected to an input of the opposite gate.

This produces the regenerative feedback

that is characteristic of all latches and flip-
flops. The latch has two outputs Q & Q’ and
two inputs, set and reset.

NOTES:

26
 SR Latch

As per truth table of NOR gate if any one input is at

logic 1 then output is logic 0.

Case 1: S = 1 and R = 0

 In this case, S input of NOR gate 2 is at logic 1.

 Hence its output, Q’ is at logic 0.
 So that its output, Q is at logic 1. Latch is

SET Case 2: R = 1 and S = 0

 In this case, R input of NOR gate 1 is at logic 1.

 Hence its output, Q is at logic 0. Latch is RESET
 Both inputs to NOR gate 2 are now at logic 0.
 So that its output, Q’ is at logic 1.

Case 3: S = 0 and R = 0 (Initially, Q=1 and Q’=0)

 With Q’ = 0, both the inputs to NOR gate 1 are at logic 0.

 So its output, Q is at logic 1.
 With Q = 1, one input of NOR gate 2 is at logic 1.
 So that its output, Q’ is at logic 0.
 This shows that when S & R both are at logic 0, the output state is NO CHANGE.
 (Initially, Q=0 and Q’=1)
 With Q’ = 1, one input of NOR gate 1 is at logic 1.
 So its output, Q is at logic 0.
 With Q = 0, both inputs to NOR gate 2 is at logic 0.
 So that its output, Q’ is at logic 1.

 In this case also there is NO CHANGE in the output state.

Case 4: S = 1 and R = 1
 Both NOT gate outputs to Logic 0 state. (Q=0 & Q’=0)
 This is called an INDETERMINATE or PROHIBITED state.

NOTES:

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  This condition violates the basic definition of a latch that requires Q to
be complement of Q’.
 Thus in normal operation this condition must be avoided by making sure that 1s
are not applied to both the inputs simultaneously.

S R Qn Qn+1 State

0 0 0 0

0 0 1 1 NO CHANGE (NC)

0 1 0 0

0 1 1 0 RESET

1 0 0 1

1 0 1 1 SET

1 1 0 X INDETERMINED

1 1 1 X STATE

Truth Table of Active High SR Latch

GATED SR LATCH:
In the SR latch we have seen that output changes occur immediately after the
input changes occur i.e. the latch is sensitive to its S and R inputs at all times. However,
it can easily be modified to create a latch that is sensitive to these inputs ONLY when an
enable input is active. Such a latch with enable input is known as Gated SR Latch. It is
shown in the Fig. The table shows the truth table for gated latch. As shown by truth
table, the circuit behaves like a SR latch when EN = 1, and retains its previous state
when EN = 0. The latch will not change until EN is HIGH; but as long as it remains
HIGH, the output is controlled by the state of the S and R inputs. The gated latch is a
level-sensitive device. In this circuit, the invalid state occurs when both S and R are
simultaneously HIGH and EN is also HIGH.

NOTES:

28
 Gated SR Latch

EN S R Qn Qn+1 State

1 0 0 0 X

1 0 0 1 X NO CHANGE (NC)

1 0 1 0 1

1 0 1 1 1 RESET

1 1 0 0 0

1 1 0 1 0 SET

1 1 1 0 0 INDETERMINED

1 1 1 1 1 STATE

0 X X 0 0

0 X X 1 1 NO CHANGE (NC)

Truth Table of Gated SR Latch

Gated SR Latch Timing Diagram

NOTES:

29
 D LATCH:
The disadvantage with the SR latch is that we need to ensure that the two inputs, S
and R, are never de-asserted at exactly the same time, and we said that we can guarantee this
by not having both of them asserted. This situation is prevented in the D latch by adding an
inverter between the original S' and R' inputs.

D Latch

This way, S' and R' will always be inverses of each other, and so, they will never be
asserted together. The circuit using NAND gates and the inverter is shown in Figure. There is
now only one input D (for data). When D = 0, then S' = 1 and R' = 0, so this is similar to
resetting the SR latch by making Q = 0. Similarly, when D = 1, then S' = 0 and R' = 1, and Q
will be set to 1. From this observation, we see that Qnext always gets the same value as the
input D and is independent of the current value of Q. Hence, we obtain the truth table for the
D latch, as shown in table.

Comparing the truth table for the D latch shown in table with the truth table for the
active low S’R’ latch shown in table., it is obvious that we have eliminated not just one, but
the rows, where S' = R'. The reason for adding the inverter to the SR-latch circuit was to
eliminate the row where S' = R' = 0. However, we still need to have the other two rows
where S' = R' = 1 in order for the circuit to remember its current value. By not being able to
set both S' and R' to 1, this D-latch circuit has now lost its ability to remember. Qnext cannot
remember the current value of Q, instead, it will always follow D. The end result is like
having a piece of wire where the output is the same as the input!

NOTES:

30
 D Qn Qn+1 State

0 0 0

0 1 0 RESET

1 0 1

1 1 1 SET

Truth Table of D Latch

‘D’ Latch Timing Diagram

GATED D LATCH

Another type of gated latch is called the D latch. It differs from the S-R latch because it has
only one input in addition to EN. This input is
called the D (data) input. Fig.contains a logic
symbol and logic diagram of a D latch.

When the D input is HIGH and the EN input is

HIGH, the latch will set. When the D input is
LOW and EN is HIGH, the latch will reset.

Gated “D” Latch

NOTES:

31
 Stated another way, the output Q follows the input D when EN is HIGH.

Gated ‘D’ Latch Timing Diagram

5.2 FLIP-FLOP & ITS TYPES:

1. A flip-flop is a one bit memory element similar to latches
2. Solves the issue of transparency of latch.
3. Latches are level sensitive memory element
4. Active when the clock = 1 (whole duration)
5. Flip-Flops are edge-triggered or edge-sensitive memory element
6. Active only at transitions; i.e. either from 0 → 1 or 1 → 0

DEFINITION OF FLIP-FLOP & LATCH V/S FLIP-FLOP

Flip-flops are synchronous Bistable devices, also known as Bistable multivibrators. In
this case, the term synchronous means that the output changes state only at a specified point
(leading or trailing edge) on the triggering input called the clock (CLK), which is
designated as a control input, C; that is, changes in the output occur in synchronization with
the clock.

NOTES:

32
 Flip-flops are edge-triggered or edge-sensitive whereas gated latches are level-sensitive.
The dynamic input indicator means the flip-flop changes state only on the edge of a clock
pulse. The types of Flip-flops are:

1. SR Flip-flop

2. D Flip-flop

3. JK Flip-flop

4. T Flip-flop

An edge-triggered flip-flop changes state either at the positive edge (rising edge) or
at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this
transition of the clock. Two types of edge-triggered flip-flops. Notice that each type can be either
positive edge-triggered (no bubble at C input) or negative edge-triggered (bubble at C input). The
key to identifying an edge-triggered flip-flop by its logic symbol is the small triangle inside the
block at the clock (C) input. This triangle is called

Types of Positive & Negative Edge Triggered Flip-flops

NOTES:

33
 NOR Gate based SR Latch Timing Diagram

5.3 FLIP-FLOP APPLICATIONS:

1. Parallel Data Storage:

A common requirement in digital systems is to store several bits of data
from parallel lines simultaneously in a group of flip-flops. For example, the group of four
flip-flops is an example of a basic 4-bit register used for data storage as shown in fig. In
digital systems, data are normally stored in groups of bits (usually eight or multiples
thereof) that represent numbers, codes, or other information.

4-Bit Parallel In Parallel Out Shift Register Logic Circuit

2. Frequency Division:
Another application of a flip-flop is dividing (reducing) the frequency of a
periodic waveform. When a pulse waveform is applied to the clock input of a D or J-K
flip-flop that is connected to toggle (D = Q or J = K = 1), the Q output is a square wave
with one-half the frequency of the clock input. Thus, a single flip-flop can be applied as a
divide-by-2 device, as is shown in fig for both a D and a J-K flip-flop. As you can see in
part (c), the flip-flop changes state on each triggering clock edge (positive edge-triggered
in this case). This results in an output that changes at half the frequency of the clock
waveform. Q is one-half the frequency of CLK.

NOTES:

34
 D-FF & JK-FF as a Divide-by-2 Counter Two D-FF’s used to divide frequency by 4

Further division of a clock frequency can be achieved by using the output of one flip-
flop as the clock input to a second flip-flop, as shown in fig. The frequency of the QA output
is divided by 2 by flip-flop B. The QB output is, therefore, one-fourth the frequency of the
original clock input. Propagation delay times are not shown on the timing diagrams. By
connecting flip- flops in this way, a frequency division of 2 n is achieved, where n is the
number of flip-flops. For example, three flip-flops divide the clock frequency by 2 3 = 8; four
flip-flops divide the clock frequency by 24 = 16; and so on.

3. Counters:
Another important application of flip-flops is in digital counters. Both flip-flops are
initially RESET. FF-A toggles on the negative-going transition of each clock pulse. The Q
output of FF-A clocks FF-B, so each time Qa makes a HIGH-to-LOW transition, FF-B
toggles. The resulting Qa and Qb waveforms are shown in the figure.

If we take QA as the least significant bit, a 2-bit sequence is produced as the flip-flops
are clocked. This binary sequence repeats every four clock pulses, as shown in the timing
diagram of fig. Thus, the flip-flops are counting in sequence from 0 to 3 (00, 01, 10, 11) and
then recycling back to 0 to begin the sequence again.

NOTES:

35
 JK flip-flops used to generate a 2-bit binary count sequence

4. Eliminate Switch Debounce or Key Debounce:

For interfacing keys to the digital systems, usually push button keys are used. These
push button keys when pressed bounces a few times, closing and opening the contacts before
providing a steady reading. Reading taken during bouncing period may be faulty. This
problem is known as Key debounce as shown in fig. The problem of key debounce is
undesirable and it must be avoided.

Switch Debouncing

One way to avoid key debounce problem is to use SR latch. The circuit used to a key bounce
with SR latch is called a Switch or Contact Debouncer. When key is at position A, the output of
SR latch is logic 1 and when key is at position B, the output of SR latch is logic 0. It is important
to note that, when key is between A & B, SR inputs are 00 and hence output does not change,

NOTES:

36
 preventing debouncing of key output. In other words, we can say that the output does not change
during transition period, eliminating key debounce.

6. SEQUENTIAL LOGIC CIRCUITS

6.1 INTRODUCTION:
A counter is probably one of the most useful and versatile subsystems in a digital
system. A counter is a sequential circuit having a limited (finite) number of states occurring in
a prescribed order. A counter is driven by a clock pulse which occurs at fixed intervals. Hence
it can be used as an instrument for measuring time and therefore period or frequency. A
counter can also be defined as ‘a sequential circuit which is used to count the number of
pulses’. Counters are well known to us as “Timers”. Counters are designed by grouping of flip
flops and applying a single clock signal to them. In simple words, the counters are those
circuits, which have the group of storage elements called flip flops to hold the count.

NEED OF COUNTERS:
Counting means incrementing or decrementing the values of an operator, with respect
to its previous state value. So to perform the mathematical operation we use no devices other
than counters. We cannot perform this action (counting) with any other logic devices rather
than counters.

6.2 ASYNCHRONOUS COUNTERS:

The term asynchronous refers to events that DO NOT have a fixed time relationship
with each other and, generally, do not occur at the same time. An asynchronous counter is one
in which the flip-flops (FF) within the counter do not change states at exactly the same time
because they DO NOT have a common clock pulse. Hence asynchronous counters are also
known as “Ripple Counters” The ripple counter is simple and straightforward in operation and
its construction usually requires a minimum of hardware. It does, however, have a speed
limitation.
NOTES:

37
 Each flip-flop is triggered by the previous flip-flop, and thus the counter has a cumulative settling
time. Hence these are also called “Serial Counter”.

4-bit Asynchronous Counter Logic Circuit

SYNCHRONOUS COUNTERS:

The term synchronous refers to events that have a fixed time relationship with each
other. A synchronous counter is one in which all the flip-flops in the counter are clocked at
the same time by a common clock pulse. J-K flip-flops are used to illustrate most synchronous
counters. D flip-flops can also be used but generally require more logic because of having no
direct toggle or no-change states. Hence an increase in speed of operation can be achieved by
use of a parallel or synchronous counters. Here, every flip-flop is triggered by the clock (in
synchronism), and thus settling time is simply equal to the delay time of a single flip-flop.
The increase in speed is usually obtained at the price of increased hardware.

NOTES:

38
 4-bit Synchronous Counter Logic Circuit

ASYNCHRONOUS COUNTERS OR RIPPLE COUNTER:

The counter in which external clock is ONLY given to the first Flip-flop & the
succeeding Flip-flops are clocked by the output of the preceding flip-flop is called
asynchronous counter or ripple counter. The name ripple counter is because the clock signal
ripples its way from the first stage of Flip-flops to the last stage. Asynchronous Counters can
easily be made from Toggle or D-type flip-flops. They can be used to implement the “divide-
by-n” counter circuits. Truncated counters can produce any modulus number count.

LIMITATIONS:

The limitations of Asynchronous Counters:

 An extra “re-synchronizing” output flip-flop may be required.

 To count a truncated sequence not equal to 2n, extra feedback logic is required.
 Counting a large number of bits, propagation delay by successive stages may become
undesirably large.
 This delay gives them the nickname of “Propagation Counters”.
 Counting errors occur at high clocking frequencies.
 Hence Synchronous Counters are preferred due to faster operation and more
reliable as they use the same clock signal for all flip-flops.

NOTES:

39
 6.3 UP COUNTERS:

 Connect the CLK input to the Q output with the opposite polarity.

Ripple Up Counter Design

DOWN COUNTERS:

 Connect the CLK input to the Q output with the same polarity.

Ripple Down Counter Design

2- BIT BINARY RIPPLE UP COUNTER

1. UP COUNTER USING FLIP-FLOP:

2-Bit Binary Ripple Up Counter

NOTES:

40
 Binary State Sequence for a 2-Bit Ripple Up Counter

Logic Circuit: - Fig. shows a 2-bit up counter connected for asynchronous operation. Here
the clock (CLK) is applied to the clock input (C) of the first flip-flop (FF0) ONLY, which is
always the least significant bit (LSB). The second flip-flop, FF1, is triggered by the ̅̅𝑄0̅
output of FF0. FF0 changes state at the positive-going edge of each clock pulse, but FF1
changes only when
triggered by a positive-going transition of the 0𝑄̅ output of FF0. Because of the inherent
propagation delay time through a flip-flop, a transition of the input clock pulse (CLK) and a
transition of the 0𝑄̅ output of FF0 can never occur at exactly the same time. Therefore, the
two flip-flops are never simultaneously triggered, so the counter operation is asynchronous.
The 2- bit counter exhibits four different states, (22 = 4). Also, notice that if Q0 represents the
least significant bit (LSB) and Q1 represents the most significant bit (MSB), the sequence of
counter states represents a sequence of binary numbers as listed in Table.

Since it goes through a binary sequence, the counter in Fig. is a binary counter. It
actually counts the number of clock pulses up to three, and on the fourth pulse it recycles to its
original state (Q0 = 0, Q1 = 0). The term recycle is commonly applied to counter operation; it
refers to the transition of the counter from its final state back to its original state.

Timing Diagram: -

Let’s examine the basic operation of the asynchronous counter of Fig. by applying
four clock pulses to FF0 and observing the Q output of each flip-flop. Fig. illustrates the
changes in the state of the flip-flop outputs in response to the clock pulses. Both flip-flops
are connected for toggle operation

(D = Q’) and are assumed to be initially RESET (Q LOW).

 The positive-going edge of CLK1 (clock pulse 1) causes the Q0 output of FF0 to

NOTES:

41
 go HIGH, as shown in timing diagram. At the same time the ̅̅𝑄0̅ output goes
LOW, but it

NOTES:

42
 has no effect on FF1 because a positive-going transition must occur to trigger the
flip-flop.
 After the leading edge of CLK1, Q0 = 1 and Q1 = 0.
 The positive-going edge of CLK2 causes Q0 to go LOW. Output ̅̅𝑄0̅ goes HIGH
and triggers FF1, causing Q1 to go HIGH.
 After the leading edge of CLK2, Q0 = 0 and Q1 = 1.
 The positive-going edge of CLK3 causes Q0 to go HIGH again. Output ̅̅𝑄0̅
goes LOW and has no effect on FF1.
 After the leading edge of CLK3, Q0 = 1 and Q1 = 1.
 The positive-going edge of CLK4 causes Q0 to go LOW, while 0𝑄̅ goes HIGH
and triggers FF1, causing Q1 to go LOW.
 After the leading edge of CLK4, Q0 = 0 and Q1 = 0. The counter has now recycled
to its original state (both flip-flops are RESET).
 In the timing diagram, the waveforms of the Q0 and Q1 outputs are shown relative
to the clock pulses as illustrated in figure 8.2.1 (a).
For simplicity, the transitions of Q0, Q1, and the clock pulses are shown as simultaneous
even though this is an asynchronous counter. There is, of course, some small delay between the
CLK and the Q0 transition and between the Q0 transition and the Q1 transition.

b) DOWN COUNTER USING FLIP-FLOP:

NOTES:

43
 2-Bit Binary Ripple Down Counter

Binary State Sequence for a 2-Bit Ripple Down Counter

Logic Circuit: - fig.shows, a 2-bit down counter connected for asynchronous operation. Here
the clock (CLK) is applied to the clock input (C) of the first flip-flop (FF-A) ONLY, which is
always the least significant bit (LSB). The second flip-flop, FF-B, is triggered by the QA
output of FF-A. FF-A changes state at the positive-going edge of each clock pulse, but FF-B
changes only when triggered by a positive-going transition of the QA output of FF-A.

Because of the
inherent propagation delay time through a flip-flop, a transition of the input clock pulse
(CLK) and a transition of the QA output of FF-A can never occur at exactly the same time.
Therefore, the two flip-flops are never simultaneously triggered, so the counter operation is
asynchronous. The 2- bit counter exhibits four different states, (22 = 4). Also, notice that if
QA represents the least significant bit (LSB) and QB represents the most significant bit
(MSB), the sequence of counter states represents a sequence of binary numbers as listed in
Table.

Since it goes through a binary sequence, the counter in Fig.is a binary counter. It
actually counts the number of clock pulses up to three, and on the fourth pulse it recycles to its
original state (QA = 0, QB = 0). The term recycle is commonly applied to counter operation;
it refers to the transition of the counter from its final state back to its original state.

Timing Diagram: - Let’s examine the basic operation of the asynchronous counter of Fig. by
applying four clock pulses to FF-A and observing the Q output of each flip-flop. Fig.

(a) illustrates the changes in the state of the flip-flop outputs in response to the clock pulses.
Both flip-flops are connected for toggle operation (D = Q’) and are assumed to be initially
RESET (Q LOW).
NOTES:

44
  Initially both flip-flop outputs are LOW, i.e. QA = QB = 0

NOTES:

45
  The positive-going edge of CLK1 (clock pulse 1) causes the QA output of FF-A to go
HIGH, as shown in timing diagram. This triggers FF-B, causing QB output of FF-B to
go HIGH.
 After the leading edge of CLK1, QA = 1 and QB = 1.
 The positive-going edge of CLK2 causes QA to go LOW. Due to this, there is NO
effect on FF-B clock pulse. Hence QB maintains in the previous state i.e. HIGH.

 After the leading edge of CLK2, QA = 0 and QB = 1.

 The positive-going edge of CLK3 causes QA goes HIGH again. This triggers FF-B,
causing QB to toggle to LOW state.

 After the leading edge of CLK3, QA = 1 and QB = 0.

 The positive-going edge of CLK4 causes QA to go LOW again. Due to this, there is
NO effect on FF-B clock pulse. Hence QB maintains in the previous state i.e. LOW.
 After the leading edge of CLK4, QA = 0 and QB = 0. The counter has now recycled
to its original state (both flip-flops are RESET).
 In the timing diagram, the waveforms of the QA and QB outputs are shown relative
to the clock pulses as illustrated in figure.

6.2 SYNCHRONOUS COUNTER OR PARALLEL COUNTER

The counter where all the flip-flops are simultaneously clocked by an external clock is
called as Synchronous Counter or Parallel Counter. Hence synchronous counters are faster
than asynchronous counters due to the simultaneous clocking. Synchronous counters DO
NOT suffer from the ripple effect that asynchronous counters do. Synchronous counters
require more logic an asynchronous counters. J-K flip-flops are used to illustrate most
synchronous counters. D flip- flops can also be used but generally require more logic because
of having no direct toggle or no- change states.
LIMITATIONS:

The limitations of Synchronous Counters:

 Requires MORE logic gates.

NOTES:

46
  Circuit Design will be COMPLEX, as the no. of states increases.
 MORE Area Requirements on IC.
 Synchronous Counters are prone to Lockout Conditions.

6.3 UP COUNTERS:

 Connect the Q output of the one FF to the shorted J & K inputs of the succeeding FF.

Synchronous Up Counter Design

DOWN COUNTERS:

1. Connect the Q’ output of the one FF to the shorted J & K inputs of the succeeding FF.

Synchronous Down Counter Design

2-BIT BINARY SYNCHRONOUS UP COUNTERS USING FLIP-FLOP

Fig. shows a 2-bit synchronous binary counter. Here the arrangement of synchronous
counter is different from that for the asynchronous counter where it uses JK FF in order to
achieve a binary sequence.

NOTES:

47
 2-Bit Binary Synchronous Up Counter

Binary State Sequence for a 2-Bit Synchronous Up Counter

LOGIC CIRCUIT:

The operation of a J-K flip-flop synchronous counter is as follows:

 First, assume that the counter is initially in the binary 0 state; i.e. both flip-flops are
RESET. When the positive edge of the first clock pulse is applied, FF0 will toggle and
Q0 will therefore go HIGH.
 When FF1 at the positive-going edge of CLK1, the inputs J1 and K1 are at LOW level
because Q0 = 0 of FF0 due to propagation delay. So, J1 = 0 and K1 = 0 when the
leading edge of the first clock pulse is applied. This is a no-change condition, and
therefore FF1 does not change state. After CLK1, Q0 = 1 and Q1 = 0 (which is the
binary 1 state).

 When the leading edge of CLK2 occurs, FF0 will toggle and Q0 will go LOW. Since
FF1 has a HIGH (Q0 = 1) on its J1 and K1 inputs at the triggering edge of this clock
pulse, the flip- flop toggles, Q1 goes HIGH. Thus, after CLK2, Q0 = 0 and Q1 = 1
(which is a binary 2 state).
 When the leading edge of CLK3 occurs, FF0 again toggles to the SET state (Q0 = 1),
and FF1 remains SET (Q1 = 1) because its J1 and K1 inputs are both LOW (Q0 = 0).
After this triggering edge, Q0 = 1 and Q1 = 1 (which is a binary 3 state).
 Finally, at the leading edge of CLK4, Q0 and Q1 go LOW because they both have a

NOTES:

48
 toggle condition on their J and K inputs. The timing detail is shown in fig. 8.4.1 (a). The
counter has now recycled to its original state, binary 0.

CASCADING COUNTERS
Counters can be connected in cascade to achieve higher-modulus operation. In essence,
cascading means that the last-stage output of one counter drives the input of the next counter.

Large counter applications requiring several stages of cascaded counters include

digital time clocks, frequency dividers, and synchronization circuits.

ASYNCHRONOUS CASCADING
ASYNCHRONOUS COUNTERS CASCADING USING FFS: (MOD-32 COUNTER)
An example of two asynchronous counters connected in cascade is shown in Fig.
for a 2-bit(Mod-4) and a 3-bit (Mod-8) ripple counter. The timing diagram is also shown in
Fig.

Notice that the final output of the modulus-8 counter (Q4), occurs once for every 32 input
clock pulses. The overall modulus of the two cascaded counters is Mod-4 * Mod-8 =
Mod-32; that is, the circuit is designed to act as a divide-by-32 counter.

Logic Circuit for Asynchronous Cascading of Counters (Mod-32 Counter)

NOTES:

49
 Timing Diagram of Asynchronous Cascading of Counters (Mod-32 Counter)

Hence, the overall modulus of cascaded counters is equal to the product of the individual moduli.

ASYNCHRONOUS COUNTERS CASCADING USING ICS: (MOD-1000 COUNTER)

Counters can be cascaded to increase the counting range. The cascading arrangement for
all the asynchronous counter ICs is the same, where the output QD of the preceding stage is
connected to the input clock terminal of the succeeding stage. Fig shows a cascading arrangement
of a 3-digitBCD counter using the 7490 ICs.

Logic Circuit for Asynchronous Cascading of Counters using ICs

As shown in the fig. three 74LS90 decade counter ICs are cascaded together to obtain
mod-10, mod-100, and mod-1000 counters. The most significant output bit, qd, is used as the
cascaded clock input to the next stage.

NOTES:

50
 6.4 APPLICATIONS OF COUNTERS

The digital counter is a useful and versatile device that is found in many
applications.

1. DIGITAL CLOCK: A common example of a counter application is in timekeeping

systems. Fig. is a simplified logic diagram of a digital clock that displays seconds, minutes,
and hours. First, a 60 Hz sinusoidal ac voltage is converted to a 60 Hz pulse waveform and
divided down to a 1 Hz pulse waveform by a divide-by-60 counter formed by a divide-by-10
counter followed by a divide-by- 6 counter. Both the seconds and minutes counts are also
produced by divide- by-60 counters. These counters count from 0 to 59 and then recycle to 0;
synchronous decade counters are used in this particular implementation.

1. AUTOMATIC PARKING CONTROL:

This counter example illustrates the use of an up/down counter to solve an everyday
problem. The problem is to devise a means of monitoring available spaces in a one-hundred
space parking garage and provide for an indication of a full condition by illuminating a
display sign and lowering a gate bar at the entrance.

NOTES:

51
 A system that solves this problem consists of optoelectronic sensors at the entrance and
exit of the garage, an up/down counter and associated circuitry, and an interface circuit that
uses the counter output to turn the FULL sign on or off as required and lower or raise the gate
bar at the entrance. A general block diagram of this system is shown in Fig

. Functional block diagram for Automatic Parking Control

2. PARALLEL-TO-SERIAL DATA CONVERSION (MULTIPLEXING):

A simplified example of data transmission using multiplexing and de-multiplexing

techniques. Essentially, the parallel data bits on the multiplexer inputs are converted to serial
data bits on the single transmission line. A group of bits appearing simultaneously on parallel
lines is called parallel data. A group of bits appearing on a single line in a time sequence is
called serial data.

Parallel-to-serial conversion is normally accomplished by the use of a counter to

provide a binary sequence for the data-select inputs of a data selector/multiplexer, as shown in
fig.(c). The Q outputs of the modulus-8 counter are connected to the data-select inputs of an
8-bit multiplexer.

NOTES:

52
 Parallel to Serial Data Conversion Logic

3. ANALOG TO DIGITAL CONVERSION:

Counters finds applications in converting an Analog value to Digital value. The

Counter type ADC can be defined as, it is the basic type of ADC. It is also known as staircase
approximation ADC, or a ramp type ADC. The circuit diagram of counter type ADC is shown
below fig. The circuit diagram of Counter Type ADC can be built with N-bit counter, digital
to analog converter, and op-amp comparator.

4. FREQUENCY DIVIDERS:
For frequency division, toggle mode flip-flops are used in a chain as a divide by two
counter.One flip-flop will divide the clock, ƒIN by 2, two flip-flops will divide ƒIN by 4 (and so
on) as shown in fig. One benefit of using toggle flip-flops for frequency division is that the output
at any point has an exact 50% duty cycle.

NOTES:

53
 Frequency Division

The final output clock signal will have a frequency value equal to the input clock
frequency divided by the MOD number of the counter. Such circuits are known as “divide-by-
n” counters.

5. MICROWAVE OVEN:
One of our kitchen appliances is microwave ovens. In that we set some temperature to
heat the food item kept in it. Internally the counter calculates the increase or decrease in
temperature and time. If it reaches the pre-set temperature, then it prevents from further
heating and spoiling of that food item.

6. WASHING MACHINES:
We use counters in washing machines also. Similar to the counting operation in
microwave oven, the counter in washing machine counts the time which we set it to operate.
In both microwave oven and washing machine, we set the device to particular time, and it
starts decreasing for every second. When the value of counter becomes zero, it activates the
switch ON / OFF. Thus the operation of the device is controlled by counters.

6.5 SHIFT REGISTERS & ITS TYPES

Shift registers are a type of sequential logic circuit used primarily for the storage of
digital data and typically do not possess a characteristic internal sequence of states. Shift
registers consist of arrangements of flip-flops and are important in applications involving the
storage and transfer of data in a digital system. A register has no specified sequence of states,
except in certain very specialized applications.

NOTES:

54
 A register is a digital circuit with two basic functions: data storage and data
movement. The storage capability of a register makes it an important type of memory device.
Fig.illustrates the concept of storing a 1 or a 0 in a D flip-flop.

1. A 1 is applied to the data input as shown, and a clock pulse is applied that stores the 1 by
setting the flip-flop.
When the 1 on the input is removed, the flip-flop remains in the SET state, thereby storing the 1.

A similar procedure applies to the storage of a 0 by resetting the flip-flop, as also

illustrated in Fig.

Flip-flop as a Storage Element

The storage capacity of a register is the total number of bits (1s and 0s) of digital data
it can retain. Each stage (flip-flop) in a shift register represents one bit of storage capacity;
therefore, the number of stages or flip-flops in a register determines its storage capacity. A
register can consist of one or more flip-flops used to store and shift data. The shift capability
of a register permits the movement of data from stage to stage within the register or into or out
of the register upon application of common clock pulses. This makes the shift register a
synchronous device.

4-bit Shift Register

Fig.illustrates the types of data movement in shift registers. The block represents the 4-bit
register, and the arrows indicate the direction of data movement.

NOTES:

55
 Basic Data Movement in Shift Registers

7.0 TYPES OF MEMORY

Introduction: Computers and other types of systems require the permanent or semi-
permanent storageof large amounts of binary data. Microprocessor-based systems rely on
storage devices for their operation because of the necessity for storing programs and for
retaining data during processing.Memory is the portion of a computer or other system that
stores binary data. In a computer, memory is accessed millions of times per second, so the
requirement for speed and accuracy is paramount. Very fast semiconductor memory is
available today in modules with several GB (a gigabyte is one billion bytes) of capacity.
These large-memory modules use exactly the same operating principles as smaller units.
With unprecedented developments in semiconductor technology, it has become possible to
make semiconductor memories of various types and sizes.These memories have become very
popular due to their small size, low cost, high speed, high reliability, and ease of expansion
of the memory size. Hence, while designing a digital processors,a designer should thoroughly
know the operating principles and limitations of various semiconductor memory devices.

NOTES:

56
 Classification of Memories:

7.1 RAM:
A RAM is a read/write memory in which data can be
written into or read from any selectedaddress in any
sequence. When a data unit is written into a given address
in the RAM, the data unitpreviously stored at that address
is replaced by the new data unit. When a data unit is read
from a given addressin the RAM, the data unit remains
stored and is not erasedby the read operation. This non-
destructive read operationcan be viewed as copying the
content of an address whileleaving the content intact. A
RAM is typically used for short-term data storage because it cannot retain stored data when power
is turned off.

NOTES:

57
 7.2 ROM:
A ROM contains permanently or semi permanently stored data, which can be read from the
memory but either cannot be changed at all or cannot be
changed without specialized equipment. A ROM stores data
that are usedrepeatedly in system applications, such as tables,
conversions, orprogrammed instructions for system
initialization and operation.ROMs retain stored data when
the power is off and are thereforecalled as non-volatile
memories.

7.3 EPROM:
EPROM stands for Erasable Programmable Read Only Memory. One disadvantage of a
PROM is that once it is programmed, the contents are stored in that memory chip permanently, it
can't be changed; a mistake in programming the chip can't be corrected. The EPROM overcomes
this difficulty. Unlike an ordinary PROM, an EPROM can be reprogrammed if an existing
program in the memory array is erased first. An EPROM uses an N-MOSFET array with an
isolated-gate structure. The isolated transistor gate has no electrical connections and can store an
electrical charge for indefinite periods of time. The data bits in this type of array are represented
by the presence or absence of a stored gate charge. Erasure of a data bit is a process that removes
the gate charge.

The EPROM has a structure and addressing scheme similar to PROM, but it is constructed
using MOS devices rather than bipolar devices. Many MOS EPROMs are TTL-compatible, and
eventhe technique used to program the chip is similar to that used with a bipolar memory. The
only difference is really the mechanism for permanently storing a 1 or a 0 in an MOS memory
cell. Theystore 1s and 0s as a packet of charge in a buried layer of the IC chip. EPROMs can be
programmedby the user with a special EPROM programmer.

The important feature of EPROM is that the data stored in EPROM are erased by exposing
the EPROM chip to Ultra-Violet light (UV light) through its Quartz Window for 15 to 20 minutes.
The isolated gate in the FET of an ultraviolet EPROM is “floating” within an oxide insulating
material. The programming process causes electrons to be removed from the floating gate. Erasure
is done by exposure of the memory array chip to high-intensity ultraviolet radiation through the
UV window on top of the package. The positive charge stored on the gate is neutralized after
several minutes to an hour of exposure time. You can recognize the UV EPROM device by the
NOTES:

58
 UV

NOTES:

59
 transparent window on the package as shown in the fig. In EPROMs, it is NOT possible to erase
selective information; when erased the entire information is lost. The chip can be re-programmed.
This memory is ideally suitable for product development, experimental projects and college
laboratories, since this chip can be reused many times.

The EPROM ICs are IC 2716 is a 16K (2K x 8) EPROM, which has capacity of 2048 words,
8 bits each, for a total storage capacity of 16,384 bits. This chip is completely TTL-
compatible and has an access time of less than 450 ns. The 11 address bits will uniquely
select one of 2048, 8-bit words (211 = 2048), and the selected word will appear at the data
output lines if chip-select is low. The IC 2732 is a 32K (4K x 8) EPROM that is pin-
compatible with the IC 2716 as it is simply twice the memory storage. Likewise, the 2764 is a
64K (SK x 8) EPROM.

Different EPROM Chips with an insight

sage to be expected on the shop floor.

NOTES:

60