Part A – All Questions

Paper: 4E1324 (2024)

Q.1. Explain digital signals.​

Answer: Digital signals are discrete-time signals with quantized amplitude. They represent
information using a finite set of values, typically two levels: HIGH (logic 1) and LOW (logic 0).

Q.2. Write the truth table of NAND, operations.​

Answer: The NAND gate is a universal gate. Its output is LOW only when all inputs are
HIGH.​
A | B | Output​
--|---|---​
0 | 0 | 1​
0 | 1 | 1​
1 | 0 | 1​
1|1|0

Q.3. Describe TTL.​

Answer: Transistor-Transistor Logic (TTL) is a logic family built from bipolar junction
transistors. It is characterized by its use of multi-emitter transistors, relatively high speed,
and significant power consumption.

Q.4. Write short note on ALU.​

Answer: An Arithmetic Logic Unit (ALU) is a digital circuit inside a CPU that performs integer
arithmetic (add, subtract) and bitwise logic operations (AND, OR, NOT).

Q.5. Explain in brief Flip Flops.​

Answer: A flip-flop is a bistable multivibrator, a sequential logic circuit that can store one bit
of state information. Its output can be changed by applying varying inputs.

Q.6. What do you mean by A/D converters?​

Answer: An Analog-to-Digital Converter (A/D or ADC) is a device that converts a continuous
analog voltage or current into a discrete digital number representing its amplitude.

Q.7. Write short note on quantization.​

Answer: Quantization is the process of mapping a large set of input values (like in an analog
signal) to a smaller, finite set of output values (digital levels).

Q.8. Explain RAM.​

Answer: Random Access Memory (RAM) is a form of volatile computer memory. "Random
access" means any byte of memory can be accessed directly without touching preceding
bytes.
Q.9. Describe CAM.​
Answer: Content-Addressable Memory (CAM) is a special type of memory that is searched
by its content rather than an address. It returns the address if the content is found.

Q.10. Write short note on FPGA.​

Answer: A Field-Programmable Gate Array (FPGA) is an integrated circuit containing a
matrix of configurable logic blocks and programmable interconnects, which can be
configured by a user post-manufacturing.

Paper: 4E1324 (July - 2023)

Q.1. State the associative property of boolean algebra.​

Answer: The associative property states that the grouping of variables does not affect the
result. For AND: (A·B)·C = A·(B·C). For OR: (A+B)+C = A+(B+C).

Q.2. List different digital logic families.​

Answer: Major logic families include TTL (Transistor-Transistor Logic), CMOS
(Complementary Metal-Oxide-Semiconductor), ECL (Emitter-Coupled Logic), and
NMOS/PMOS logic.

Q.3. Differentiate between a conventional encoder and a priority encoder.​

Answer: A conventional encoder generates an output for only one active input. A priority
encoder provides a valid output even with multiple active inputs, based on the highest
priority input.

Q.4. Draw the truth table for a half adder circuit and write the boolean expressions for
sum and carry.​
Answer:​
A | B | Sum | Carry​
--|---|-----|------​
0 | 0 | 0 | 0​
0 | 1 | 1 | 0​
1 | 0 | 1 | 0​
1 | 1 | 0 | 1​
Sum = A ⊕ B; Carry = A · B.

Q.5. Write excitation table of D flip - flop.​

Answer: The excitation table shows the required input (D) for a given present-to-next-state
transition.​
Q(t) | Q(t+1) | D​
-----|--------|---​
0 | 0 | 0​
0 | 1 | 1​
1 | 0 | 0​
1|1|1
Q.6. Write about race around condition.​
Answer: The race-around condition occurs in level-triggered JK flip-flops when J=K=1. The
output toggles continuously as long as the clock is high, leading to an indeterminate final
state.

Q.7. What are the advantages and disadvantages of R-2R ladder D/A converter.​
Answer: Advantage: Requires only two resistor values (R and 2R), providing better
accuracy. Disadvantage: Slower conversion speed compared to some other architectures.

Q.8. State the advantages and applications of sample and hold circuits.​
Answer: Advantage: It holds the analog voltage steady, allowing the A/D converter
sufficient time for an accurate conversion. Application: Used at the input stage of A/D
converters.

Q.9. Differentiate between static RAM and dynamic RAM.​

Answer: Static RAM (SRAM) uses flip-flops to store data and is faster but less dense.
Dynamic RAM (DRAM) uses capacitors, requiring periodic refreshing, but is denser and
cheaper.

Q.10. What is a programmable logic array? How it differs from ROM.​

Answer: A Programmable Logic Array (PLA) has both a programmable AND array and a
programmable OR array. A ROM has a fixed AND array (decoder) and a programmable OR
array.
Paper: 4E1324 (2024) - Part B

Q.1. Describe Schottky TTL and CMOS logic.​

Answer:​
Schottky TTL: This is a high-speed variant of the standard Transistor-Transistor Logic (TTL)
family. Its key feature is the integration of a Schottky diode as a clamp between the base and
collector of the switching transistors. This prevents the transistor from going into deep
saturation when it is turned on. By avoiding deep saturation, the storage time delay
associated with removing charge from the base region is significantly reduced. This results
in much faster switching times and higher operating frequencies compared to standard TTL,
though with slightly higher power consumption.

CMOS Logic: Complementary Metal-Oxide-Semiconductor (CMOS) logic is the most widely

used logic family in modern digital ICs. It is built using a combination of complementary
p-channel (PMOS) and n-channel (NMOS) transistors. In a static state (logic 0 or 1), one of
the transistors in the pair is ON while the other is OFF, creating no direct path from the
power supply to ground. This results in extremely low static power consumption. CMOS logic
is also known for its excellent noise immunity and wide operating voltage range.

Q.2. Obtain decimal equivalent of hexadecimal number (3A.2F)₁₆.​

Answer:​
To convert a hexadecimal number to its decimal equivalent, we multiply each hexadecimal
digit by its corresponding positional weight, which is a power of 16, and then sum the results.​
The number is (3A.2F)₁₆.

●​ For the integer part (3A):

○​ The digit '3' is in the 16¹ position.
○​ The digit 'A' (which is 10 in decimal) is in the 16⁰ position.
○​ Integer Value = (3 × 16¹) + (10 × 16⁰) = 48 + 10 = 58.
●​
●​ For the fractional part (.2F):
○​ The digit '2' is in the 16⁻¹ position.
○​ The digit 'F' (which is 15 in decimal) is in the 16⁻² position.
○​ Fractional Value = (2 × 16⁻¹) + (15 × 16⁻²) = 2/16 + 15/256 = 0.125 +
0.05859375 = 0.18359375.
●​

Combining both parts, the final decimal equivalent is 58.18359375.

Q.3. Implement the expression using a multiplexer F(A, B, C, D) = Σm(0, 2, 3, 6, 8, 9, 12,

14).​
Answer:​
To implement this 4-variable function, we can use an 8:1 multiplexer with A, B, and C as the
select lines and D as the input variable. We create an implementation table by listing pairs of
minterms for each combination of select lines and determining the required MUX input (I₀ to
I₇) in terms of D.

●​ I₀ (ABC=000): Minterms (0, 1). Function includes m(0), so we need the output to be 1
when D=0. This means I₀ = D'.
 ●​ I₁ (ABC=001): Minterms (2, 3). Function includes both m(2) and m(3). The output is 1
for D=0 and D=1. So, I₁ = 1.
●​ I₂ (ABC=010): Minterms (4, 5). Function includes neither. So, I₂ = 0.
●​ I₃ (ABC=011): Minterms (6, 7). Function includes m(6). The output is 1 when D=0.
So, I₃ = D'.
●​ I₄ (ABC=100): Minterms (8, 9). Function includes both m(8) and m(9). So, I₄ = 1.
●​ I₅ (ABC=101): Minterms (10, 11). Function includes neither. So, I₅ = 0.
●​ I₆ (ABC=110): Minterms (12, 13). Function includes m(12). The output is 1 when
D=0. So, I₆ = D'.
●​ I₇ (ABC=111): Minterms (14, 15). Function includes m(14). The output is 1 when D=0.
So, I₇ = D'.

The implementation requires connecting A, B, C to the select lines S₂, S₁, S₀ respectively.
The data inputs are connected as derived above.

Q.4. Describe shift registers. Write the application of shift registers.​

Answer:​
A shift register is a digital memory circuit composed of a cascade of flip-flops, where the
output of one is the input to the next. They share a single clock signal, causing the stored
data to shift one position at each clock pulse. They are fundamental in systems that require
manipulation of data bits.​
Types include:

●​ SISO (Serial-In, Serial-Out): Data enters one bit at a time and exits one bit at a time.
●​ SIPO (Serial-In, Parallel-Out): Data enters serially but is available on all outputs
simultaneously.
●​ PISO (Parallel-In, Serial-Out): All bits are loaded at once but are shifted out one by
one.
●​ PIPO (Parallel-In, Parallel-Out): Data is loaded and read in parallel.

Applications:

1.​ Data Conversion: SIPO and PISO registers are crucial for converting between serial
and parallel data formats in communication systems like UARTs.
2.​ Time Delays: A SISO register can be used to delay a digital signal by N clock cycles,
where N is the number of flip-flops.
3.​ Counters and Sequence Generators: Modified shift registers like Ring Counters
and Johnson Counters are used to generate specific repeating state sequences for
control applications.
4.​ Arithmetic Operations: Can be used to perform multiplication and division by
powers of two.

Q.5. Explain sample and hold circuit.​

Answer:​
A sample and hold (S/H) circuit is an analog device that captures (samples) the voltage of a
continuously varying analog signal and holds its value at a constant level for a specified
minimum period.​
Working Principle: It operates in two modes:
 1.​ Sample Mode: A switch (typically a MOSFET) connects the input analog signal to a
capacitor. The capacitor charges or discharges to track the input voltage.
2.​ Hold Mode: The switch is opened. The capacitor is now isolated from the input and
holds the voltage it had at the moment the switch opened.​
Purpose: The primary application is at the input stage of an Analog-to-Digital
Converter (ADC). ADCs require a finite amount of time to perform a conversion. If the
input analog signal changes during this time, the conversion will be inaccurate. The
S/H circuit freezes the input voltage, providing a stable DC value to the ADC, thus
ensuring a precise and reliable conversion.

Q.6. Write short notes on the following: (i) Sequential Memory (ii) ROM as a PLD​
Answer:​
(i) Sequential Memory: This is a type of memory where data is stored and accessed in a
specific linear sequence. To read or write a particular piece of data, one must physically scan
through all the preceding data locations. This is in contrast to random access memory (RAM)
where any location can be accessed directly. Magnetic tapes are a classic example of
sequential memory. While access time is very slow, its main advantage is very high storage
density and low cost per bit, making it suitable for data archiving and backup.

(ii) ROM as a PLD: A Read-Only Memory (ROM) can be used to implement any
combinational logic function, effectively acting as a Programmable Logic Device (PLD). A
ROM consists of a fixed AND array and a programmable OR array. The AND array is an
N-to-2ᴺ decoder that generates all possible 2ᴺ minterms for N input variables. The OR array
consists of a set of OR gates whose inputs can be programmably connected to any of the
minterm lines. By programming the connections in the OR array, we can sum any desired
set of minterms to create any Boolean function.

Q.7. Explain CPLDs.​

Answer:​
A Complex Programmable Logic Device (CPLD) is a programmable logic device with a
complexity that lies between simple PALs/GALs and more advanced FPGAs.​
Architecture: A CPLD consists of multiple programmable logic blocks, often called Logic
Array Blocks (LABs) or Function Blocks. Each block is similar to a PAL, containing a
programmable AND-OR array and a macrocell. The macrocell typically includes flip-flops for
sequential logic and logic for controlling output polarity. These logic blocks are
interconnected through a central programmable interconnect matrix.​
Characteristics:

●​ Non-Volatile: CPLDs retain their configuration when power is removed, usually using
EEPROM or Flash technology.
●​ Predictable Timing: The interconnect structure is less complex than an FPGA's,
leading to very predictable and deterministic timing delays, which is a major
advantage for high-speed control logic.
●​ Applications: They are well-suited for implementing decoders, state machines, and
other "glue logic" functions that connect larger components in a digital system.
Paper: 4E1324 (2024) - Part C

Q.1. Design a Gray-to-Binary Code Converter.​

Answer:​
A Gray-to-Binary code converter is a combinational logic circuit that translates a Gray code
input into its equivalent standard binary code output.​
Step 1: Conversion Logic​
Let the 4-bit Gray code input be G = G₃G₂G₁G₀ and the 4-bit Binary code output be B =
B₃B₂B₁B₀. The conversion rules are derived as follows:

●​ The Most Significant Bit (MSB) of the binary code is the same as the MSB of the
Gray code.​
B₃ = G₃
●​ For all subsequent bits, the binary bit is the result of the XOR operation between the
previous binary bit and the current Gray code bit.​
B₂ = B₃ ⊕ G₂​
B₁ = B₂ ⊕ G₁​
B₀ = B₁ ⊕ G₀

Step 2: Truth Table (Illustrative)​

| Gray (G₃G₂G₁G₀) | Binary (B₃B₂B₁B₀) |​
|---|---|​
| 0000 | 0000 |​
| 0001 | 0001 |​
| 0011 | 0010 |​
| 0010 | 0011 |​
| 0110 | 0100 |

Step 3: Circuit Implementation​

The derived Boolean expressions can be directly implemented using Exclusive-OR (XOR)
gates. The circuit consists of:

●​ A direct connection for the MSB from input G₃ to output B₃.

●​ A 2-input XOR gate with inputs G₃ and G₂. Its output is B₂.
●​ A second 2-input XOR gate with inputs B₂ (from the previous gate's output) and G₁.
Its output is B₁.
●​ A third 2-input XOR gate with inputs B₁ (from the second gate's output) and G₀. Its
output is B₀.​
This creates a simple, high-speed combinational circuit with a propagation delay
equivalent to the delay of the cascade of XOR gates.

Q.2. Describe BCD Arithmetic and Carry look ahead adder.​

Answer:​
BCD Arithmetic: Binary Coded Decimal (BCD) is a system of representing decimal digits
(0-9) using a 4-bit binary code. BCD arithmetic involves performing operations on these
codes.

●​ BCD Addition: When adding two BCD numbers, the standard binary addition is
performed on each 4-bit group. A correction is needed if the result of a 4-bit sum is
 an invalid BCD code (i.e., greater than 9) or if a carry-out is generated from the 4-bit
group. In either case, the result is corrected by adding 6 (0110) to that 4-bit sum. The
carry from this addition is then propagated to the next 4-bit group.

Carry Look-Ahead Adder: This is a high-speed parallel adder designed to overcome the
speed limitations of the ripple-carry adder. The ripple-carry adder's delay is proportional to
the number of bits because each full adder must wait for the carry-in from the previous
stage.

●​ Principle: The Carry Look-Ahead (CLA) logic computes the carry for each stage in
parallel. It uses two signals for each bit position i:
○​ Carry Generate (Gᵢ = Aᵢ · Bᵢ): A carry is generated at this stage regardless of
the carry-in.
○​ Carry Propagate (Pᵢ = Aᵢ ⊕ Bᵢ): An incoming carry will be propagated to the
next stage.
●​
●​ Implementation: The carry-out for any stage i+1 can be expressed as Cᵢ₊₁ = Gᵢ +
Pᵢ·Cᵢ. By recursively expanding this, all carries can be calculated directly from the
primary inputs (A, B, and C₀) using a two-level logic circuit, making the addition
process significantly faster.

Q.3. Explain clocked SR flip flop, J-K and D-type flipflops.​

Answer:​
Flip-flops are fundamental 1-bit memory elements in sequential logic. Their state changes
are synchronized by a clock signal.

●​ Clocked SR Flip-Flop: This is the most basic clocked flip-flop, with Set (S), Reset
(R), and Clock (CLK) inputs. Its operation is defined as:
○​ Hold (S=0, R=0): The output Q remains in its current state.
○​ Set (S=1, R=0): The output Q is forced to 1 on the active clock edge.
○​ Reset (S=0, R=1): The output Q is forced to 0 on the active clock edge.
○​ Forbidden (S=1, R=1): This input condition is invalid because it attempts to
set and reset the output simultaneously, leading to an unpredictable state.
This is the main drawback of the SR flip-flop.
●​
●​ J-K Flip-Flop: The J-K flip-flop is an enhancement of the SR flip-flop that resolves
the forbidden state issue. The J input behaves like S (Set) and the K input behaves
like R (Reset).
○​ Hold (J=0, K=0): Output Q holds its state.
○​ Set (J=1, K=0): Output Q becomes 1.
○​ Reset (J=0, K=1): Output Q becomes 0.
○​ Toggle (J=1, K=1): This is the key feature. The output inverts its current state
(Q becomes Q') on each active clock edge. This toggle functionality makes it
extremely versatile for designing counters.
●​
●​ D-type Flip-Flop (Data/Delay Flip-Flop): This flip-flop has a single data input, D. Its
function is to capture and store the value on the D input at the moment of the active
clock edge. The characteristic equation is simply Q(t+1) = D. Whatever value (0 or 1)
 is present at the D input is transferred to the Q output when the clock triggers. It
effectively delays the input signal by one clock cycle, making it the primary building
block for memory registers and shift registers.

Q.4. Explain Synchronous counters and sequence generator.​

Answer:​
Synchronous Counters: In a synchronous counter, the clock inputs of all the constituent
flip-flops are connected to a common clock signal. This is a significant difference from
asynchronous (ripple) counters where the output of one flip-flop clocks the next.

●​ Advantage: Because all flip-flops are triggered by the same clock edge, they all
change state simultaneously (after a small propagation delay). This eliminates the
cumulative delay of ripple counters and allows for much higher operating frequencies
and reliable decoding of states.
●​ Design: The logic for the J-K or D inputs of each flip-flop is designed based on the
desired count sequence. An excitation table is used to determine the necessary
inputs for each flip-flop to transition from its present state to the next state in the
sequence.

Sequence Generator: A sequence generator is a sequential circuit that produces a specific,

predefined sequence of bits or states that may not be a standard binary count.

●​ Implementation: They can be implemented in two main ways:

1.​ Using Shift Registers: Modified shift registers with custom feedback logic
can generate specific sequences. For example, a Ring Counter generates a
sequence of a single shifting '1', and a Johnson Counter generates a
sequence of 2N unique states for N flip-flops.
2.​ Using State Machines: A more general approach is to design a state
machine (using a synchronous counter structure) where the state transitions
are explicitly designed to follow the desired arbitrary sequence.
●​

Q.5. Describe A/D converter using voltage to frequency and voltage to time
conversion.​
Answer:​
These are both types of integrating A/D converters, which are known for their high noise
immunity but are generally slower than other architectures.

●​ Voltage-to-Frequency (V/F) ADC: This converter first transforms the analog input
voltage into a pulse train. The key principle is that the frequency of this pulse train is
directly proportional to the input voltage amplitude. The conversion to a digital value
is then achieved by using a counter to count the number of pulses that occur within a
fixed, precision time interval. A higher input voltage results in a higher frequency,
which in turn leads to a larger count and a higher digital output value.
●​ Voltage-to-Time (V/T) ADC (Dual-Slope Converter): This is a very common and
accurate integrating ADC. It converts the input voltage into a time interval, which is
then measured. The process involves two phases (slopes):
 1.​ Phase 1 (Integrate Input): The analog input voltage V_in is integrated for a
fixed period of time (T₁). The voltage on the integrator's capacitor ramps up to
a level proportional to V_in.
2.​ Phase 2 (De-integrate Reference): The input to the integrator is switched to
a fixed, negative reference voltage (-V_ref). The capacitor now ramps down
at a constant rate. A counter measures the time (T₂) it takes for the voltage to
return to zero.​
This time T₂ is directly proportional to V_in. The dual-slope method has the
advantage of canceling out errors due to component aging (like capacitor or
resistor value changes), making it very accurate.
●​

Paper: 4E1324 (July - 2023) - Part B

Q.1. Perform each of the following conversions:​

a. (444.456)₁₀ to octal​
b. (A3B)₁₆ to decimal​
c. (2D5)₁₆ to binary​
d. (115)₁₀ to hexadecimal​
Answer:​
a. (444.456)₁₀ to octal:

●​ Integer Part (444): Use repeated division by 8.​

444 ÷ 8 = 55 Remainder 4​
55 ÷ 8 = 6 Remainder 7​
6 ÷ 8 = 0 Remainder 6​
Reading remainders bottom-up gives (674)₈.
●​ Fractional Part (0.456): Use repeated multiplication by 8.​
0.456 × 8 = 3.648 (Integer part is 3)​
0.648 × 8 = 5.184 (Integer part is 5)​
0.184 × 8 = 1.472 (Integer part is 1)​
Reading integer parts top-down gives (.351...)₈.
●​ Result: (674.351)₈ (approx).

b. (A3B)₁₆ to decimal:​
Multiply each digit by its positional weight (power of 16).​
= (A × 16²) + (3 × 16¹) + (B × 16⁰)​
= (10 × 256) + (3 × 16) + (11 × 1)​
= 2560 + 48 + 11 = 2619₁₀.

c. (2D5)₁₆ to binary:​
Convert each hexadecimal digit to its 4-bit binary equivalent.​
2 → 0010​
D → 1101​
5 → 0101​
Result: (001011010101)₂.
d. (115)₁₀ to hexadecimal:​
Use repeated division by 16.​
115 ÷ 16 = 7 Remainder 3​
7 ÷ 16 = 0 Remainder 7​
Reading remainders bottom-up gives (73)₁₆.

Q.2. Compare the characteristics of TTL and CMOS logic families.​

Answer:​
TTL (Transistor-Transistor Logic) and CMOS (Complementary Metal-Oxide-Semiconductor)
are two of the most important digital logic families. Their characteristics differ significantly:

●​ Power Consumption: CMOS has extremely low static power consumption because
in a steady state, one transistor in the complementary pair is always off. TTL
consumes significantly more power as its transistors draw current even when idle.
●​ Speed: Standard TTL is generally faster than older standard CMOS. However,
modern CMOS technologies (like HCMOS) are very fast and often outperform TTL
variants.
●​ Noise Immunity: CMOS has a higher noise margin and is more immune to noise
because its logic levels are closer to the supply rails (Vdd and Vss).
●​ Fan-out: This is the number of standard inputs a gate can drive. Standard TTL can
drive up to 10 other standard TTL gates. CMOS fan-out is very high when driving
other CMOS gates (limited by capacitance and speed requirements) but lower when
driving TTL gates.
●​ Supply Voltage: TTL operates on a strict +5V supply with tight tolerances. CMOS
has a much wider and more flexible operating voltage range (e.g., 3V to 15V for older
series).
●​ Packing Density: CMOS technology allows for a higher packing density of
transistors on a chip, which is why it dominates in LSI and VLSI applications like
microprocessors.

Q.3. Using K-map, minimize the expression F(A, B, C, D) = Σm(1,5,7,9,11,13,15).​

Answer:​
The function F includes all minterms where the variable D is 1, except for m(3). A more
direct observation is that all included minterms (1, 5, 7, 9, 11, 13, 15) are odd numbers,
which means their binary representation always has the Least Significant Bit (D) as 1. Let's
verify this with a K-map.

We create a 4-variable K-map and place 1s in the cells corresponding to the given minterms.

CD\AB 00 01 11 10
00 . . . .
01 1 1 1 1 (m1, m5, m13, m9)
10 . . . .
11 . 1 1 1 (m7, m15, m11)

From the K-map, we can form the following groups to cover all the 1s:
 1.​ Group 1 (Quad): Covers the four corners of the map, m(1, 5, 9, 13). In these cells, B
is always 0 and D is always 1. The term for this group is B'D.
2.​ Group 2 (Quad): Covers the cells m(5, 7, 13, 15). Here, B is always 1 and D is
always 1. The term for this group is BD.
3.​ Group 3 (Quad): Covers the cells m(9, 11, 13, 15). Here, A is always 1 and D is
always 1. The term for this group is AD.

The sum-of-products expression from these prime implicants is F = B'D + BD + AD.​

Using Boolean algebra to simplify this expression:​
F = D(B' + B) + AD​
Since B' + B = 1:​
F = D(1) + AD​
F = D + AD​
Using the absorption law (X + XY = X):​
F = D(1 + A)​
Since 1 + A = 1:​
F = D(1) = D.​
The simplest possible minimal expression is F = D.

Q.4. Explain 4-bit serial in parallel out register.​

Answer:​
A 4-bit Serial-In, Parallel-Out (SIPO) shift register is a sequential logic circuit that accepts
data serially (one bit per clock cycle) and makes all the stored bits available simultaneously
on parallel outputs.​
Construction: It is constructed from four flip-flops (e.g., D-type) cascaded together. The Q
output of the first flip-flop is connected to the D input of the second, the Q of the second to
the D of the third, and so on. A common clock signal is applied to all flip-flops.​
Operation:

1.​ Data Input: Data is fed serially into the D input of the first flip-flop.
2.​ Shifting: At each active clock edge, the bit at the D input of each flip-flop is
transferred to its Q output. This effectively shifts the entire contents of the register
one position to the right. The new bit enters the first flip-flop, and the bit from the last
flip-flop is shifted out (and lost, unless captured).
3.​ Parallel Output: After four clock pulses, the 4-bit serial data word is fully loaded into
the register. The value of each bit is then available simultaneously on the parallel
output pins (Q₀, Q₁, Q₂, Q₃). This register is essential for converting serial data
streams from communication lines into parallel data for processing by a
microprocessor.

Q.5. Draw the logic diagram and timing sequence of a 4-bit ring counter.​
Answer:​
A 4-bit ring counter is a simple synchronous sequential circuit created from a shift register. It
circulates a single active logic level (usually a '1') through its stages.​
Logic Diagram:​
It is constructed from four D-type flip-flops (FF₀, FF₁, FF₂, FF₃) connected in a cascade. The
output of each flip-flop (Q) is connected to the data input (D) of the next one: Q₀→D₁, Q₁→D₂,
Q₂→D₃. The "ring" is formed by feeding the output of the final flip-flop (Q₃) back to the data
input of the first one (D₀). All flip-flops share a common clock signal. An asynchronous Preset
or Clear input is required to initialize the counter to a starting state, typically '1000', as it has
invalid "lock-up" states (e.g., 0000) from which it cannot escape.

Working and Timing Sequence:​

Assuming the counter is preset to the state Q₃Q₂Q₁Q₀ = 1000.​
| Clock Pulse | Q₃ | Q₂ | Q₁ | Q₀ |​
|---|---|---|---|---|​
| Initial State | 1 | 0 | 0 | 0 |​
| 1 | 0 | 1 | 0 | 0 |​
| 2 | 0 | 0 | 1 | 0 |​
| 3 | 0 | 0 | 0 | 1 |​
| 4 | 1 | 0 | 0 | 0 | (Sequence repeats)​
The sequence of states (1000, 0100, 0010, 0001) repeats every four clock cycles. It is useful
for generating timing signals to control a sequence of operations.

Q.6. Explain the terms accuracy and resolution for D/A converter.​
Answer:​
Accuracy and resolution are two critical, but distinct, performance metrics for a
Digital-to-Analog Converter (DAC).

●​ Resolution: This is a measure of the smallest possible change in the analog output
voltage. It is determined by the number of digital input bits (N). For an N-bit DAC,
there are 2ᴺ possible output levels. The resolution is the voltage difference between
two adjacent output levels, often called the step size or LSB (Least Significant Bit)
value.​
Resolution (Step Size) = V_fs / (2ᴺ), where V_fs is the full-scale output voltage.​
A higher number of bits (e.g., 16-bit vs 8-bit) results in a smaller step size and thus a
finer, or higher, resolution.
●​ Accuracy: This measures how close the actual analog output voltage is to the
theoretically ideal or expected voltage for a given digital input. It is expressed as a
percentage of the full-scale range or in terms of LSBs. Accuracy is affected by
real-world imperfections in the DAC's components, such as:
○​ Offset Error: A constant voltage shift present at the output even for a zero
input.
○​ Gain Error: A deviation in the slope of the actual transfer curve from the ideal
one.
○​ Non-linearity: The deviation of the transfer curve from a perfect straight line.​
A converter can have high resolution (many small steps) but poor accuracy
(the steps are in the wrong place).
●​

Q.7. Differentiate EPROM and PROM.​

Answer:​
PROM and EPROM are both types of non-volatile read-only memory, but they differ
fundamentally in their programmability and reusability.

●​ PROM (Programmable Read-Only Memory):

 ○​ Programmability: It is a One-Time Programmable (OTP) device. It is
manufactured with a matrix of fuses. The user can program it exactly once by
passing a high current through specific paths to "blow" the fuses, thereby
storing the data pattern.
○​ Erasure: It cannot be erased. Once programmed, the data is permanent.
○​ Application: Used for final product firmware where the code is finalized and
will not change.
●​
●​ EPROM (Erasable Programmable Read-Only Memory):
○​ Programmability: It can be programmed multiple times. Programming is
done electronically by trapping charge on a floating gate.
○​ Erasure: The memory can be erased by exposing the silicon die to a strong
source of ultraviolet (UV) light for several minutes. The chip package has a
characteristic transparent quartz window to allow this. The UV light gives the
trapped electrons enough energy to escape the floating gate, resetting the
memory to its initial state.
○​ Application: Primarily used during the development and prototyping phase of
a project, where code needs to be repeatedly tested, debugged, and
modified.
●​

Paper: 4E1324 (July - 2023) - Part C

Q.1. Define the following with one example: Error correcting codes, Gray code,
Hamming distance, Even and odd parity code.​
Answer:

●​ Error Correcting Codes (ECC): These are advanced codes designed not only to
detect the presence of errors in transmitted data but also to locate and correct a
certain number of them without requiring re-transmission. They achieve this by
adding carefully designed redundant bits. Example: Hamming code is a classic ECC
that can detect up to two-bit errors and correct single-bit errors.
●​ Gray Code: This is a non-weighted binary encoding system where any two
successive values differ in only one bit position. This property is highly useful in
systems where a value is changing sequentially (like a rotary shaft encoder) because
it prevents the temporary, erroneous intermediate states that can occur when multiple
bits change simultaneously in standard binary code. Example: The 2-bit Gray code
sequence is 00, 01, 11, 10.
●​ Hamming Distance: This is a metric for comparing two binary strings of equal
length. It is defined as the number of bit positions in which the corresponding bits are
different. The minimum Hamming distance of a code set determines its error
detection and correction capability. Example: The Hamming distance between the
codewords 10110 and 11010 is 3.
●​ Even and Odd Parity Code: This is a simple error detection scheme. A single bit,
called the parity bit, is appended to a block of data.
 ○​ Even Parity: The parity bit is set to 0 or 1 to make the total number of '1's in
the codeword (data + parity bit) an even number. Example: For data 1101
(three 1s), the even parity bit is 1, making the codeword 11011.
○​ Odd Parity: The parity bit is set to make the total number of '1's an odd
number. Example: For data 1101, the odd parity bit is 0, making the
codeword 11010.​
This can detect any single-bit error.
●​

Q.2. Using the Quine-McCluskey method, obtain the minimal sum of product
expression of the following function. F(A, B, C, D) = Σm(0,1,3,7,8,9,11,15).​
Answer:​
The Quine-McCluskey method is a tabular method for logic minimization.​
Step 1: Group Minterms by Number of 1s​
| Group | Minterm | Binary |​
|---|---|---|​
| G0 | 0 | 0000 |​
| G1 | 1, 8 | 0001, 1000 |​
| G2 | 3, 9 | 0011, 1001 |​
| G3 | 7, 11 | 0111, 1011 |​
| G4 | 15 | 1111 |

Step 2: Combine Terms from Adjacent Groups​

| Combination | Resulting Term | Binary |​
|---|---|---|​
| (0,1) | A'B'C' | 000- |​
| (0,8) | B'C'D' | -000 |​
| (1,3) | A'B'D | 00-1 |​
| (1,9) | B'C'D | -001 |​
| (3,7) | A'CD | 0-11 |​
| (9,11) | AB'D | 10-1 |​
| (7,15) | BCD | -111 |​
| (11,15) | ACD | 1-11 |

Step 3: Combine Again​

| Combination | Resulting Term | Binary |​
|---|---|---|​
| (1,3,9,11) [from (1,3)&(9,11) and (1,9)&(3,11)] ->This is not correct. (1,9)&(3,11) is -0-1. So,
yes. | B'D | -0-1 |

No further combinations are possible. The prime implicants are all terms from Step 2 that
were not used in Step 3, plus the term from Step 3.​
Prime Implicants (PIs): B'D, A'B'C', B'C'D', A'CD, BCD, ACD.

Step 4: Prime Implicant Chart​

| PI | Cost | 0 | 1 | 3 | 7 | 8 | 9 | 11 | 15 |​
|---|---|---|---|---|---|---|---|---|---|​
| B'C'D' | 3 | X | | | | X | | | | EPI​
| A'CD | 3 | | | X | X | | | | | EPI​
| B'D | 2 | | X | X | | | X | X | |​
| BCD | 3 | | | | X | | | | X |​
| ACD | 3 | | | | | | | X | X |​
| A'B'C' | 3 | X | X | | | | | | |

●​ m(8) is only covered by B'C'D'. It is an Essential Prime Implicant (EPI). It also covers
m(0).
●​ m(7) is only covered by A'CD. It is an EPI. It also covers m(3).
●​ After selecting these EPIs, we need to cover the remaining minterms: m(1), m(9),
m(11), m(15).
●​ PI B'D covers m(1), m(9), and m(11).
●​ PI ACD covers m(11) and m(15).
●​ To cover the remaining minterms, we need to cover m(1), m(9), m(11), m(15).
●​ Selecting B'D covers 1, 9, 11. Only 15 remains.
●​ To cover 15, we must select either BCD or ACD. Both have the same cost.
●​ One minimal solution is F = B'C'D' + A'CD + B'D + BCD.
●​ Let's check the chart again. My EPI selection might be wrong.
○​ m8 -> B'C'D'. EPI. Covers 0, 8.
○​ Remaining: 1,3,7,9,11,15.
○​ m9 -> only covered by B'D. EPI. Covers 1,3,9,11.
○​ Remaining: 7, 15.
○​ m7 -> only covered by A'CD or BCD.
○​ m15 -> only covered by BCD or ACD.
○​ To cover both 7 and 15, we can select BCD.​
Minimal Solution: F = B'C'D' + B'D + BCD.
●​

Q.3. a. Convert J-K flip-flop to S-R flip-flop. b. Design a 4-bit synchronous counter.​
Answer:​
a. Convert J-K flip-flop to S-R flip-flop:​
The goal is to use a JK-FF and external logic to replicate the behavior of an SR-FF.

1.​ Characteristic Table: We create a table showing the SR inputs (S, R), the desired
state transition (Q(t) to Q(t+1)), and the required JK inputs (J, K) to achieve that
transition.​
| S | R | Q(t) | Q(t+1) | J | K |​
|---|---|---|---|---|---|​
| 0 | 0 | 0 | 0 | 0 | X |​
| 0 | 0 | 1 | 1 | X | 0 |​
| 0 | 1 | 0 | 0 | 0 | X |​
| 0 | 1 | 1 | 0 | X | 1 |​
| 1 | 0 | 0 | 1 | 1 | X |​
| 1 | 0 | 1 | 1 | X | 0 |​
| 1 | 1 | X | X | X | X | (Forbidden in SR, so all are Don't Cares)
2.​ K-maps for J and K: We create K-maps for J and K in terms of S, R, and Q(t).
○​ For J: The K-map gives J = S.
○​ For K: The K-map gives K = R.
 3.​
4.​ Implementation: The conversion is trivial. Connect the S input directly to the J
terminal and the R input directly to the K terminal of the JK flip-flop.

b. Design a 4-bit synchronous UP counter:​

This counter will cycle from 0000 to 1111. We will use T flip-flops for simplicity.

1.​ State Table and Excitation Table: We determine the required T input for each
flip-flop (T₃, T₂, T₁, T₀) to transition from the Present State (Q₃Q₂Q₁Q₀) to the Next
State. A T-FF toggles (Q->Q') when T=1.​
| Present State | Next State | T₃ | T₂ | T₁ | T₀ |​
|---|---|---|---|---|---|​
| 0000 | 0001 | 0 | 0 | 0 | 1 |​
| 0001 | 0010 | 0 | 0 | 1 | 1 |​
| 0010 | 0011 | 0 | 0 | 0 | 1 |​
| 0011 | 0100 | 0 | 1 | 1 | 1 |​
...and so on...
2.​ Derive Logic Expressions: By observing the pattern or using K-maps for each T
input:
○​ T₀ toggles on every clock pulse: T₀ = 1.
○​ T₁ toggles whenever Q₀ is 1: T₁ = Q₀.
○​ T₂ toggles whenever Q₁ and Q₀ are both 1: T₂ = Q₁·Q₀.
○​ T₃ toggles whenever Q₂, Q₁, and Q₀ are all 1: T₃ = Q₂·Q₁·Q₀.
3.​
4.​ Circuit Implementation:
○​ Use four T flip-flops, with all clock inputs connected to a common clock signal.
○​ Connect T₀ to a logic HIGH source.
○​ Connect T₁ to the Q₀ output.
○​ Use a 2-input AND gate with inputs Q₁ and Q₀ to drive T₂.
○​ Use a 3-input AND gate with inputs Q₂, Q₁, and Q₀ to drive T₃.
5.​

Q.5. Write a notes on FPGA (field programmable gate array) with a neat diagram.​
Answer:​
A Field-Programmable Gate Array (FPGA) is a high-density, semiconductor integrated circuit
containing a large matrix of programmable logic components and programmable
interconnects. Unlike a microprocessor, which executes software instructions sequentially,
an FPGA is configured to implement a custom digital hardware circuit directly.

Architecture (Diagram should show these components):

1.​ Configurable Logic Blocks (CLBs) / Logic Array Blocks (LABs): These are the
fundamental building blocks for implementing logic. A typical CLB contains one or
more Look-Up Tables (LUTs) and several flip-flops. An N-input LUT is a small RAM
that can implement any combinational logic function of N variables. The flip-flops are
used to implement sequential logic (registers, counters, state machines).
2.​ Programmable Interconnects: This is a rich, hierarchical network of routing
channels and programmable switches (pass transistors or multiplexers) that connect
 the CLBs to each other and to the I/O blocks. The routing architecture is a key factor
in an FPGA's performance and density.
3.​ Input/Output Blocks (IOBs): Located at the periphery of the chip, these blocks
connect the internal logic to the external pins of the FPGA. They are highly
configurable to support a wide variety of I/O standards (e.g., LVCMOS, LVDS) and
can be configured as inputs, outputs, or bidirectional pins.
4.​ Specialized Blocks: Modern FPGAs also include dedicated hardware blocks for
common functions, such as Block RAMs (BRAMs) for memory, DSP slices for digital
signal processing, and high-speed transceivers.

Design Flow:

1.​ Design Entry: The user describes the desired hardware circuit using a Hardware
Description Language (HDL) like VHDL or Verilog.
2.​ Synthesis: An EDA tool synthesizes the HDL code into a netlist of generic logic
gates and flip-flops.
3.​ Implementation (Place & Route): The tool maps the synthesized logic to the
specific resources of the target FPGA (e.g., placing logic into CLBs) and then routes
the connections between them using the programmable interconnects.
4.​ Bitstream Generation: The final placed and routed design is converted into a
bitstream file, which contains the configuration data for every programmable element
in the FPGA. This file is then downloaded to the FPGA to implement the circuit.