Qualcomm Technologies, Inc.

IPQ6000 Wi-Fi Access Point SoC

Data Sheet

80-YB726-3 Rev. F
November 13, 2020

For additional information or to submit technical questions go to https://createpoint.qti.qualcomm.com

Confidential – Qualcomm Technologies, Inc. and/or its affiliated companies – May Contain Trade Secrets

NO PUBLIC DISCLOSURE PERMITTED: Please report postings of this document on public servers or websites to:
DocCtrlAgent@qualcomm.com.

Restricted Distribution: Not to be distributed to anyone who is not an employee of either Qualcomm Technologies, Inc. or its affiliated
companies without the express approval of Qualcomm Configuration Management. Distribution to anyone who is not an employee of either
Qualcomm Incorporated or its affiliated companies is subject to applicable confidentiality agreements.

Not to be used, copied, reproduced, or modified in whole or in part, nor its contents revealed in any manner to others without the express
written permission of Qualcomm Technologies, Inc.

All Qualcomm products mentioned herein are products of Qualcomm Technologies, Inc. and/or its subsidiaries.

Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. Other product and brand names
may be trademarks or registered trademarks of their respective owners.

This technical data may be subject to U.S. and international export, re-export, or transfer (“export”) laws. Diversion contrary to U.S. and
international law is strictly prohibited.

Qualcomm Technologies, Inc.

5775 Morehouse Drive
San Diego, CA 92121
U.S.A.
© 2019–2020 Qualcomm Technologies, Inc. and/or its subsidiaries. All rights reserved.
 Revision history

Revision Date Description

A May 2019 Initial release
B July 2019 Added content for the following sections:
 Section 3.1 Absolute maximum ratings
 Section 3.2 Operating conditions
 Section 3.4 Digital-logic characteristics
 Section 3.7.6 PWM interfaces
 Section 4.2 Part marking
 Section 4.3 Device ordering information
 Section 4.4 Device moisture-sensitivity level
 Section 4.5 Thermal characteristics
 Section 5 Carrier, storage, and handling information
 Section 6 PCB mounting guidelines
Updated the following contents:
 Section 1 Introduction: Updated features
 Figure 1-1 IPQ6000 functional block diagram
 Table 2-13 GPIO pins: Removed unsupported configurations

 Section 3 Electrical specifications: Removed USXGMII, I2S, TDM

interfaces
C December 2019 Added content for the following sections:
 Section 3.7.2 Parallel NAND and display interface
 Section 7.1 Reliability qualifications summary
Updated the following contents:
 Section 1.3.1 Wi-Fi subsystem
 Table 3-1 Absolute maximum ratings
 Table 3-2 Operating conditions
 Table 3-3 Operating conditions for voltage rails with AVS
 Table 3-11 Supported SD standards and exceptions
 Figure 3-1 IPQ6000 Power-on sequence

D May 2020 Updated the following contents:

 Table 3-1 Absolute maximum ratings
E September 2020 Fixed a typo in Figure 3-1 IPQ6000 Power-on sequence
F November 2020 Updated Section 6.2 SMT assembly guidelines

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 Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Interfaces and power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.1 Wi-Fi subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.2 Networking subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.3 CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.4 Reference clock structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.5 Peripherals/interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.7 Platform extension options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 Terms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 I/O parameter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Pin map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.1 CLK/RST and PMIC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.2 Wi-Fi PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.3 Analog test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.4 DDR4/DDR3L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.5 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.6 PLL test clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.7 PSGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.8 SDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.9 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.10 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.11 USXGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.12 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.13 Ground, power-supply and NC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3.14 Boot configuration GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3 Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.4 Digital-logic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.5.1 Timing diagram conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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3.5.2 Rise and fall time specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.6 Memory support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.6.1 DDR4/DDR3L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.6.2 eMMC on SDC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.6.3 NOR memory on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.7 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.7.1 Serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.7.2 Parallel NAND and display interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.7.3 SD interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.7.4 USB interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.7.5 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.7.6 PWM interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.8 UniPHY interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.8.1 PSGMII interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.8.2 QSGMII interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.8.3 SGMII+ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.8.4 SGMII interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.9 Internal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.9.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.9.2 Modes and resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.9.3 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.10 Analog IQ interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4 Mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.1 Device physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 Part marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.3 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.4 Device moisture-sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5 Carrier, storage, and handling information . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.1 Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1.1 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.1.2 Matrix tray information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2.1 Bag storage conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2.2 Out of bag duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3.1 Baking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3.2 Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.4 Barcode label and packing for shipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6 PCB mounting guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.1 RoHS compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.2 SMT assembly guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3 High-temperature warpage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7 Part reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.1 Reliability qualifications summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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7.2 Qualification sample description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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Tables
Table 1-1 Terms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2-1 I/O description parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2-2 CLK/RST interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2-3 Wi-Fi PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2-4 Analog test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 2-5 DDR4/DDR3L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 2-6 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 2-7 PLL test clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 2-8 PSGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 2-9 SDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 2-10 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 2-11 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2-12 USXMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2-13 GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 2-14 Ground, power-supply and NC pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 2-15 Boot configuration GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 3-1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3-2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 3-3 Operating conditions for voltage rails with AVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3-4 Digital I/O characteristics for VDDPX_1 (1.2 V or 1.35 V) . . . . . . . . . . . . . . . . . . . 41
Table 3-5 DC specification of VDDPX_3 = 1.8 V GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 3-6 Digital I/O characteristics for VDDPX_7 = 1.8/3.0 V nominal (SDC1) . . . . . . . . . . 43
Table 3-7 Supported DDR4/DDR3L standards and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 3-8 SPI master timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 3-9 Supported LCD controller standards and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 3-10 Supported NAND standards and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 3-11 Supported SD standards and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 3-12 Supported USB standards and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 3-13 Supported I2C standards and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 3-14 PSGMII transmitter DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 3-15 PSGMII receiver DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 3-16 PSGMII transmitter jitter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 3-17 PSGMII receiver jitter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 3-18 QSGMII transmitter DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 3-19 QSGMII receiver DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 3-20 QSGMII transmitter jitter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 3-21 QSGMII receiver jitter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 3-22 SGMII+ transmitter DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 3-23 SGMII+ receiver DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 3-24 SGMII+ transmitter jitter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 3-25 SGMII+ receiver jitter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

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Table 3-26 SGMII transmitter DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 3-27 SGMII receiver DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 3-28 SGMII transmitter jitter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 3-29 SGMII receiver jitter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 3-30 JTAG interface timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 3-31 Analog interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 3-32 Analog I/Q interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 4-1 Package marking line description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 4-2 Device identification details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 4-3 Source configuration code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 4-4 Ordering numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 4-5 Device JEDEC thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 7-1 IPQ6000 silicon reliability results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 7-2 IPQ6000 package reliability results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Contents

Figures
Figure 1-1 IPQ6000 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 1-2 IPQ6000 Reference clock structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2-1 IPQ6000 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3-1 IPQ6000 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3-2 IV curve for VOL and VOH (valid for all VDDPX_X) . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3-3 Timing diagram conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3-4 Rise and fall times under different load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3-5 SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 3-6 PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 3-7 PSGMII jitter eye diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 3-8 QSGMII jitter eye diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 3-9 JTAG interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 4-1 IPQ6000 mechanical dimensions, top and bottom views . . . . . . . . . . . . . . . . . . . . . 58
Figure 4-2 IPQ6000 device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 4-3 Device identification code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 5-1 Tape orientation on reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 5-2 Part orientation in tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 5-3 Matrix tray part orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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 1 Introduction

IPQ6000 is a System on Chip (SoC) for 11ax Wi-Fi Access Points, Retail Routers, and Carrier
Gateways. The chip consists of a Wi-Fi subsystem, a networking subsystem, and a CPU
subsystem.

1.1 Functional block diagram

5G FEM 5G FEM 2G FEM 2G FEM

QCN5x22/
QCN5x52
QCN5x21
RFA
RFA

2x2/80 2x2/40
11ax 11ax

Wi-Fi CPU Subsystem PTA/WCI coex

Quad-A53
16/32 bit
32 kB I$, 32 kB D$, 512 kB L2 UART/SPI
DDR3L/4
1.2 GHz

SPI
Security Accelerator PMU 3rd-party PMIC
NOR/NAND

ONFI/Parallel
Multi-thread Network Processor 1* USB3.0
NAND

2*2.5GE or 1*2.5GE + 4*1GE or

5*1GE Packet Processor 4*PWM,
SD/eMMC
GPIOs
P/QSGMII/SGMII/+ SGMII/+

QCA8075 QCA8081
5*1GE 2.5GE

Figure 1-1 IPQ6000 functional block diagram

1.2 Interfaces and power management

IPQ6000 comes with a large variety of interfaces to enable various platform configurations. It has
one USB 3.0, multiple serial IOs selectable between SPI/I2C/UART, Dual SDIO for eMMC and
SD card. 16/32 bits DDR3L/4 up to 1866/2133 MT/s, parallel NAND, serial NOR, and Wi-Fi/IOT

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Introduction

coexistence interfaces for up to two radios.

IPQ6000 comes with advanced power management for low active and standby power
consumption, making it extremely valuable for carrier gateway and enterprise AP power over
Ethernet (PoE) applications.

1.3 Features
NOTE: The features listed in this document show the chip hardware capability. Customers
should look to software documentation about support for features at software/system
level.

1.3.1 Wi-Fi subsystem

The Wi-Fi subsystem supports IEEE802.11ax. The IPQ6000 supports dual band simultaneous
(DBS) operation. One radio operates in 5 GHz with 2 antennae (2x2/80) and another radio in
2.4 GHz with 2 antennae (2x2/40) .
 Antenna configuration
 5 GHz: 2x2/80 MHz
 2.4 GHz: 2x2/40 MHz
 Four IQ transmit pairs and four IQ receive pairs to external
QCN5021/QCN5121/QCN5022/QCN5122/QCN5052/QCN5152
 802.11ac mode
 PHY rate: 866.7 Mbps (5 GHz) and 400 Mbps (2.4 GHz)
or proprietary PHY rate: 1083 Mbps (5 GHz) and 500 Mbps (2.4 GHz)
 5 GHz: SU-MIMO (2ss, 1 user) and MU-MIMO (2ss, 2 users)
 2.4 GHz: SU-MIMO (2ss, 1 user) and MU-MIMO (2ss, 2 users)
 Explicit beamforming
 3.2 µs Symbol Duration; 0.4 µs and 0.8 µs GI
 802.11ax mode
 PHY rate: 1201 Mbps (5 GHz) and 573.5 Mbps (2.4 GHz)
 5 GHz: SU-MIMO (2ss, 1 user), DL MU-MIMO (2ss, 2 users), DL-OFDMA (8 users),
UL-OFDMA (4 users)
 2.4 GHz: SU-MIMO (2ss, 1 user), DL MU-MIMO (2ss, 2 users), DL-OFDMA (8 users),
UL-OFDMA (4 users)
 Explicit beamforming
 12.8 µs Symbol Duration; 0.8 µs, 1.6 µs, or 3.2 µs GI
 Spatial Reuse/BSS color
 Extended Range (DCM, ER-SU)

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 Target Wake Time (TWT)

 Legacy 11a/b/g/n
 Radio Control interfaces, including Smart Antenna interface to manage external antenna
switch

1.3.2 Networking subsystem

The networking subsystem is a high-performance, high-throughput, programmable offload engine
to the networking stack that runs on the Host CPU subsystem.

The high-performance ingress packet engine of the networking subsystem makes IPQ6000 very
well suited to deliver Quality of Service (QoS) for carrier gateway applications to guarantee zero
packet loss for paid services like voice and video.

The networking subsystem performs standard routing/bridging within the WAN/LAN Ethernet
ports. Advanced features including tunneling and de/fragmentation are performed by a networking
processing unit (NPU) that consists of 12 threaded programmable engines (UBI32 core), running
at 1.5 GHz.
 Two Ethernet SerDes to connect to external multi-GbE PHYs.
 One SerDes supports 6.25/5/3.125/1.25 Gbps Ethernet SerDes ports for external
5*1/4*1/2.5/1 GbE PHYs. This SerDes can operate in PSGMII, QSGMII, SGMII+, or
SGMII mode to connect to QCA8075/QCA8072 (5/2 port GbE PHY).
 The other SerDes runs in either SGMII+ or SGMII mode to connect to QCA8081(2.5 GbE
PHY) or QCA803x (single port GbE PHY).

NOTE: When PSGMII is used, the other SerDes cannot be used.

 Packet Acceleration
 Packet Processing Engine (PPE) for standard 5-tuple routing/bridging of IPv4 and IPv6
packets with ingress capacity of 37.5M packet per second (Mpps) and egress capacity of
up to 10 Mpps per port
– Flexible VLAN assignment and translation on ingress, including filtering, double tag,
single tag, untag, priority tag
– Classification based on L2/L3/L4 and User Defined fields; actions like policing, QoS
Marking, en-queue, forwarding, and so forth
– Flow based routing/bridging/NAT; IPv4 unicast routing and NAT, IPv6 unicast
routing, PPPoE IPMC bridging
– MAC table for Bridge learning and aging, Station Movement control, L2 multicast,
Spanning tree, Link aggregation, Egress VLAN filtering, PPPoE
– Egress Queues:
• 256 unicast and 44 multicast queues
• PCP, DSCP, Flow, Classifier based Priority
• Classifier based policer with two rate, three color meters, marker

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• Ingress scheduling, shaping

• WRED lite with color aware dynamic, and static threshold
• 2-level Scheduler, 3-level Shaper with CIR, EIR rate control (HTB lite)
 One Twelve-Threaded network processing unit (NPU) Ubi32 @ 1.5 GHz
 Wi-Fi driver offload on NPU (optional)
 4 level QoS between pipelines
 Security
 In line security engine
– AES 128, 256
– SHA 1-96, 128, 256, 512
– 3DES 1-96, MD5-96
– CCM operation
 Four OTP keys for multi root revocation
 eMMC in-line crypto
 Secure execution environment
 ARM Trustzone

1.3.3 CPU subsystem

 Quad ARM Cortex A53 at 1.2 GHz, 64-bit ISA v8 instruction set
 32 kB/32 kB I$/D$ and 512 kB L2$
 64-bit Floating Point and NEON SIMD DSP extension for each core, which can be used for
enhanced audio/voice/video processing
 Supports crypto instruction extensions

1.3.4 Reference clock structure

The IPQ6000 has three options for reference clock input:
 External Wi-Fi RF chip (QCN5021/QCN5121/QCN5022/QCN5122/QCN5052/QCN5152).
 Off-chip Oscillator
 Off-chip Crystal

The top-level clock structure is shown in the diagram below.

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Serdes
24 MHz
PLLs
48 MHz Crystal or
32KHz ETH clock driver
MPM
Serdes cmn_refclk_sel[1:0]

48 MHz

TBD MHz 48 or 192

5G BB MHz Wi-Fi PHY
Copper
TBD MHz 2x2 DBS
2G BB

wlan_refclk_sel

Figure 1-2 IPQ6000 Reference clock structure

Definition for the select pins:

 wlan_refclk_sel: 0 for 48 MHz, 1 for 192 MHz
 cmn_refclk_sel[1:0]:
 00: Clock from Copper
 01: Clock from on board active oscillator
 10: Clock from crystal (internal ac-couple path)
 11: Clock from crystal (internal dc-couple path)

1.3.5 Peripherals/interfaces
 One USB 3.0
 Multiple programmable serial interface for SPI, UART or I2C
 Parallel NAND and Display Interface
 Serial NOR
 SD-card/eMMC
 16 or 32 bits DDR3L at 1866 MT/s or DDR4 at 2133 MT/s

1.3.6 Power management

 Advanced Power Management for low active and stand-by power consumption
 Interface to external third-party PMIC MP5496

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1.3.7 Platform extension options

 BT/BLE/15.4 companion chip through SPI/UART
 LTE-WAN through USB
 IOT radio with coexistence I/F through UART/SPI
 Display through QPIC port
 Storage through USB 3.0

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1.4 Terms and abbreviations

Table 1-1 lists terms, abbreviations, and acronyms commonly used throughout this document.

Table 1-1 Terms and abbreviations

Term Definition

AP Access point
DBDC Dual band dual concurrent
DDR Double data rate
NPU Networking processing unit
PPE Packet processing engine
PoE Power over Ethernet
PSGMII Penta-SGMII
QoS Quality of Service
QPIC Qualcomm parallel interface controller (NAND + LCD)
QSGMII Quad-SGMII
SA Spectrum analysis
SoC System on a chip

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 2 Pin definitions

2.1 I/O parameter definitions

Table 2-1 I/O description parameters
Symbol Description
Pad attribute
AI Analog input (does not include pad circuitry)
AO Analog output (does not include pad circuitry)
B Bidirectional digital with CMOS input
DI Digital input (CMOS)
DO Digital output (CMOS)
P Power
H High-voltage tolerant
S Schmitt trigger input
Z High-impedance (high-Z) output
Pad pull details for digital I/Os
nppdpukp Programmable pull resistor. The default pull direction is indicated using capital letters, and
is a prefix to other programmable options:
PU:nppdkp = default pull-up, with programmable options following the colon (:).
PD:nppukp = default pull-down, with programmable options following the colon (:).
NP:pdpukp = default no-pull, with programmable options following the colon (:).
KP:nppdpu = default keeper, with programmable options following the colon (:).
PU Contains an internal pull-up device
PD Contains an internal pull-down device
NP Contains no internal pull
KP Contains an internal week keeper device (keepers cannot drive external buses)
Pad-voltage groupings
P1 Pad group 1 (EBI/DDR); tied to VDDPX_1 (1.2 V or 1.35 V)
P3 Pad group 3 (general power: mode, JTAG, GPIOS); tied to VDDPX_3 (1.8 V only)
P7 Pad group 7 (SDC1); tied to VDDPX_7 (1.8 V only)
Output-current drive strength
EBI pads Pads for EBI are tailored for 1.2 V interfaces and are source terminated.

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Pin definitions

Table 2-1 I/O description parameters

Symbol Description
3.0 V (H) pads Programmable drive strength, 2–8 mA, in 2 mA steps

Others1 Programmable drive strength, 2–16 mA, in 2 mA steps

1. Digital pads other than EBI0 pads or high-voltage tolerant pads.

2.2 Pin map

The IPQ6000 device is available in the 570-pin FCBGA that includes several ground pins for
electrical grounding, mechanical strength, and thermal continuity. See Chapter 4 for package
details. A high-level view of the pin assignments is shown in Figure 2-1.

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Pin definitions

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

WLAN_REF VDDA_WL PHYA_CH0 PHYA_CH0 PHYA_CH1 PHYA_CH1 PHYB_CH0 PHYB_CH0 PHYB_CH1 PHYB_CH1
A VSSX_0 GPIO_72 GPIO_73 GPIO_75 VSSX_0
CLKN AN_1P8
VSSX_0
_IN _QN
VSSX_0
_IN _QN
VSSX_0
_IN _QN
VSSX_0
_IN _QN
VSSX_0 VSSX_0 GPIO_7 GPIO_4 GPIO_2 GPIO_11 GPIO_6 VSSX_0

WLAN_REF WLAN_ATE PHYA_CH0 PHYA_CH0 PHYA_CH1 PHYA_CH1 PHYB_CH0 PHYB_CH0 PHYB_CH1 PHYB_CH1
B GPIO_69 GPIO_70 GPIO_68 GPIO_71 VSSX_0
CLKP ST
VSSX_0
_IP _QP
VSSX_0
_IP _QP
VSSX_0
_IP _QP
VSSX_0
_IP _QP
VSSX_0 GPIO_1 GPIO_0 GPIO_5 GPIO_16 GPIO_8 GPIO_9 GPIO_10

CMN_REF
VDDPX_3_ VDDPX_3_ VDDPX_3_
C CLK_SEL_ GPIO_66
1P8
VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0
1P8
GPIO_3
1P8
GPIO_13 GPIO_12
1
PHYB5G_ PHYB5G_ PHYB2G_ PHYB2G_
PHYA_WSI PHYA_WSI VDDA_PHY VDDA_PHY VDDA_PHY VDDA_PHY
D ATEST0 ATEST1 VSSX_0 GPIO_79 GPIO_76 GPIO_77 GPIO_64 GPIO_67 GPIO_78
0_DATA 1_DATA A_1P2 A_1P2 B_1P2 B_1P2
VSSX_0 WSI0_DAT WSI1_DAT WSI0_DAT WSI1_DAT GPIO_20 GPIO_19 VSSX_0 GPIO_45 GPIO_17 GPIO_15 LEGEND
A A A A

WLAN_REF VDDPX_3_ PHYA_WSI PHYA_WSI VDDA_PHY VDDA_PHY VDDA_PHY VDDA_PHY PHYB5G_ PHYB5G_ PHYB2G_ PHYB2G_ VDDPX_3_ Net
E CLK_SEL
SRST_N
1P8
TRST_N TMS GPIO_65 GPIO_74 GPIO_49 GPIO_48
0_CLK 1_CLK A_1P2 A_1P2 B_1P2 B_1P2
VSSX_0
WSI0_CLK WSI1_CLK WSI0_CLK WSI1_CLK
GPIO_18 GPIO_21 GPIO_43 VSSX_0
1P8
GPIO_38 GPIO_14 Color
Group

CMN_REF
F CLK_SEL_ TDO TCK TDI GPIO_44 GPIO_42 GPIO_39 GPIO_40 EB I1*
0

G VSSX_0 VSSX_0 VSSX_0 MODE_1 MODE_0 GPIO_53 GPIO_23 GPIO_24 GPIO_27 USB *

PSGMII_TX PSGMII_TX VDDCX_1_ VDDCX_1_ VDDCX_1_ VDDCX_1_

H P N
XTAL_O XTAL_I VSSX_0 VSSX_0
0P8 0P8
VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0
0P8 0P8
VSSX_0 VSSX_0 GPIO_47 GPIO_41 VSSX_0 GPIO_25 GPIO_28 BB R*

PSGMII_R PSGMII_R CMN_CLK VDDA_CM VDDCX_1_ VDDCX_1_ VDDCX_1_ VDDCX_1_ VDDPX_3_

J XP XN _25M_OUT N_1P8
VSSX_0 VSSX_0
0P8 0P8
VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0
0P8 0P8
VSSX_0 VSSX_0 RESIN_N RESOUT_N
1P8
GPIO_26 GPIO_34 *DAC*

VDDA_USX VDDA_CM
VDDCX_1_ VDDCX_1_ VDDCX_1_ VDDCX_1_ VDDCX_1_ VDDCX_1_ VDDCX_1_ VDDCX_1_
K VSSX_0 VSSX_0 VSSX_0 GMII0_PLL N_LDO_OU
0P8 0P8
VSSX_0 VSSX_0
0P8 0P8
VSSX_0
0P8 0P8
VSSX_0 VSSX_0
0P8 0P8
GPIO_50 GPIO_52 GPIO_29 GPIO_33 *GPIO*
_0P9 T_0P9

CMN_CLK CMN_CLK
CMN_ATE CMN_RBIA VDDCX_1_ VDDCX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_
L _50M_DE_ _50M_DE_
ST S 0P8 0P8
VSSX_0 VSSX_0
0P85 0P85
VSSX_0
0P85 0P85
VSSX_0 VSSX_0
0P85 0P85
GPIO_46 GPIO_22 GPIO_31 GPIO_32 V DDPX*
P2 N2

VDDCX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ VDDPX_3_

M VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0
0P8 0P85
VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX_0
0P85 0P85
VSSX_0 VSSX_0 GPIO_51 GPIO_37
1P8
GPIO_36 GPIO_35 *V DD*

VDDA_PS
USXGMII0_ USXGMII0_ VDDA_PS VDDCX_1_ VDDCX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_
N TXP TXN
GMII_PLL_
GMII_0P85 0P8 0P8
VSSX_0 VSSX_0
0P85 0P85
VSSX_0
0P85 0P85
VSSX_0 VSSX_0
0P85 0P85
GPIO_30 VSSX_0 VSSX_0 VSSX_0 VSSX_0 VSSX *
0P9
VDDA_CM VDDA_CM
USXGMII0_ USXGMII0_ VDDCX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ DDR_CS_
P RXP RXN
N_PLL_0P N_LDO_IN VSSX_0
0P8
VSSX_0 VSSX_0
0P85 0P85
VSSX_0
0P85 0P85
VSSX_0 VSSX_0
0P85 0P85
VSSX_0 VSSX_0
N
DDR_ODT *V SS*
9 _1P2
VDDA_USX VDDA_USX
VDDCX_1_ VDDMX_1_ VDDMX_1_ VDDMX_1_ VDDCX_1_ VDDCX_1_ DDR_ACT_
R VSSX_0 VSSX_0 VSSX_0 GMII0_RX_ GMII0_TX_ VSSX_0 VSSX_0
0P8 0P85
VSSX_0 VSSX_0
0P85 0P85
VSSX_0
0P8 0P8
VSSX_0 VSSX_0 NC DDR_A_16 DDR_A_14
N
*CLK*
0P85 0P85
CMN_CLK CMN_CLK VDDPX_1_1
VDDCX_1_ VDDMX_1_ VDD_BM_ VDDMX_1_ VDDCX_1_ VDDCX_1_ VDDCX_1_ VDDCX_1_
T _50M_DE_ _50M_DE_ VSSX_0 VSSX_0 VSSX_0 VSSX_0
0P8 0P85
VSSX_0 VSSX_0
PLL_1P8 0P85
VSSX_0
0P8 0P8 0P8 0P8
NC P2_1P35_V VSSX_0 DDR_A_10 DDR_A_12
P N DDQ
VDDA_US VDDA_US VDDPX_1_1
VDDCX_1_ VDDCX_1_ VDD_APC0 VDD_APC0 VDD_APC0 VDD_APC0 VDDCX_1_
U VSSX_0 VSSX_0 VSSX_0 B0_CORE_ B0_SS_1P
0P8 0P8
VSSX_0 VSSX_0
_0P8 _0P8 _0P8 _0P8
VSSX_0
0P8
VSSX_0 VSSX_0 VSSX_0 DDR_ZQ DDR_BG_1 P2_1P35_V DDR_BA_0 DDR_A_4
0P925_SS 8 DDQ

VDDA_US VDDA_US
USB0_HS_ USB0_HS_ VDDCX_1_ VDDCX_1_ VDD_APC0 VDD_APC0 VDD_HY_P VDDCX_1_ VDD_PLL_ DDR_DTO_
V DP DM
VSSX_0 B0_HS_1P B0_HS_3P
0P8 0P8
VSSX_0 VSSX_0
_0P8
VSSX_0 VSSX_0
_0P8 LL_0P85 0P8 DDR_1P8
VSSX_0 VSSX_0
0
DDR_ATO DDR_BA_1 DDR_A_15
8 3

USB_SS_T VDDCX_1_ VDDMX_1_ VDD_APC0 VDD_APC0 VDD_PLL_ VDD_PLL_ DDR_DTO_

W VSSX_0
PA
NC VSSX_0 VSSX_0 VSSX_0
0P8 0P85 _0P8
VSSX_0 VSSX_0
_0P8 DDR_1P8 DDR_1P8
VSSX_0 VSSX_0 VSSX_0
1
NC VSSX_0 DDR_A_6 DDR_A_3

VDD_QFPR VDDPX_1_1
USB0_SS_ USB0_SS_ VDDCX_1_ VDDMX_1_ VDD_APC0 VDD_APC0 VREF_DDR VREF_DDR VREF_DDR
Y TXP TXM
NC NC OM_BLOW VSSX_0
0P8 0P85
VSSX_0
_0P8 _0P8 _DQ_2_3
VSSX_0 VSSX_0 VSSX_0
_DQ_0_1
VSSX_0
_CA
NC P2_1P35_V DDR_A_1 DDR_A_5
_1P8 DDQ

USB0_SS_ USB0_SS_
AA RXP RXM
VSSX_0 VSSX_0 NC NC DDR_A_2 DDR_A_0

VDDA_USB_0
USB0_HS_ USB0_SS_ DDR_RAM
AB REXT REXT
_CORE_0P92 VDDA_1P8 VDDA_3P3 DDR_A_17
_RST_N
VSSX_0 DDR_A_7 DDR_A_8
5_HS

VDDPX_1_1 VDDPX_1_1 VDDPX_1_1

PLL_TEST PLL_TEST DDR_DQ_2 DDR_DQ_2 DDR_DQ_2 DDR_DQ_2 DDR_DQ_1 DDR_DQ_1
AC VSSX_0 VSSX_0 VSSX_0
_DE_N _DE_P
GPIO_61 GPIO_62 GPIO_63 GPIO_57 GPIO_54 P2_1P35_V
4 6
VSSX_0
7 5
VSSX_0
2
P2_1P35_V VSSX_0
1
VSSX_0 NC VSSX_0 P2_1P35_V DDR_A_13 DDR_A_9
DDQ DDQ DDQ

SDC1_DAT SDC1_DAT VDDPX_7_ VDDPX_3_ DDR_DQ_2 DDR_DQ_3 DDR_DQ_3 DDR_DQ_2 DDR_DQ_1 DDR_DQ_1 DDR_DQ_1 DDR_DQ_1
AD A_0 A_1 1P8_3P0
GPIO_60 GPIO_59 GPIO_58 GPIO_56
1P8
GPIO_55 VSSX_0
8 0
VSSX_0
1 9
VSSX_0 DDR_DQ_8
0 4 5
VSSX_0
3
DDR_DQ_9 DDR_A_11 DDR_BG_0

V DDA _VTT _L VDDPX_1_1 VDDPX_1_1 VDDPX_1_1 VDDPX_1_1

SDC1_DAT SDC1_DAT VBIAS_SD VDDPX_7_ VDDA_0P9 DDR_CK_
AE A_2 A_3 C1_1P25 1P8_3P0
VDDA_1P8
25
DO_OUT_0P6 VSSX_0 P2_1P35_V VSSX_0 P2_1P35_V VSSX_0 P2_1P35_V P2_1P35_V VSSX_0 VSSX_0
N
DDR_CK
_0P 675 DDQ DDQ DDQ DDQ
VDDPX_1_1
SDC1_CM SDC1_DAT DDR_DQ_2 DDR_DQ_1 DDR_DQS DDR_DM_ DDR_DQS DDR_DQ_1 DDR_DQ_2 DDR_DQS DDR_DM_ DDR_DQS
AF SDC1_CLK
D A_5
VSSX_0 NC NC VSSX_0 NC VSSX_0 NC VSSX_0
0 6 _N_2 2 _N_3 9 3
DDR_DQ_4 DDR_DQ_0
_N_0 0 _N_1
DDR_DQ_3 DDR_DQ_7 DDR_CKE P2_1P35_V
DDQ
VDDPX_1_1
SDC1_DAT SDC1_DAT SDC1_DAT DDR_DQ_2 DDR_DQ_1 DDR_DM_ DDR_DQS DDR_DQS DDR_DQ_1 DDR_DQ_2 DDR_DQS DDR_DQS
AG VSSX_0
A_6 A_7 A_4
VSSX_0 NC VSSX_0 NC VSSX_0 NC VSSX_0
2 8 3 _2 _3 7 1
DDR_DQ_6 DDR_DQ_2 DDR_DM_1
_0 _1
DDR_DQ_1 DDR_DQ_5 P2_1P35_V VSSX_0
DDQ

Figure 2-1 IPQ6000 pin assignments

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2.3 Pin descriptions

2.3.1 CLK/RST and PMIC interface

Table 2-2 CLK/RST interface

Pad # Pad name Voltage Type Description
J23 RESIN_N 1.8 V DI Hardware reset input
J24 RESOUT_N 1.8 V DO Reset output when chip is in reset

2.3.2 Wi-Fi PHY

Table 2-3 Wi-Fi PHY

Pad # Pad name Voltage Type Description
A9 PHYA_CH0_IN 1.2 V AI, AO
PHYA Chain0 ADC/DAC signal
B9 PHYA_CH0_IP 1.2 V AI, AO
A10 PHYA_CH0_QN 1.2 V AI, AO
PHYA Chain0 ADC/DAC signal
B10 PHYA_CH0_QP 1.2 V AI, AO
A12 PHYA_CH1_IN 1.2 V AI, AO
PHYA Chain1 ADC/DAC signal
B12 PHYA_CH1_IP 1.2 V AI, AO
A13 PHYA_CH1_QN 1.2 V AI, AO
PHYA Chain1 ADC/DAC signal
B13 PHYA_CH1_QP 1.2 V AI, AO
E10 PHYA_WSI0_CLK 1.8 V DO
PHYA Chain 0 WSI interface clock
D10 PHYA_WSI0_DATA 1.8 V B
E11 PHYA_WSI1_CLK 1.8 V DO
PHYA Chain 0 WSI interface clock
D11 PHYA_WSI1_DATA 1.8 V B
A15 PHYB_CH0_IN 1.2 V AI, AO
PHYB Chain0 ADC/DAC signal
B15 PHYB_CH0_IP 1.2 V AI, AO
A16 PHYB_CH0_QN 1.2 V AI, AO
PHYB Chain0 ADC/DAC signal
B16 PHYB_CH0_QP 1.2 V AI, AO
A18 PHYB_CH1_IN 1.2 V AI, AO
PHYB Chain1 ADC/DAC signal
B18 PHYB_CH1_IP 1.2 V AI, AO
A19 PHYB_CH1_QN 1.2 V AI, AO
PHYB Chain1 ADC/DAC signal
B19 PHYB_CH1_QP 1.2 V AI, AO
E19 PHYB2G_WSI0_CLK 1.8 V DO
PHYB 2G Chain 0 WSI interface clock
D19 PHYB2G_WSI0_DATA 1.8 V B
E20 PHYB2G_WSI1_CLK 1.8 V DO
PHYB 2G Chain 1 WSI interface clock
D20 PHYB2G_WSI1_DATA 1.8 V B

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Table 2-3 Wi-Fi PHY (cont.)

Pad # Pad name Voltage Type Description
E17 PHYB5G_WSI0_CLK 1.8 V DO
PHYB 5G Chain 0 WSI interface clock
D17 PHYB5G_WSI0_DATA 1.8 V B
E18 PHYB5G_WSI1_CLK 1.8 V DO
PHYB 5G Chain 1 WSI interface clock
D18 PHYB5G_WSI1_DATA 1.8 V B
B7 WLAN_ATEST 1.8 V AI, AO Analog test PAD
E1 WLAN_REFCLK_SEL 1.8 V DI Reference frequency selection
A6 WLAN_REFCLKN 1.8 V AI
Reference clock
B6 WLAN_REFCLKP 1.8 V AI

2.3.3 Analog test

Table 2-4 Analog test

Pad # Pad name Voltage Type Description
D1 ATEST0 1.8 V AO
Analog test pin
D2 ATEST1 1.8 V AO

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2.3.4 DDR4/DDR3L

Table 2-5 DDR4/DDR3L

Pad # Pad name Voltage Type Description
AA27 DDR_A_0 1.20/1.35 V DO
Y26 DDR_A_1 1.20/1.35 V DO
AA26 DDR_A_2 1.20/1.35 V DO
W27 DDR_A_3 1.20/1.35 V DO
U27 DDR_A_4 1.20/1.35 V DO
Y27 DDR_A_5 1.20/1.35 V DO
W26 DDR_A_6 1.20/1.35 V DO
AB26 DDR_A_7 1.20/1.35 V DO
AB27 DDR_A_8 1.20/1.35 V DO
DDR address[17:0]
AC27 DDR_A_9 1.20/1.35 V DO
T26 DDR_A_10 1.20/1.35 V DO
AD26 DDR_A_11 1.20/1.35 V DO
T27 DDR_A_12 1.20/1.35 V DO
AC26 DDR_A_13 1.20/1.35 V DO
R26 DDR_A_14 1.20/1.35 V DO
V27 DDR_A_15 1.20/1.35 V DO
R24 DDR_A_16 1.20/1.35 V DO
AB23 DDR_A_17 1.20/1.35 V DO
R27 DDR_ACT_N 1.20/1.35 V DO Activate output
V24 DDR_ATO 1.20/1.35 V AO Analog test output
U26 DDR_BA_0 1.20/1.35 V DO
Bank address[0:1]
V26 DDR_BA_1 1.20/1.35 V DO
AD27 DDR_BG_0 1.20/1.35 V DO
Bank group address[0:1]
U24 DDR_BG_1 1.20/1.35 V DO
AE27 DDR_CK 1.20/1.35 V DO
Differential clock
AE26 DDR_CK_N 1.20/1.35 V DO
AF26 DDR_CKE 1.20/1.35 V DO Clock enable
P26 DDR_CS_N 1.20/1.35 V DO Chip select
AF22 DDR_DM_0 1.20/1.35 V DO Data mask[0]
AG21 DDR_DM_1 1.20/1.35 V DO Data mask[1]
AF15 DDR_DM_2 1.20/1.35 V DO Data mask[2]
AG14 DDR_DM_3 1.20/1.35 V DO Data mask[3]

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Table 2-5 DDR4/DDR3L (cont.)

Pad # Pad name Voltage Type Description
AF20 DDR_DQ_0 1.20/1.35 V B
AG24 DDR_DQ_1 1.20/1.35 V B
AG20 DDR_DQ_2 1.20/1.35 V B
AF24 DDR_DQ_3 1.20/1.35 V B
AF19 DDR_DQ_4 1.20/1.35 V B
AG25 DDR_DQ_5 1.20/1.35 V B
AG19 DDR_DQ_6 1.20/1.35 V B
AF25 DDR_DQ_7 1.20/1.35 V B
AD18 DDR_DQ_8 1.20/1.35 V B
AD24 DDR_DQ_9 1.20/1.35 V B
AD19 DDR_DQ_10 1.20/1.35 V B
AC21 DDR_DQ_11 1.20/1.35 V B
AC18 DDR_DQ_12 1.20/1.35 V B
AD23 DDR_DQ_13 1.20/1.35 V B
AD20 DDR_DQ_14 1.20/1.35 V B
AD21 DDR_DQ_15 1.20/1.35 V B
Data[0:31]
AF13 DDR_DQ_16 1.20/1.35 V B
AG17 DDR_DQ_17 1.20/1.35 V B
AG13 DDR_DQ_18 1.20/1.35 V B
AF17 DDR_DQ_19 1.20/1.35 V B
AF12 DDR_DQ_20 1.20/1.35 V B
AG18 DDR_DQ_21 1.20/1.35 V B
AG12 DDR_DQ_22 1.20/1.35 V B
AF18 DDR_DQ_23 1.20/1.35 V B
AC12 DDR_DQ_24 1.20/1.35 V B
AC16 DDR_DQ_25 1.20/1.35 V B
AC13 DDR_DQ_26 1.20/1.35 V B
AC15 DDR_DQ_27 1.20/1.35 V B
AD12 DDR_DQ_28 1.20/1.35 V B
AD16 DDR_DQ_29 1.20/1.35 V B
AD13 DDR_DQ_30 1.20/1.35 V B
AD15 DDR_DQ_31 1.20/1.35 V B

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Table 2-5 DDR4/DDR3L (cont.)

Pad # Pad name Voltage Type Description
AG22 DDR_DQS_0 1.20/1.35 V B
AG23 DDR_DQS_1 1.20/1.35 V B
AG15 DDR_DQS_2 1.20/1.35 V B
AG16 DDR_DQS_3 1.20/1.35 V B
Data strobe[0:3]
AF21 DDR_DQS_N_0 1.20/1.35 V B
AF23 DDR_DQS_N_1 1.20/1.35 V B
AF14 DDR_DQS_N_2 1.20/1.35 V B
AF16 DDR_DQS_N_3 1.20/1.35 V B
V23 DDR_DTO_0 1.20/1.35 V DO
Digital test output
W23 DDR_DTO_1 1.20/1.35 V DO
P27 DDR_ODT 1.20/1.35 V DO On-die termination
AB24 DDR_RAM_RST_N 1.20/1.35 V DO Reset output
U23 DDR_ZQ – AI, AO IO calibration pad (240 Ω 1%)

2.3.5 Mode

Table 2-6 Mode

Pad # Pad name Voltage Type Description
G5 MODE_0 1.8 V DI
Chip functional mode select
G4 MODE_1 1.8 V DI

2.3.6 PLL test clock

Table 2-7 PLL test clock

Pad # Pad name Voltage Type Description
AC4 PLL_TEST_DE_N 1.8 V B
PLL higher frequency test pin
AC5 PLL_TEST_DE_P 1.8 V B

2.3.7 PSGMII

Table 2-8 PSGMII

Pad # Pad name Voltage Type Description
J2 PSGMII_RXN 0.9 V AI
Receiver differential signal
J1 PSGMII_RXP 0.9 V AI

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Table 2-8 PSGMII (cont.)

Pad # Pad name Voltage Type Description
H2 PSGMII_TXN 0.9 V AO
Transmitter differential signal
H1 PSGMII_TXP 0.9 V AO
L4 CMN_ATEST 0.9 V AI, AO Analog test pin
J4 CMN_CLK_25M_OUT 0.9 V AO 25 MHz output clock
T2 CMN_CLK_50M_DE_N 0.9 V AO
T1 CMN_CLK_50M_DE_P 0.9 V AO
50 MHz differential output clock
L2 CMN_CLK_50M_DE_N2 0.9 V AO
L1 CMN_CLK_50M_DE_P2 0.9 V AO
L5 CMN_RBIAS 0.9 V AI, AO External resistor for BIAS
F1 CMN_REFCLK_SEL_0 1.8 V DI
CMN clock source selection
C1 CMN_REFCLK_SEL_1 1.8 V DI
H5 XTAL_I 0.9 V AI, AO Crystal in
H4 XTAL_O 0.9 V AI, AO Crystal out

2.3.8 SDC

Table 2-9 SDC

Pad # Pad name Voltage Type Description
AF1 SDC1_CLK 3.3 V/1.8 V B Clock
AF2 SDC1_CMD 3.3 V/1.8 V B Command
AD1 SDC1_DATA_0 3.3 V/1.8 V B Data0 for EMMC/SD
AD2 SDC1_DATA_1 3.3 V/1.8 V B Data1 for EMMC/SD
AE1 SDC1_DATA_2 3.3 V/1.8 V B Data2 for EMMC/SD
AE2 SDC1_DATA_3 3.3 V/1.8 V B Data3 for EMMC/SD
AG4 SDC1_DATA_4 3.3 V/1.8 V B Data4 only for EMMC
AF3 SDC1_DATA_5 3.3 V/1.8 V B Data5 only for EMMC
AG2 SDC1_DATA_6 3.3 V/1.8 V B Data6 only for EMMC
AG3 SDC1_DATA_7 3.3 V/1.8 V B Data7 only for EMMC

2.3.9 JTAG

Table 2-10 JTAG

Pad # Pad name Voltage Type Description
E2 SRST_N 1.8 V B JTAG reset for debug
F4 TCK 1.8 V DI JTAG test clock input

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Table 2-10 JTAG (cont.)

Pad # Pad name Voltage Type Description
F5 TDI 1.8 V DI JTAG test data input
F2 TDO 1.8 V DO JTAG test data output
E5 TMS 1.8 V DI JTAG test mode state
E4 TRST_N 1.8 V DI JTAG test reset

2.3.10 USB

Table 2-11 USB

Pad # Pad name Voltage Type Description
USB0
W2 USB_SS_TPA 0.925 V AI, AO USB0 SS test point
V2 USB0_HS_DM 3.3 V AI, AO
USB0 HS data
V1 USB0_HS_DP 3.3 V AI, AO
AB1 USB0_HS_REXT 0.925 V AI USB0 HS external resistor 4.02 KΩ 1%
AB2 USB0_SS_REXT 0.925 V AI USB0 SS external resistor 100 Ω 1%
AA2 USB0_SS_RXM 0.925 V AI
USB0 SS receive data
AA1 USB0_SS_RXP 0.925 V AI
Y2 USB0_SS_TXM 0.925 V AO
USB0 SS transmit data
Y1 USB0_SS_TXP 0.925 V AO

2.3.11 USXGMII

Table 2-12 USXMII

Pad # Pad name Voltage Type Description
P2 USXGMII0_RXN 0.9 V AI
Receiver differential signal
P1 USXGMII0_RXP 0.9 V AI
N2 USXGMII0_TXN 0.9 V AO
Transmitter differential signal
N1 USXGMII0_TXP 0.9 V AO

2.3.12 GPIO
Individual GPIO is configured by software using GPIO_CFGn registers corresponding to the
GPIO number.

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Table 2-13 GPIO pins

Pad FPIO_CFG[5:2]
Pad # Voltage Type Function Functional description
Name (FUNC_SEL)
B 0 GPIO_IN_OUT(0) Configurable I/O
B22 GPIO[0] 1.8 V DI 1 QPIC_PAD_TE LCDC TE, VSYNC input
DI 2 WCI2_RXD(0) Wi-Fi WCI 2.0 receive data
B 0 GPIO_IN_OUT(1) Configurable I/O
NAND BUSY_NOT_READY input.
B21 GPIO[1] 1.8 V DI 1 QPIC_PAD_BUSY_N
Active low.
DO 2 MAC1_SA0(2) Wi-Fi MAC1 smart antenna
B 0 GPIO_IN_OUT(2) Configurable I/O
LCDC RESX, reset signal. Active
A24 GPIO[2] 1.8 V DO 1 QPIC_PAD_LCD_RS_N
low.
DO 2 WCI2_TXD(0) Wi-Fi WCI 2.0 transmit data
B 0 GPIO_IN_OUT(3) Configurable I/O
C21 GPIO[3] 1.8 V DO 1 QPIC_PAD_WE_N NAND/LCDC write enable
DO 2 MAC0_SA0(1) Wi-Fi MAC0 smart antenna
B 0 GPIO_IN_OUT(4) Configurable I/O
A23 GPIO[4] 1.8 V DO 1 QPIC_PAD_OE_N NAND/LCDC read enable
DO 2 MAC0_SA1(1) Wi-Fi MAC0 smart antenna
B 0 GPIO_IN_OUT(5) Configurable I/O
B23 GPIO[5] 1.8 V DO 1 QPIC_PAD_DAT(4) NAND/LCDC data[4]
DO 2 MAC2_SA0(1) Wi-Fi MAC2 smart antenna
B 0 GPIO_IN_OUT(6) Configurable I/O
A26 GPIO[6] 1.8 V DO 1 QPIC_PAD_DAT(5) NAND/LCDC data[5]
DO 2 MAC2_SA1(1) Wi-Fi MAC2 smart antenna
B 0 GPIO_IN_OUT(7) Configurable I/O
A22 GPIO[7] 1.8 V
DO 1 QPIC_PAD_DAT(6) NAND/LCDC data[6]
B 0 GPIO_IN_OUT(8) Configurable I/O
B25 GPIO[8] 1.8 V
DO 1 QPIC_PAD_DAT(7) NAND/LCDC data[7]
B 0 GPIO_IN_OUT(9) Configurable I/O
DO 1 QPIC_PAD_LCD_CS_N LCD chip select
B26 GPIO[9] 1.8 V
DO 3 CXC_CLK(0) Wi-Fi WSI 1.0 clock
DO 4 MAC1_SA0(3) Wi-Fi MAC1 smart antenna
B 0 GPIO_IN_OUT(10) Configurable I/O
NAND CLE/LCDC DCX. CLE is
B27 GPIO[10] 1.8 V commend latch enable. Active
DO 1 QPIC_PAD_CLE_LB_N
high. DCX is data/commend. 1 is
data, 0 is commend.

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Table 2-13 GPIO pins (cont.)

Pad FPIO_CFG[5:2]
Pad # Voltage Type Function Functional description
Name (FUNC_SEL)
B 0 GPIO_IN_OUT(11) Configurable I/O
QPIC_PAD_NAND_CS_
DO 1 NAND chip select
A25 GPIO[11] 1.8 V N
DI 2 WCI2_RXD(2) Wi-Fi WCI 2.0 receive data
DO 3 MAC1_SA1(2) Wi-Fi MAC1 smart antenna
B 0 GPIO_IN_OUT(12) Configurable I/O
C27 GPIO[12] 1.8 V
DO 1 QPIC_PAD_DAT(1) NAND/LCDC data[1]
B 0 GPIO_IN_OUT(13) Configurable I/O
C26 GPIO[13] 1.8 V
DO 1 QPIC_PAD_DAT(2) NAND/LCDC data[2]
B 0 GPIO_IN_OUT(14) Configurable I/O
E27 GPIO[14] 1.8 V
DO 1 QPIC_PAD_DAT(3) NAND/LCDC data[3]
B 0 GPIO_IN_OUT(15) Configurable I/O
D27 GPIO[15] 1.8 V
DO 1 QPIC_PAD_DAT(0) NAND/LCDC data[0]
B 0 GPIO_IN_OUT(16) Configurable I/O
DO 1 QPIC_PAD_DAT(8) NAND/LCDC data[8]
B24 GPIO[16] 1.8 V
DO 2 CXC_DATA(0) Wi-Fi WSI 1.0 data
DO 3 MAC1_SA1(3) Wi-Fi MAC1 smart antenna
B 0 GPIO_IN_OUT(17) Configurable I/O
D26 GPIO[17] 1.8 V DO 1 QPIC_PAD_ALE_LB_N NAND ALE. Active high.
DO 3 WCI2_TXD(2) Wi-Fi WCI 2.0 transmit data
B 0 GPIO_IN_OUT(18) Configurable I/O
Audio Pulse Width Modulation
DO 1 PWM0(0)
E21 GPIO[18] 1.8 V interface 0
DI 3 WCI2_RXD(3) Wi-Fi WCI 2.0 receive data
DO 4 MAC1_SA0(1) Wi-Fi MAC1 smart antenna
B 0 GPIO_IN_OUT(19) Configurable I/O
Audio Pulse Width Modulation
DO 1 PWM1(0)
D22 GPIO[19] 1.8 V interface 1
DO 3 WCI2_TXD(3) Wi-Fi WCI 2.0 transmit data
DO 4 MAC1_SA1(1) Wi-Fi MAC1 smart antenna
B 0 GPIO_IN_OUT(20) Configurable I/O
D21 GPIO[20] 1.8 V Audio Pulse Width Modulation
DO 1 PWM2(0)
interface 2
B 0 GPIO_IN_OUT(21) Configurable I/O
E22 GPIO[21] 1.8 V Audio Pulse Width Modulation
DO 1 PWM3(0)
interface 3

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Pin definitions

Table 2-13 GPIO pins (cont.)

Pad FPIO_CFG[5:2]
Pad # Voltage Type Function Functional description
Name (FUNC_SEL)
B 0 GPIO_IN_OUT(22) Configurable I/O
L24 GPIO[22] 1.8 V Audio Pulse Width Modulation
DO 3 PWM0(2)
interface 0
B 0 GPIO_IN_OUT(23) Configurable I/O
G24 GPIO[23] 1.8 V Audio Pulse Width Modulation
DO 2 PWM1(2)
interface 1
B 0 GPIO_IN_OUT(24) Configurable I/O
G26 GPIO[24] 1.8 V Audio Pulse Width Modulation
DO 2 PWM2(2)
interface 2
B 0 GPIO_IN_OUT(25) Configurable I/O
H26 GPIO[25] 1.8 V Audio Pulse Width Modulation
DO 2 PWM3(2)
interface 3
B 0 GPIO_IN_OUT(26) Configurable I/O
J26 GPIO[26] 1.8 V Audio Pulse Width Modulation
DO 2 PWM0(4)
interface 0
B 0 GPIO_IN_OUT(27) Configurable I/O
G27 GPIO[27] 1.8 V Audio Pulse Width Modulation
DO 2 PWM1(4)
interface 1
B 0 GPIO_IN_OUT(28) Configurable I/O
H27 GPIO[28] 1.8 V Audio Pulse Width Modulation
DO 2 PWM2(4)
interface 2
B 0 GPIO_IN_OUT(29) Configurable I/O
K26 GPIO[29] 1.8 V Audio Pulse Width Modulation
DO 3 PWM0(3)
interface 0
B 0 GPIO_IN_OUT(30) Configurable I/O
N23 GPIO[30] 1.8 V Audio Pulse Width Modulation
DO 2 PWM1(3)
interface 1
B 0 GPIO_IN_OUT(31) Configurable I/O
L26 GPIO[31] 1.8 V Audio Pulse Width Modulation
DO 2 PWM2(3)
interface 2
B 0 GPIO_IN_OUT(32) Configurable I/O
L27 GPIO[32] 1.8 V Audio Pulse Width Modulation
DO 2 PWM3(3)
interface 3
K27 GPIO[33] 1.8 V B 0 GPIO_IN_OUT(33) Configurable I/O
B 0 GPIO_IN_OUT(34) Configurable I/O
J27 GPIO[34] 1.8 V DO 2 MAC1_SA0(0) Wi-Fi MAC1 smart antenna
DO 3 MAC0_SA0(0) Wi-Fi MAC0 smart antenna

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Pin definitions

Table 2-13 GPIO pins (cont.)

Pad FPIO_CFG[5:2]
Pad # Voltage Type Function Functional description
Name (FUNC_SEL)
B 0 GPIO_IN_OUT(35) Configurable I/O
M27 GPIO[35] 1.8 V DO 2 MAC1_SA1(0) Wi-Fi MAC1 smart antenna
DO 3 MAC0_SA1(0) Wi-Fi MAC0 smart antenna
B 0 GPIO_IN_OUT(36) Configurable I/O
M26 GPIO[36] 1.8 V
DO 2 MAC2_SA0(0) Wi-Fi MAC2 smart antenna
B 0 GPIO_IN_OUT(37) Configurable I/O
M24 GPIO[37] 1.8 V
DO 2 MAC2_SA1(0) Wi-Fi MAC2 smart antenna
B 0 GPIO_IN_OUT(38) Configurable I/O
DO 1 BLSP0_UART_RFR_N UART0 ready for receiving
E26 GPIO[38] 1.8 V
DO 2 BLSP0_I2C_SCL I2C0 clock
DO 3 BLSP0_SPI_CLK SPI0 clock
B 0 GPIO_IN_OUT(39) Configurable I/O
DI 1 BLSP0_UART_CTS_N UART0 clear to send
F26 GPIO[39] 1.8 V
DO 2 BLSP0_I2C_SDA I2C0 data
DO 3 BLSP0_SPI_CS_N SPI0 chip select
B 0 GPIO_IN_OUT(40) Configurable I/O
F27 GPIO[40] 1.8 V DI 1 BLSP0_UART_RX UART0 receive serial data
B 2 BLSP0_SPI_MISO SPI0 master-in slave- out data
B 0 GPIO_IN_OUT(41) Configurable I/O
H24 GPIO[41] 1.8 V DO 1 BLSP0_UART_TX UART0 transmit serial data
DO 2 BLSP0_SPI_MOSI SPI0 master-out slave-in data
B 0 GPIO_IN_OUT(42) Configurable I/O
DO 1 BLSP2_UART_RFR_N UART2 ready for receiving
F24 GPIO[42] 1.8 V
DO 2 BLSP2_I2C_SCL I2C2 clock
DO 3 BLSP2_SPI_CLK SPI2 clock
B 0 GPIO_IN_OUT(43) Configurable I/O
DI 1 BLSP2_UART_CTS_N UART2 clear to send
E23 GPIO[43] 1.8 V
DO 2 BLSP2_I2C_SDA I2C2 data
DO 3 BLSP2_SPI_CS_N SPI2 chip select
B 0 GPIO_IN_OUT(44) Configurable I/O
F23 GPIO[44] 1.8 V DI 1 BLSP2_UART_RX UART2 receive serial data
B 2 BLSP2_SPI_MISO SPI2 master-in slave- out data
B 0 GPIO_IN_OUT(45) Configurable I/O
D24 GPIO[45] 1.8 V DO 1 BLSP2_UART_TX UART2 transmit serial data
DO 2 BLSP2_SPI_MOSI SPI2 master-out slave-in data

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Pin definitions

Table 2-13 GPIO pins (cont.)

Pad FPIO_CFG[5:2]
Pad # Voltage Type Function Functional description
Name (FUNC_SEL)
B 0 GPIO_IN_OUT(46) Configurable I/O
L23 GPIO[46] 1.8 V
DO 1 BLSP5_I2C_SCL I2C5 clock
B 0 GPIO_IN_OUT(47) Configurable I/O
H23 GPIO[47] 1.8 V
DO 1 BLSP5_I2C_SDA I2C5 data
B 0 GPIO_IN_OUT(48) Configurable I/O
E9 GPIO[48] 1.8 V
DI 1 BLSP5_UART_RX UART5 receive serial data
B 0 GPIO_IN_OUT(49) Configurable I/O
E8 GPIO[49] 1.8 V
DO 1 BLSP5_UART_TX UART5 transmit serial data
B 0 GPIO_IN_OUT(50) Configurable I/O
Audio Pulse Width Modulation
K23 GPIO[50] 1.8 V DO 1 PWM0(1)
interface 0
DO 2 GP0_CLK(1) General Purpose clock
B 0 GPIO_IN_OUT(51) Configurable I/O
DI 1 PTA1_1 Wi-Fi Co-exist PTA 1
Audio Pulse Width Modulation
M23 GPIO[51] 1.8 V DO 2 PWM1(1)
interface 1
DO 3 GP1_CLK(1) General Purpose clock
DI 4 RX_LOS(1) Ethernet Loss of Signal
B 0 GPIO_IN_OUT(52) Configurable I/O
DO 1 PTA1_2 Wi-Fi Co-exist PTA 1
K24 GPIO[52] 1.8 V Audio Pulse Width Modulation
DO 2 PWM2(1)
interface 2
DO 3 GP2_CLK(1) General Purpose clock
B 0 GPIO_IN_OUT(53) Configurable I/O
DI 1 PTA1_0 Wi-Fi Co-exist PTA 1
G23 GPIO[53] 1.8 V
Audio Pulse Width Modulation
DO 2 PWM3(1)
interface 3
AC10 GPIO[54] 1.8 V B 0 GPIO_IN_OUT(54) Configurable I/O
B 0 GPIO_IN_OUT(55) Configurable I/O
DO 1 BLSP4_UART_RFR_N UART4 ready for receiving
AD10 GPIO[55] 1.8 V
DO 2 BLSP4_I2C_SCL I2C4 clock
DO 3 BLSP4_SPI_CLK SPI4 clock
B 0 GPIO_IN_OUT(56) Configurable I/O
DI 1 BLSP4_UART_CTS_N UART4 clear to send
AD8 GPIO[56] 1.8 V
DO 2 BLSP4_I2C_SDA I2C4 data
DO 3 BLSP4_SPI_CS_N SPI4 chip select

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Pin definitions

Table 2-13 GPIO pins (cont.)

Pad FPIO_CFG[5:2]
Pad # Voltage Type Function Functional description
Name (FUNC_SEL)
B 0 GPIO_IN_OUT(57) Configurable I/O
AC9 GPIO[57] 1.8 V DI 1 BLSP4_UART_RX UART4 receive serial data
B 2 BLSP4_SPI_MISO SPI4 master-in slave- out data
B 0 GPIO_IN_OUT(58) Configurable I/O
AD7 GPIO[58] 1.8 V DO 1 BLSP4_UART_TX UART4 transmit serial data
DO 2 BLSP4_SPI_MOSI SPI4 master-out slave-in data
B 0 GPIO_IN_OUT(59) Configurable I/O
AD6 GPIO[59] 1.8 V
DO 2 GP0_CLK(0) General Purpose clock
B 0 GPIO_IN_OUT(60) Configurable I/O
AD5 GPIO[60] 1.8 V
DO 2 GP1_CLK(0) General Purpose clock
B 0 GPIO_IN_OUT(61) Configurable I/O
AC6 GPIO[61] 1.8 V
DO 2 GP2_CLK(0) General Purpose clock
B 0 GPIO_IN_OUT(62) Configurable I/O
AC7 GPIO[62] 1.8 V
DI 1 SD_CARD_DETECT SD card detect
B 0 GPIO_IN_OUT(63) Configurable I/O
AC8 GPIO[63] 1.8 V DI 1 SD_WRITE_PROTECT SD card write protection
DI 2 RX_LOS(0) Ethernet Loss of Signal
B 0 GPIO_IN_OUT(64) Configurable I/O
D7 GPIO[64] 1.8 V
DO 1 MDC Management Data Clock
B 0 GPIO_IN_OUT(65) Configurable I/O
E6 GPIO[65] 1.8 V
B 1 MDIO Management Data Input/Output
B 0 GPIO_IN_OUT(66) Configurable I/O
DI 1 PTA2_0 Wi-Fi Co-exist PTA 2
C2 GPIO[66] 1.8 V
DI 2 WCI2_RXD(1) Wi-Fi WCI 2.0 transmit data
DO 3 CXC_CLK(1) Wi-Fi WSI 1.0 clock
B 0 GPIO_IN_OUT(67) Configurable I/O
D8 GPIO[67] 1.8 V
DI 1 PTA2_1 Wi-Fi Co-exist PTA 2
B 0 GPIO_IN_OUT(68) Configurable I/O
DO 1 PTA2_2 Wi-Fi Co-exist PTA 2
B3 GPIO[68] 1.8 V
DO 2 WCI2_TXD(1) Wi-Fi WCI 2.0 transmit data
DO 3 CXC_DATA(1) Wi-Fi WSI 1.0 data
B 0 GPIO_IN_OUT(69) Configurable I/O
DO 1 BLSP1_UART_RFR_N UART1 ready for receiving
B1 GPIO[69] 1.8 V
DO 2 BLSP1_I2C_SCL I2C1 clock
DO 3 BLSP1_SPI_CLK SPI1 clock

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Pin definitions

Table 2-13 GPIO pins (cont.)

Pad FPIO_CFG[5:2]
Pad # Voltage Type Function Functional description
Name (FUNC_SEL)
B 0 GPIO_IN_OUT(70) Configurable I/O
DI 1 BLSP1_UART_CTS_N UART1 clear to send
B2 GPIO[70] 1.8 V
DO 2 BLSP1_I2C_SDA I2C1 data
DO 3 BLSP1_SPI_CS_N SPI1 chip select
B 0 GPIO_IN_OUT(71) Configurable I/O
B4 GPIO[71] 1.8 V DI 1 BLSP1_UART_RX UART1 receive serial data
B 2 BLSP1_SPI_MISO SPI1 master-in slave- out data
B 0 GPIO_IN_OUT(72) Configurable I/O
A2 GPIO[72] 1.8 V DO 1 BLSP1_UART_TX UART1 transmit serial data
DO 2 BLSP1_SPI_MOSI SPI1 master-out slave-in data
B 0 GPIO_IN_OUT(73) Configurable I/O
DO 1 BLSP3_UART_RFR_N UART3 ready for receiving
A3 GPIO[73] 1.8 V
DO 2 BLSP3_I2C_SCL I2C3 clock
DO 3 BLSP3_SPI_CLK SPI3 clock
B 0 GPIO_IN_OUT(74) Configurable I/O
DI 1 BLSP3_UART_CTS_N UART3 clear to send
E7 GPIO[74] 1.8 V
DO 2 BLSP3_I2C_SDA I2C3 data
DO 3 BLSP3_SPI_CS_N SPI3 chip select
B 0 GPIO_IN_OUT(75) Configurable I/O
A4 GPIO[75] 1.8 V DI 1 BLSP3_UART_RX UART3 receive serial data
B 2 BLSP3_SPI_MISO SPI3 master-in slave- out data
B 0 GPIO_IN_OUT(76) Configurable I/O
D5 GPIO[76] 1.8 V DO 1 BLSP3_UART_TX UART3 transmit serial data
DO 2 BLSP3_SPI_MOSI SPI3 master-out slave-in data
B 0 GPIO_IN_OUT(77) Configurable I/O
D6 GPIO[77] 1.8 V
Z 1 BLSP3_SPI_CS1_N SPI3 additional CS[1]
B 0 GPIO_IN_OUT(78) Configurable I/O
D9 GPIO[78] 1.8 V
Z 1 BLSP3_SPI_CS2_N SPI3 additional CS[2]
B 0 GPIO_IN_OUT(79) Configurable I/O
D4 GPIO[79] 1.8 V
Z 1 BLSP3_SPI_CS3_N SPI3 additional CS[3]

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Pin definitions

2.3.13 Ground, power-supply and NC

Table 2-14 Ground, power-supply and NC pins
Pad # Pad name Description
Bias, calibration, reference, PLLs power
AE4 VBIAS_SDC1_1P25 Calibration delay circuit
V18, W16, W17 VDD_PLL_DDR_1P8 DDR PLL analog power
Reference voltage input for
Y23 VREF_DDR_CA command/address. Provided by
resistor divider.
VREF_DDR_DQ_0_ Reference voltage for data lane.
Y19
1 For DDR3L, provided by resistor
VREF_DDR_DQ_2_ divider.
Y15 For DDR4, internally generated.
3
T14 VDD_BM_PLL_1P8 PLL analog power 1.8 V
V16 VDD_HY_PLL_0P85 PLL analog power 0.85 V
VDD_QFPROM_ Power for programming Q-fuses;
Y8
BLOW_1P8 otherwise connect to ground
Core power
U12, U13, U14, U15, V12, V15, W12, W15,
VDD_APC0_0P8 Application processor core
Y13, Y14
H10, H11, H17, H18, J10, J11, J17, J18,
K8, K9, K12, K13, K15, K16, K19, K20, L8,
L9, M10, N8, N9, P9, R10, R17, R18, T10, VDDCX_1_0P8 Digital core
T17, T18, T19, T20, U8, U9, U17, V8, V9,
V17, W10, Y10
Memory power
L12, L13, L15, L16, L19, L20, M11, M17,
M18, N12, N13, N15, N16, N19, N20, P12,
VDDMX_1_0P85 Memory power
P13, P15, P16, P19, P20, R11, R14, R15,
T11, T15, W11, Y11
USB power
VDDA_USB_0_
AB3 High-speed analog and digital supply
CORE_0P925_HS
VDDA_USB0_
U4 Super-speed analog and digital supply
CORE_0P925_SS
VDDA_USB0_HS_
V4
1P8
High-speed high-voltage
VDDA_USB0_HS_
V5
3P3
VDDA_USB0_SS_
U5 Super-speed high-voltage
1P8
USXGMII power
VDDA_USXGMII0_
K4 Analog power for PLL
PLL_0P9

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Pin definitions

Table 2-14 Ground, power-supply and NC pins (cont.)

Pad # Pad name Description
VDDA_USXGMII0_
R4 Analog power for Rx
RX_0P85
VDDA_USXGMII0_
R5 Analog power for Tx
TX_0P85
PSGMII power
VDDA_PSGMII_
N5 Analog power for SGMII
0P85
VDDA_PSGMII_
N4 Analog power for PLL
PLL_0P9
Analog HV power for bandgap and bias
J5 VDDA_CMN_1P8
generation
VDDA_CMN_LDO_
P5 LDO input power
IN_1P2
VDDA_CMN_LDO_
K5 LDO output power
OUT_0P9
VDDA_CMN_PLL_
P4 Analog power for PLL
0P9
DDR VTT
VDDA_VTT_LDO_
AE11 VTT LDO output power
OUT_0P6_0P675
Wi-Fi power
Analog 1.2 V supply for the PHYA radio
D12, D13, E12, E13 VDDA_PHYA_1P2
interface
Analog 1.2 V supply for the PHYB radio
D14, D15, E14, E15 VDDA_PHYB_1P2
interface
A7 VDDA_WLAN_1P8 Analog 1.8 V for WLAN reference clock
Pad power
AC11, AC19, AC25, AE14, AE17, AE20, VDDPX_1_1P2_
Pad power for EBI (DDR)
AE22, AF27, AG26, T24, U25, Y25 1P35_VDDQ
Pad power for General power: MODE,
AD9, C4, C20, C23, E3, E25, J25, M25 VDDPX_3_1P8
JTAG, GPIOs, WSI
AD3, AE5 VDDPX_7_1P8_3P0 Pad power for SDC1
AE7, AB4 VDDA_1P8
AE9 VDDA_0P925 Pad for analog power
AB5 VDDA_3P3
Ground pad

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Pin definitions

Table 2-14 Ground, power-supply and NC pins (cont.)

Pad # Pad name Description
A5, A8, A11, A14, A17, A20, B5, B8, B11,
B14, B17, B20, C5, C7, C8, C10, C11,
C13, C14, C16, C17, C19, D16, E16, H12,
H13, H14, H15, H16, J12, J13, J14, J15,
J16, A1, A21, A27, AA4, AA5, AB25, AC1,
AC2, AC3, AC14, AC17, AC20, AC22,
AC24, AD11, AD14, AD17, AD22, AE13,
AE16, AE19, AE23, AE24, AF4, AF7, AF9,
AF11, AG1, AG5, AG7, AG9, AG11, AG27,
D3, D23, E24, G1, G2, G3, H8, H9, H19,
H20, H25, J8, J9, J19, J20, K1, K2, K3,
K10, K11, K14, K17, K18, L10, L11, L14, VSSX_0 Ground
L17, L18, M1, M2, M3, M4, M5, M8, M9,
M12, M13, M14, M15, M16, M19, M20,
N10, N11, N14, N17, N18, N24, N25, N26,
N27, P8, P10, P11, P14, P17, P18, P23,
P24, R1, R2, R3, R8, R9, R12, R13, R16,
R19, R20, T4, T5, T8, T9, T12, T16, T25,
U1, U2, U3, U10, U11, U18, U19, U20, V3,
V10, V11, V13, V14, V19, V20, W1, W5,
W8, W9, W13, W14, W18, W19, W20,
W25, Y9, Y12, Y16, Y17, Y18, Y20, T13,
U16
NC
AA23, AA24, AC23, R23, T23, W24, Y24,
AG10, AF10, AF5, AG8, AF8, AG6, AF6, NC Not connected pins
Y5, Y4, W4

2.3.14 Boot configuration GPIOs

Table 2-15 Boot configuration GPIOs
Pad name and/or Pad name or
Pad # Voltage Type Description
function alt function
Auth enable:
A24 BOOT_CONFIG[0] GPIO_2 1.8 V DI 0: No auth
1: Auth is required
C21 BOOT_CONFIG[1] GPIO_3 1.8 V DI Fast boot (boot interface select):
0: SPI-NOR
B27 BOOT_CONFIG[2] GPIO_10 1.8 V DI 1: eMMC
2: Para NAND
D26 BOOT_CONFIG[3] GPIO_17 1.8 V DI 3: USB 2.0
4: SPI-NOR-GPT
Hash in fuse (SW use only)
E22 BOOT_CONFIG[4] GPIO_21 1.8 V DI 0: PK hash is stored in boot ROM
1: PK hash is stored in OTP
Boot from ROM:
D22 BOOT_CONFIG[5] GPIO_19 1.8 V DI 0: boot from code ram
1: boot from rom

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Pin definitions

Table 2-15 Boot configuration GPIOs

Pad name and/or Pad name or
Pad # Voltage Type Description
function alt function
D21 BOOT_CONFIG[6] GPIO_20 1.8 V DI Boot ROM boot speed:
00: Uniphy CMN clock - 24MHz
01: GPLL0- 200MHz
E8 BOOT_CONFIG[7] GPIO_49 1.8 V DI 10: GPLL0- 400MHz
11: GPLL0- 800MHz
IMAGE_ENCRYPTION_ENABLE
K23 BOOT_CONFIG[8] GPIO_50 1.8 V DI 0: UIE Disable
1: UIE Enable
watchdog_enable
K24 BOOT_CONFIG[9] GPIO_52 1.8 V DI 0: watchdog enable.
1: watchdong disable (Default)
Use Serial Num:
AC10 BOOT_CONFIG[10] GPIO_54 1.8 V DI 0: Use Serial Num
1: Use OEM ID
D7 BOOT_CONFIG[11] GPIO_64 1.8 V DI Board Type[2:0] detect the board and
autoload the Configuration data table
G27 BOOT_CONFIG[12] GPIO_27 1.8 V DI 000: CP01
001: CP02
H27 BOOT_CONFIG[13] GPIO_28 1.8 V DI 010: CP03
0: Not force boot from USB
J26 forced_usb_boot GPIO_26 1.8 V DI
1: Force boot from USB
Note: All the boot configuration pins are internally weakly pulled down. Pull the pins to the correct values
externally on the board.

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 3 Electrical specifications

3.1 Absolute maximum ratings

Absolute maximum ratings (Table 3-1) reflect conditions that the IPQ6000 device may be exposed
to beyond the operating limits, without experiencing immediate functional failure. They are
limiting values, to be considered individually when all other parameters are within their specified
operating ranges. Functionality and long-term reliability can only be expected within the operating
conditions, as described in Section 3.2.

Table 3-1 Absolute maximum ratings

Parameter Min Max Unit
Power supply voltages
VBIAS_SDC1_1P25 SDC I/O pad bias voltage 2.09
VDD_PLL_DDR_1P8 DDR PLL analog power 2.057
VDD_HY_PLL_0P85 PLL analog power -0.3 2.057 V
VDD_BM_PLL_1P8 PLL analog power 2.057
VDD_QFPROM_BLOW Power for programming Q-fuses 2.057
VDDA_USB_0_1_CORE_0P925_HS High-speed analog and digital supply 1.0505
VDDA_USB0_SS_ 1P8 Super-speed high-voltage 2.057
VDDA_USB0_CORE_0P925_SS Super-speed analog and digital supply 1.0505
VDDA_USB0_HS_1P8 High-speed high-voltage -0.3 2.057 V
VDDA_USB0_HS_3P3 High-speed high-voltage 3.63
VDDA_USB1_HS_1P8 High-speed high-voltage 2.057
VDDA_USB1_HS_3P3 High-speed high-voltage 3.63
VDDA_CMN_1P8 Analog HV power for bandgap and bias 2.057
generation
VDDA_CMN_LDO_ IN_1P2 LDO input power 1.463
VDDA_CMN_PLL_ 0P9 Analog power for PLL -0.3 1.0505 V
VDDA_USXGMII0_PLL_0P9 Analog power for PLL 1.0505
VDDA_USXGMII0_RX_0P85 Analog power for Rx 1.0505
VDDA_USXGMII0_TX_0P85 Analog power for Tx 1.0505
VDDA_PSGMII _0P85 Analog power for SGMII 1.0505
-0.3 V
VDDA_PSGMII_PLL_0P9 Analog power for PLL 1.0505
VDDA_PHYA_1P2 5 GHz analog power 1.463
-0.3 V
VDDA18A_WLAN_1P8 5 GHz analog power 2.079
VDDA_PHYB_1P2 2.4 GHz analog power -0.3 1.463 V

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IPQ6000 Wi-Fi Access Point SoC Data Sheet Electrical specifications

Table 3-1 Absolute maximum ratings (cont.)

Parameter Min Max Unit
VDDPX_1_1P2_1P35_VDDQ Pad power for EBI (DDR) 1.62
VDDPX_3_1P8 Pad power for General power: MODE, 2.09
-0.3 V
JTAG, GPIOs
VDDPX_7_1P8_3P0 Pad power for SDC1 2.09
VDD_APC0_0P8 Power for VDD_APC pads
VDDCX_1_0P8 Power for VDDCX_1 pads -0.3 1.178 V
VDDMX_1_0P8 Power for VDDMX_1 pads
Tstore Storage temperature1 2 -55 150 °C
1. The storage temperature range applies when the device is in the OFF state (the device is not assembled
in any platform and is not electrically connected to any voltage or I/O signals). Damage may occur when
the device is subjected to this temperature for any length of time.
2. For devices shipped in tape and reel, the storage temperature range is +15°C to 35°C and relative
humidity (RH) is < 90%. QTI recommends allowing the device to return to ambient room temperature
before usage.

3.2 Operating conditions

Operating conditions include design team-controlled parameters including power supply voltage
and thermal conditions (Table 3-2). The IPQ6000 meets all performance specifications listed in
Section 3.3 through Section 3.10, when used within the operating conditions, unless otherwise
noted in those sections (provided the absolute maximum ratings have never been exceeded).

Table 3-2 Operating conditions

Parameter Min Typ11 Max Unit

Power supply voltages
VBIAS_SDC1_1P25 SDC I/O pad bias voltage 1.2 1.25 1.3 V
VDD_PLL_DDR_1P8 DDR PLL analog power 1.62 1.8 1.98 V
VREF_DDR_CA Reference voltage for 0.642 0.675 0.709 V
command/address
VREF_DDR_DQ_0_ 1 Reference voltage for data lane. For 0.642 0.675 0.709 V
DDR3L, provided by resistor divider.
VREF_DDR_DQ_2_ 3 For DDR4, internally generated. 0.642 0.675 0.709 V
VDD_HY_PLL_0P85 PLL analog power 0.765 0.85 1.09 V
VDD_BM_PLL_1P8 PLL analog power 1.7 1.8 1.9 V
VDD_QFPROM_BLOW Power for programming Q-fuses 1.71 1.8 1.89 V

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Table 3-2 Operating conditions (cont.)

Parameter Min Typ11 Max Unit

VDDA_USB_0_1_CORE_ High-speed analog and digital supply 0.879 0.925 0.971 V
0P925_HS
VDDA_USB0_SS_ 1P8 Super-speed high-voltage 1.71 1.8 1.89 V
VDDA_USB0_CORE_ Super-speed analog and digital 0.879 0.925 0.971 V
0P925_SS supply
VDDA_USB0_HS_1P8 High-speed high-voltage 1.71 1.8 1.89 V
VDDA_USB0_HS_3P3 High-speed high-voltage 2.945 3.3 3.63 V
VDDA_USB1_HS_1P8 High-speed high-voltage 1.71 1.8 1.89 V
VDDA_USB1_HS_3P3 High-speed high-voltage 2.945 3.3 3.63 V
VDDA_CMN_1P8 Analog HV power for bandgap and 1.71 1.8 1.89 V
bias generation
VDDA_CMN_LDO_ IN_ LDO input power 1.14 1.2 1.26 V
1P2
VDDA_CMN_PLL_ 0P9 Analog power for PLL 0.81 0.9 0.99 V
VDDA_USXGMII0_PLL_ Analog power for PLL 0.81 0.9 0.99 V
0P9
VDDA_USXGMII0_RX_ Analog power for Rx 0.765 0.85 0.935 V
0P85
VDDA_USXGMII0_TX_ Analog power for Tx 0.765 0.85 0.935 V
0P85
VDDA_PSGMII_0P85 Analog power for SGMII 0.765 0.85 0.935 V
VDDA_PSGMII_PLL_0P9 Analog power for PLL 0.81 0.9 0.99 V
VDDA_PHYA_1P2 5 GHz analog power 1.14 1.2 1.26 V
VDDA_WLAN_1P8 5 GHz analog power 1.71 1.8 1.89 V
VDDA_PHYB_1P2 2.4 GHz analog power 1.14 1.2 1.26 V
VDDPX_1_1P2_1P35_ Pad power for EBI (DDR) 1.14/1.283 1.2/1.35 1.26/1.417 V
VDDQ
VDDPX_3_1P8 Pad power for General power: 1.65 1.8 1.95 V
MODE, JTAG, GPIOs
VDDPX_7_1P8_3P0 Pad power for SDC1 1.65/2.85 1.8/3.0 1.95/3.15 V
Thermal conditions
Device operating temperature (case) 0 +25 110 °C
TC Fuse programming temperature
+10 +25 110 °C
(case)
1. Typical voltages represent the recommended output settings of the companion PMIC device.

Table 3-3 Operating conditions for voltage rails with AVS

Parameter11 Min Typ Max Unit

Turbo L1 0.8500 – 1.0625 V
VDD_APC0_0P8 Nominal 0.7125 – 0.8625 V
SVS 0.6000 – 0.7250 V

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Table 3-3 Operating conditions for voltage rails with AVS (cont.)

Parameter11 Min Typ Max Unit

VDDCX_1_0P8 Nominal 0.7125 – 0.8625 V
0.850 – 0.9875 V
VDDMX_1_0P8 Turbo Nominal
0.850 – 0.9125 V
1. Parts with voltages outside of the specified ranges are not guaranteed to operate properly.

3.3 Power sequencing

The MP5496 PMIC and external RC networks on some of the discrete SMPS and LDO devices
provide the proper power sequencing for the IPQ6000 chipset.

The power-on sequence is shown in Figure 3-1.

Vin System =12V

3.3V vin MP5496, 3.3V USB2 & other 3.3V devices
E‐SMPS8 (3.3V)

MP5496 AUTOON

MP5496 PMIC – PON Sequence (2ms delay per slot)

MP5496 DCDC1 (1.00V) VDD_MX

MP5496 DCDC3 (0.90V) VDD_CX

MP5496 DCDC2 (0.90V) VDD_CX_APC

MP5496 DCDC4 (1.80V) PLLs, Copper, USB and PCIe Analog

MP5496 LDO4 (1.20V) 1.2V Copper 2G/5G Analog I/Q

MP5496 LDO5 (0.90V) VDDA USB2, USB3, PCIe PHY

MP5496 LDO2 (3.00V) PX7_SDC1 (SDC I/O)

E‐LDO/SMPS – PON Sequences

Enabled by LDO4
E‐LDO1 (0.85V) VDDA Ethernet PHY
Enabled by 3.3

E‐SMPS15 (1.35/1.2V) VDD_PX1 (1.35V DDR3L or 1.2V DDR4)

Enabled by 12V In + 10 ms
E‐SMPS10 (1.8V) 1.8V Analog & Digital Copper and QCN5x2x/QCN5x52 2G/5G 1.8V QCA8081, IPQ60xx PX3, & other 1.8V devices
Enabled by E‐SMPS10 + 1ms

E‐LDO3 (1.05V) 1.05V QCN5x2x/QCN5x52 2G/5G

Enabled by E‐SMPS10 + 2ms

E‐LDO4 (2.2V) 2.2V, QCN5x52 5G

Enabled by E‐LDO4
2.2V, QCN5x21 2G w/ iPA
E‐SMPS13 (2.2V)

RSTO delay = DCDC4 + 100 ms

MP5496 RSTO (OTP Configurable: 10 ms < Delay < 140 ms)

Figure 3-1 IPQ6000 Power-on sequence

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3.4 Digital-logic characteristics

A digital I/O’s performance specification depends on its pad type, its usage, and/or its supply
voltage:
 Some digital I/Os are dedicated for interconnections between the IPQ6000 and other ICs
within the QTI chipset; therefore, specifications are not required.
 Some digital I/Os are defined by existing standards, such as I2C and SPI. QTI devices comply
with those standards; therefore, additional specifications are not required.
 All other digital I/Os require performance specifications
.

Table 3-4 Digital I/O characteristics for VDDPX_1 (1.2 V or 1.35 V)

Parameter Comments Min Max Unit
VREF Reference voltage 0.49 × VDDPX_1 0.51 × VDDPX_1 V

VIH High-level input voltage,

0.65 × VDDPX_1 – V
CMOS/Schmitt-LPRx

VIL Low-level input voltage

– 0.35 × VDDPX_1 V
CMOS/Schmitt-LPRx

VIH High-level input voltage,

VDDPX_1/2 + 0.1 – V
CMOS/Schmitt-MPRx

VIL Low-level input voltage

– VDDPX_1/2 - 0.1 V
CMOS/Schmitt-MPRx

IIH Input high leakage current, no

– 5 µA
pulldown
IIL Input low leakage current, no pullup -5 – µA

IIHPD Input high leakage current, with

40 3000 µA
pulldown
IILPU Input low leakage current, with pullup -3000 -40 µA
High-level output voltage, CMOS, at
VOH 0.355 – V
rated drive strength-config G11
Low-level output voltage, CMOS, at
VOL – 0.35 V
rated drive strength- config G22

IOZHKP High-level, tri-state leakage, with

-1200 -10 µA
keeper

IOZLKP Low-level, tri-state leakage, with

10 1200 µA
keeper
CI/O I/O capacitance 1.25 2.5 pF
1. See Table 2-1 for each output pin’s drive strength (IOH and IOL); the drive strengths of many output pins
are programmable, and depend on the associated supply voltage.
2. Input capacitance and I/O capacitance values are guaranteed by design, but not 100% tested.

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Table 3-5 DC specification of VDDPX_3 = 1.8 V GPIOs

Parameter Description Min Max Units

VIH High-level input voltage, CMOS/Schmitt,

0.65 × VDDPX_x VDDPX_x + 0.3 V V
(hihys_en = LOW)

VIL Low-level input voltage, CMOS/Schmitt,

-0.3 V 0.35 × VDDPX_x V
(hihys_en = LOW)

VIH High-level input voltage, CMOS/Schmitt,

0.7 × VDDPX_x VDDPX_x+ 0.3 V V
(hihys_en = HIGH)

VIL Low-level input voltage, CMOS/Schmitt,

-0.3 V 0.3 × VDDPX_x V
(hihys_en = HIGH)

VSHYS Schmitt hysteresis voltage, 

100 – mV
(hihys_en = LOW)

VSHYS Schmitt hysteresis voltage, 

300 – mV
(hihys_en = HIGH)
Input high leakage current with no
IIH – 1 µA
pulldow11
IIL Input low leakage current with no pull-up1 -1 – µA

IIHPD 27.5 97.5 µA

Input high leakage current with pull-down
(60 K) (20 K) Ω

IILPU -97.5 -27.5 µA

Input low leakage current with pull-up
(20 K) (60 K) Ω
High-level, tri-state leakage current with
IOZH – 1 µA
no pulldown1
Low-level, tri-state leakage current with
IOZL -1 – µA
no pullup1

IOZHPD High-level, tri-state leakage current with 27.5 97.5 µA

pull-down (60 K) (20 K) Ω

IOZLPU Low-level, tri-state leakage current with 97.5 27.5 µA

pull-up (20 K) (60 K) Ω
High-level, tri-state leakage current with -22.5 -7.5 µA
IOZHKP
keeper22 (20 K) (60 K) Ω
Low-level, tri-state leakage current with 7.5 22.5 µA
IOZLKP
keeper 2 (60 K) (20 K) Ω
VOH High-level output voltage, CMOS VDDPX_x - 0.45 VDDPX_x V
VOL Low-level output voltage, CMOS 0.0 0.45 V
RPULL-UP Pull-up resistance 20 K 60 K Ω
RPULL-
Pull-down resistance 20 K 60 K Ω
DOWN

RKEEPER-UP Keeper-up resistance 20 K 60 K Ω

RKEEPER-
Keeper-down resistance 20 K 60 K Ω
DOWN

RFFE pins
RPULL-UP Pull-up resistance – 41.25 K Ω

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Table 3-5 DC specification of VDDPX_3 = 1.8 V GPIOs (cont.)

Parameter Description Min Max Units
RPULL- Pull-down resistance – 41.25 K Ω
DOWN

RKEEPER-UP Keeper-up resistance – 41.25 K Ω

RKEEPER- Keeper-down resistance – 41.25 K Ω

DOWN

1. Pin voltage = VDDPX_x maximum. For keeper pins, pin voltage = VDDPX_x maximum - 0.45 V.
2. Pin voltage = GND and supply = VDDPX_x maximum. For keeper pins, pin voltage = 0.45 V and supply =
VDDPX_x maximum.

Table 3-6 Digital I/O characteristics for VDDPX_7 = 1.8/3.0 V nominal (SDC1)
Parameter Description Min Typ Max Units

VOH High-level output

VDDPX_7 - 0.45 V – – V
voltage

VOL Low-level output

– – 0.45 V V
voltage

VIH High-level input

0.65 × VDDPX_7 – VDDPX_7 + 0.3 V V
voltage

VIL Low-level input

-0.3 V – 0.35 × VDDPX_7 V
voltage
Ω
RPULL-UP Pull-up resistance 10 K – 100 K

Ω
RPULL-DOWN Pull-down resistance 10 K – 100 K

In all digital I/O cases, VOL, and VOH are linear functions (Figure 3-2) regarding the drive current
(drive currents are given in Table 2-1). They can be calculated using the following relationships:

% drive  450
Vol [max]  mV
100
 % drive  450 
Voh [min]  V DDPX _ X    mV
 100 

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VOL (max) VOH (min)

100 100

80 80
% Drive

% Drive
60 60

40 40

20 20

0 0
0 0.15 0.30 0.45 V DDPX_X – 0.45 V DDPX_X – 0.30 VDDPX_X – 0.15 VDDPX_X
Output voltage Output voltage

Figure 3-2 IV curve for VOL and VOH (valid for all VDDPX_X)

3.5 Timing characteristics

Specifications for the device timing characteristics are included (where appropriate) under each
function’s section, along with all its other performance specifications. Some general comments
about timing characteristics and pertinent pad design methodologies are included in this section.

NOTE: All IPQ6000 devices are characterized with actively terminated loads; therefore, all
baseband timing parameters in this document assume no bus loading. This is
described in more detail in Section 3.5.2.

3.5.1 Timing diagram conventions

The conventions used within timing diagrams throughout this document are shown in Figure 3-3.

Waveform Description
Don't care or bus is driven

Signal is changing from low to high

Signal is changing from high to low

Bus is changing from invalid to valid

Keeper Bus is changing from valid to keeper

Bus is changing from Hi-Z to valid

Denotes multiple clock periods

Figure 3-3 Timing diagram conventions

For each signal in the diagram:

 One clock period (T) extends from one rising clock edge to the next rising clock edge.

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 The high level represents 1, the low level represents 0, and the middle level represents the
floating (high-impedance) state.
 When both the high and low levels are shown over the same time interval, the meaning
depends on the signal type:
 For a bus type signal (multiple bits), the processor or external interface is driving a value,
but that value may or may not be valid.
 For a single signal, this indicates don’t care.

3.5.2 Rise and fall time specifications

The testers that characterize IPQ6000 devices have actively terminated loads, making the rise and
fall times quicker (mimicking a no-load condition). The impact that different external load
conditions have on rise and fall times is shown in Figure 3-4.

Specified switch low points Specified switch high points

(active terminated load) (active terminated load)
Actual switch low
VDDPX_X
point at 30 pF
Simulated driving VOH
30 pF signal load VOL
Actual switch high
0V
point at 30 pF
Actual switch low
VDDPX_X
point at 80 pF
Simulated driving VOH
80 pF signal load VOL
Actual switch high
0V
point at 80 pF

Figure 3-4 Rise and fall times under different load conditions

To account for external load conditions, rise or fall times must be added to parameters that start
timing at the IPQ6000 and terminate at an external device (or vice versa). Adding these rise and
fall times is equivalent to applying capacitive load derating factors.

3.6 Memory support

All timing parameters in this document assume no bus loading. Rise/fall time numbers must be
factored into the numbers in this document. For example, setup-time numbers may get worse, and
hold time numbers may get better.

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3.6.1 DDR4/DDR3L
Table 3-7 Supported DDR4/DDR3L standards and exceptions
Applicable standard Feature exceptions IPQ variations
JESD79-4B – DDR4 specification None None
JESD79-3F – DDR3L specification None None

3.6.2 eMMC on SDC1

eMMC NAND flash can be supported via the SDC1 port. See Section 3.7.3 for secure digital
interface details.

3.6.3 NOR memory on SPI

SPI can be used to support NOR memory devices with appropriate user-modified software. See
Section 3.7.1 for serial peripheral interface details.

3.7 Connectivity
The connectivity functions supported by the IPQ6000 that require electrical specifications include:
 SD, including SD cards and MMC
 USB host/slave support with built-in physical layer (PHY)
 Through proper configuration of the six BLSP ports:
 Universal asynchronous receiver/transmitter (UART) ports
 Inter-integrated circuit (I2C) interfaces
 Serial peripheral interface (SPI) ports
Pertinent specifications for these functions are detailed in the following subsections.

NOTE: In addition to the following hardware specifications, refer to the latest software release
notes for software-based performance features or limitations.

3.7.1 Serial peripheral interface

The IPQ6000 supports SPI as a master only. Any one of the six BLSP ports can be configured as
an SPI master.

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SPI_CS_N to SPI_CLK timing is fixed at 1 clock period.

SPI_CS_N
T
T 50% clock duty cycle is shown, but is not a requirement.
SPI_CLK
t(mov)
t(mov) value is positive if after clock transition (shown); negative if before.
SPI_DATA_MOSI
t(mis) t(mih)
SPI_DATA_MISO

Figure 3-5 SPI master timing diagram

Table 3-8 SPI master timing characteristics

Parameter Comments Min Typ Max Unit

T (SPI clock period)11 50 MHz maximum 20 – – ns

t(ch) Clock HIGH 8 – – ns

t(cl) Clock LOW 8 – – ns
t(mov) Master output valid -5 – 5 ns
t(mis) Master input setup 5 – – ns
t(mih) Master input hold 1 – – ns
1. The minimum clock period includes 1% jitter of maximum frequency.

3.7.2 Parallel NAND and display interface

The Qualcomm Parallel Interface Controller (QPIC) is an enhanced and modified version of the
previously known EBI2 controller. The External Bus Interface 2 (EBI2) is an external memory
interface and is targeted to be the interface for slow peripheral devices. The feature in chip
supports LCD and Parallel NAND device.

Table 3-9 Supported LCD controller standards and exceptions

Applicable standard Feature exceptions IPQ variations
The LCD controller supports the MIPI DBI type B device standard
interface.
The LCD controller has a device register writes/reads and device None None
data writes support, when device register transfers are treated
over 8 pins interface.

Table 3-10 Supported NAND standards and exceptions

Applicable standard Feature exceptions IPQ variations
Support NAND ONFI 1.0 JEDEC None None

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3.7.3 SD interfaces
Table 3-11 Supported SD standards and exceptions
Applicable standard Feature exceptions IPQ variations
Embedded Multimedia Card (e.MMC) Specification HS400 mode is not
None
version 5.1 supported
Secure Digital: Physical Layer Specification None
None
version 3.0
SDIO Card Specification version 3.0 None None

3.7.4 USB interfaces

Table 3-12 Supported USB standards and exceptions
Applicable standard Feature exceptions IPQ variations
Universal Serial Bus Specification, Revision 3.1 SS Gen 2 Operating voltages, system
(August 11, 2014 or later) clock, and VBUS

3.7.5 I2C interface

Table 3-13 Supported I2C standards and exceptions
Applicable standard Feature exceptions IPQ variations
Multi-master, slave mode,
I2C Specification, version 3.0 None and 10-bit addressing are not
supported.

3.7.6 PWM interfaces

The IPQ6000 has a four-channel PWM controller. Each channel has a 16-bit pre-divider and a 
16-bit divider. The output frequency of each channel can be as low as 1 Hz. The frequency and
duty cycle are configurable via software. The PWM controller can be used for LED control.

The following figure shows the internal structure of the PWM controller.

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TCSR

PWM
DIV_PRE DIV out0

out1
DIV_PRE DIV
100 MHz
GCC TLMM
out2
DIV_PRE DIV

out3
DIV_PRE DIV

Figure 3-6 PWM controller

3.8 UniPHY interfaces

3.8.1 PSGMII interface

Table 3-14 PSGMII transmitter DC electrical characteristics
Symbol Parameter Min Typ Max Unit
T_BAUD Transmitter baud rate – 6.250 – Gbps

T_Vdiff1 Output differential voltage (into the load Rload=100 ) 400 – 850 mVppd

T_Rdiff Differential output impedance 80 100 120 

T_Vcm2 Output common mode voltage 0.375 0.425 0.475 V

1. The output differential voltage is affected by power supply voltage which is assumed 850 mV ±10%.
2. The output common mode voltage is affected by power supply voltage which is assumed 850 mV ±10%.

Table 3-15 PSGMII receiver DC electrical characteristics

Symbol Parameter Min Typ Max Unit
R_BAUD Receiver baud rate – 6.250 – Gbps
R_Vdiff Input differential voltage 100 – 1200 mVppd
R_Rdiff Differential input impedance 80 100 120 

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Transmitter Eye Receiver Eye

T_Y2 R_Y2

T_Y1
Amplitude mV

R_Y1
0 0

-R_Y1
-T_Y1

-T_Y2 -R_Y2

0.0 T_X1 T_X2 1-T_X2 1-T_X1 1.0 0.0 R_X1 0.5 1-R_X1 1.0
Time UI Time UI

Figure 3-7 PSGMII jitter eye diagrams

Table 3-16 PSGMII transmitter jitter specifications

Symbol Parameter Min Typ Max Unit
T_DCD Duty cycle distortion – – 0.05 UIpp
T_TJ Total jitter – – 0.30 UIpp
T_X1 Eye mask – – 0.15 UI
T_X2 Eye mask – – 0.40 UI
T_Y1 Eye mask 200 – – mV
T_Y2 Eye mask – – 450 mV

Table 3-17 PSGMII receiver jitter specifications

Symbol Parameter Min Typ Max Unit
R_TJ Total jitter – – 0.60 UIpp
R_X1 Eye mask – – 0.30 UI
R_Y1 Eye mask 50 – – mV
R_Y2 Eye mask – – 450 mV

3.8.2 QSGMII interface

Table 3-18 QSGMII transmitter DC electrical characteristics
Symbol Parameter Min Typ Max Unit
T_BAUD Transmitter baud rate – 5.0 – Gbps

T_Vdiff1 Output differential voltage (into the load Rload=100 ) 400 – 850 mVppd

T_Rdiff Differential output impedance 80 100 120 

T_Vcm2 Output common mode voltage 0.375 0.425 0.475 V

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1. The output differential voltage is affected by power supply voltage which is assumed 850 mV ±10%.
2. The output common mode voltage is affected by power supply voltage which is assumed 850 mV ±10%.

Table 3-19 QSGMII receiver DC electrical characteristics

Symbol Parameter Min Typ Max Unit
R_BAUD Receiver baud rate – 5.0 – Gbps
R_Vdiff Input differential voltage 100 – 1200 mVppd
R_Rdiff Differential input impedance 80 100 120 

Transmitter Eye Receiver Eye

T_Y2 R_Y2

T_Y1
Amplitude mV

R_Y1
0 0

-R_Y1
-T_Y1

-T_Y2 -R_Y2

0.0 T_X1 T_X2 1-T_X2 1-T_X1 1.0 0.0 R_X1 0.5 1-R_X1 1.0
Time UI Time UI

Figure 3-8 QSGMII jitter eye diagrams

Table 3-20 QSGMII transmitter jitter specifications

Symbol Parameter Min Typ Max Unit
T_DCD Duty cycle distortion – – 0.05 UIpp
T_TJ Total jitter – – 0.30 UIpp
T_X1 Eye mask – – 0.15 UI
T_X2 Eye mask – – 0.40 UI
T_Y1 Eye mask 200 – – mV
T_Y2 Eye mask – – 450 mV

Table 3-21 QSGMII receiver jitter specifications

Symbol Parameter Min Typ Max Unit
R_TJ Total jitter – – 0.60 UIpp
R_X1 Eye mask – – 0.30 UI
R_Y1 Eye mask 50 – – mV
R_Y2 Eye mask – – 450 mV

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3.8.3 SGMII+ interface

Table 3-22 SGMII+ transmitter DC electrical characteristics
Symbol Parameter Min Typ Max Unit
T_BAUD Transmitter baud rate – 3.125 – Gbps

T_Vdiff1 Output differential voltage (into the load Rload=100 ) 400 – 850 mVppd

T_Rdiff Differential output impedance 80 100 120 

T_Vcm2 Output common mode voltage 0.375 0.425 0.475 V

1. The output differential voltage is affected by power supply voltage which is assumed 850 mV ±10%.
2. The output common mode voltage is affected by power supply voltage which is assumed 850 mV ±10%.

Table 3-23 SGMII+ receiver DC electrical characteristics

Symbol Parameter Min Typ Max Unit
R_BAUD Receiver baud rate – 3.125 – Gbps
R_Vdiff Input differential voltage 100 – 1200 mVppd
R_Rdiff Differential input impedance 80 100 120 

Table 3-24 SGMII+ transmitter jitter specifications

Symbol Parameter Min Typ Max Unit
T_TJ Total jitter – – 0.35 UIpp

Table 3-25 SGMII+ receiver jitter specifications

Symbol Parameter Min Typ Max Unit
R_TJ Total jitter – – 0.60 UIpp

3.8.4 SGMII interface

Table 3-26 SGMII transmitter DC electrical characteristics
Symbol Parameter Min Typ Max Unit
T_BAUD Transmitter baud rate – 1.250 – Gbps

T_Vdiff1 Output differential voltage (into the load Rload=100 ) 400 – 850 mVppd

T_Rdiff Differential output impedance 80 100 120 

T_Vcm2 Output common mode voltage 0.375 0.425 0.475 V

1. The output differential voltage is affected by power supply voltage which is assumed 850 mV ±10%.
2. The output common mode voltage is affected by power supply voltage which is assumed 850 mV ±10%.

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Table 3-27 SGMII receiver DC electrical characteristics

Symbol Parameter Min Typ Max Unit
R_BAUD Receiver baud rate – 1.250 – Gbps
R_Vdiff Input differential voltage 100 – 1200 mVppd
R_Rdiff Differential input impedance 80 100 120 

Table 3-28 SGMII transmitter jitter specifications

Symbol Parameter Min Typ Max Unit
T_DCD Duty cycle distortion – – 30 ps
T_CCJ Cycle to cycle clock jitter – – 100 ps
T_DDJ Data dependent jitter – – 70 ps
T_TJ Total jitter – – 300 ps

Table 3-29 SGMII receiver jitter specifications

Symbol Parameter Min Typ Max Unit
R_TJ Total jitter – – 500 ps

3.9 Internal functions

Some internal functions require external interfaces to enable their operation. These include clock
generation, modes and resets, and JTAG functions.

3.9.1 Clocks
Clocks that are specific to particular functions are addressed in the corresponding sections of this
document. Others are specified here.

3.9.1.1 WLAN Reference requirements – 48 MHz

The differential WLAN reference clock is driven to IPQ6000 from the companion radio
transceiver IC.

Parameter Conditions Min Typ Max Units

Input frequency – – 48 – MHz
Frequency tolerance over operating temperature – -20 – 20 ppm
Duty cycle of input signal – 40 50 60 %
Differential amplitude – 0.4 – 0.8 V
TIE RMS jitter specification – – – 2 ps

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Parameter Conditions Min Typ Max Units

Input termination (differential)1 – – 100 – 

1. The clock between the companion radio transceiver and IPQ6000 should be routed using a 100 
differential (50  single-ended) transmission line.

3.9.2 Modes and resets

Mode and reset functions are basic digital I/Os that meet the performance specifications presented
in Section 3.4.

3.9.3 JTAG
t(tckcy)
t(tckh) t(tckl)
TCK

t(htms)
t(sutms)
TMS

t(htdi)
t(sutdi)
TDI
t(do)
TDO

Figure 3-9 JTAG interface timing diagram

Table 3-30 JTAG interface timing characteristics

Parameter Comments Min Typ Max Unit
t(tckcy) TCK period 50 – – ns
t(tckh) TCK pulse width high 20 – – ns
t(tckl) TCK pulse width low 20 – – ns
t(sutms) TMS input setup time 5 – – ns
t(htms) TMS input hold time 20 – – ns
t(sutdi) TDI input setup time 5 – – ns
t(htdi) TDI input hold time 20 – – ns
t(do) TDO data output delay – – 15 ns

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3.10 Analog IQ interfaces

The analog I/Q interface signals between IPQ6000 and the companion radio transceiver in a
QCN5021/QCN5121/QCN5022/QCN5052/QCN5122/QCN5152 device are listed in Table 3-31.
IPQ6000 has four sets of analog I/Q interfaces, one for each RF chain. The I/Q baseband analog
interface consists of four transmission lines shared between the Tx and Rx paths. In Tx mode these
four lines are used to connect DAC output pins to Tx BBF input pins; the ADC input pins and Rx
BBF output pins are in high-Z mode. For Rx mode, conversely, the four lines are used to connect
the Rx BBF output pins to ADC input pins as the DAC outputs and Tx BBF inputs are in high-Z
mode.

Table 3-31 Analog interface signals

Direction (with respect
Signal name1 Description
to RF)
Baseband analog I negative, multiplexed between
PHYx_CHy_IN Analog I/O
TX_IN and RX_IN on the RF side. See Table 3-32.
Baseband analog I positive, multiplexed between
PHYx_CHy_IP Analog I/O
TX_IP and RX_IP on the RF side. See Table 3-32.
Baseband analog Q negative, multiplexed between
PHYx_CHy_QN Analog I/O
TX_QN and RX_QN on the RF side. See Table 3-32.
Baseband analog Q positive, multiplexed between
PHYx_CHy_QP Analog I/O
TX_QP and RX_QP on the RF side. See Table 3-32.
1. Where x = A or B, and y = 0 or 1.

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The electrical specifications of the interface signals can be found in Table 3-32.

Table 3-32 Analog I/Q interface specifications

Specification Comments Min Typ Max Units
External parasitic
Maximum interconnect capacitance I capacitance on I or Q
– – 7 pF
or Q, single ended 1 inputs due to board
routing, connector, etc.
Tx mode operation
Tx I or Q load impedance for normal
DC to 45 MHz – 100 – 
operation mode, differential
Tx mode, AC current positive or
– 1 – mApp
negative inputs (I or Q)
Tx mode, common mode voltage on
– 0.3 – V
either positive or negative input (I or Q)
Rx mode operation
Rx I/Q differential input voltage -1.4 – +1.4 V
Common mode voltage on either
0.45 0.5 0.55 V
positive or negative output (I or Q)
1. 50  strip transmission lines should be used for I/Q baseband analog interface signals.

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 4 Mechanical information

4.1 Device physical dimensions

The IPQ6000 device is available in the 18.1 mm × 18.1 mm × 1.7 mm FCBGA package that
includes a ground pad for improved grounding, mechanical strength, and thermal continuity. Pin 1
is located by an indicator mark on the top of the package.

Figure 4-1 shows the IPQ6000 device mechanical dimensions, top and bottom views.

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Figure 4-1 IPQ6000 mechanical dimensions, top and bottom views

NOTE: Unless otherwise specified:

1. Interpret drawing per ASME Y14.100.

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2. All dimensions shown on this drawing are in millimeters (mm).

3. Interpret dimension and tolerances per ASME Y14.5-2009.
4. Workmanship shall be in accordance with Qualcomm package assembly workmanship
standard 80-V0691-2.
5. Qualcomm supplied electronic database(s) are for reference only. Dimensional information on
current revision of released drawing takes precedence over electronic database(s).
6. Change approval. All changes shall be in accordance with 80-V3652-1 General Supplier
Quality Requirement.
7. Dimension measured at the maximum solder ball diameter, parallel to the primary datum -C-.
8. The seating plane is defined by three non-colinear balls that support the free standing package
when it is placed on the flat surface. The vectors formed by the three balls establishing the
seating plane shall include the center of gravity.
9. Primary datum -C- is determined by the first order LMS regression plane through the spherical
crowns of all solder balls on this side of the package.
10. Maximum package height determined by RSS tolerance method.
11. Allowable component area. Maximum component height shall not exceed 0.40 mm.
12. Dimension includes (0.08 mm) bump standoff with underfill.
13. Underfill area, package contact prohibited.
14. Ink not permitted on die and substrate surfaces.

4.2 Part marking

Line P1 Qualcomm
Line P2
IPQ6000
[Variant]
Line P3

Line E

Line T1 FAYWWXXX

Ball A1 identifier

Figure 4-2 IPQ6000 device marking

Table 4-1 Package marking line description

Line Marking Description
Line P1 Qualcomm Qualcomm name
Line P2 IPQ6000 Qualcomm Technologies, Inc. product name

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Table 4-1 Package marking line description (cont.)

Line Marking Description
Line P3 [Variant] Device variant information
 See Table 4-2 for assigned values.
Line T1 FAYWWXXX F = source of supply code
 F = H (GLOBALFOUNDRIES)
A = assembly site code
 A = H (STATSChipPAC, KOREA)
 A = E (ASE, Taiwan)
Y = single/last digit of year
WW = two-digit work week of year specified by Y
XXX = traceability number
Pin 1 ● Ball A1 identifier
Line E Space reserved for optional additional trace information

4.3 Device ordering information

Figure 4-3 shows the form of ordering numbers.

Device ID
AAA-AAAA -P DDDDDD - CCC - EE - RR -S - BB
code

Symbol Config Package Number Shipping Product Source Feature

Product name
definition code type of pins package revision code code

Example IPQ-6000 -0 - FCBGA 570 - TR - 00 -0 - VV

Feature code (BB) may not be included when identifying older devices.

Figure 4-3 Device identification code

Device identification details for all sample available to date are summarized in Table 4-2.

Table 4-2 Device identification details

Variant (PRR-BB)
P = product configuration code Shipping
Device S value3 Temperature
RR = product revision code package2
BB = feature code (if applicable)1
000 TR 0 Commercial
IPQ6000
000 MT 0 Commercial
1. BB is the feature code that identifies an IC’s specific feature set, which distinguish it from other versions or
variants.
2. TR = tape and reel, MT = matrix tray
3. S is the source configuration code that identifies all the qualified die fabrication-source combinations
available at the time a particular sample type was shipped. S values are defined in Table 4-3.

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Table 4-3 Source configuration code

S value Die F value = H
0 Digital GLOBALFOUNDRIES

Table 4-4 shows the available ordering numbers.

Table 4-4 Ordering numbers

Ordering number
IPQ-6000-0-FCBGA570-MT-00-0
IPQ-6000-0-FCBGA570-TR-00-0

4.4 Device moisture-sensitivity level

Plastic-encapsulated surface mount packages are susceptible to damage induced by absorbed
moisture and high temperature. A package’s moisture-sensitivity level (MSL) indicates its ability
to withstand exposure after it is removed from its shipment bag, while it is on the factory floor
awaiting PCB installation. A low MSL rating is better than a high rating; a low MSL device can be
exposed on the factory floor longer than a high MSL device.

Qualcomm Technologies Inc. follows the latest IPC/JEDEC J-STD-020 standard revision for
moisture-sensitivity qualification. The IPQ6000 is classified as MSL3; the qualification
temperature was 255ºC.

4.5 Thermal characteristics

Table 4-5 Device JEDEC thermal resistance

Parameter Comment Typ Unit
 With thermal vias
JA Junction-to-Ambient 18.39 °C/W
 JESD51-2A, JESD51-7
 No thermal vias
JB Junction-to-Board 9.10 °C/W
 JESD51-7, JESD51-8
 No thermal vias
JC Junction-to-Case 0.21 °C/W
 JESD51-7, JESD51-8

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 5 Carrier, storage, and handling
information

5.1 Carrier

5.1.1 Tape and reel information

Carrier tape system conforms to the EIA-481 standard.

Simplified sketches of the IPQ6000 tape carrier is shown in Figure 5-1 and Figure 5-2, including
the part orientation. Tape and reel details for the IPQ6000 are as follows:
 Reel diameter: 330 mm
 Hub size: 102 mm
 Tape width: 32 mm
 Tape pocket pitch: 24 mm
 Feed: Dual
 Units per reel: 1000

Figure 5-1 Tape orientation on reel

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Figure 5-2 Part orientation in tape

5.1.2 Matrix tray information

Qualcomm Technologies matrix tray carriers conform to JEDEC standards. The device pin 1 is
oriented to the chamfered corner of the matrix tray. Each tray of the IPQ6000 device contains up to
84 devices. See Figure 5-3 for matrix-tray key attributes and dimensions.

Key dimensions
Array 6 × 14 = 84
M 14.45 mm
M1 14.50 mm
M2 22.00 mm
M3 21.40 mm

Figure 5-3 Matrix tray part orientation

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5.2 Storage

5.2.1 Bag storage conditions

IPQ6000 devices delivered in tape and reel carriers must be stored in sealed, moisture barrier, anti-
static bags. Refer to the ASIC Packing Methods and Materials Specification (80-VK055-1) for the
expected shelf life.

5.2.2 Out of bag duration

The out-of-bag duration is the time a device can be on the factory floor before being installed onto
a PCB. It is defined by the device MSL rating, as described in Section 4.4.

5.3 Handling
Tape handling is described in Section 5.1.1. Other (IC-specific) handling guidelines are presented
below.

5.3.1 Baking
It is not necessary to bake the IPQ6000 if the conditions specified in Section 5.2.1 and
Section 5.2.2 have not been exceeded.
It is necessary to bake the IPQ6000 if any condition specified in Section 5.2.1 or Section 5.2.2 has
been exceeded. The baking conditions are specified on the moisture-sensitive caution label
attached to each bag; see ASIC Packing Methods and Materials Specification (80-VK055-1) for
details.

CAUTION: If baking is required, the devices must be transferred into trays that can be baked to at
least 125°C. Devices should not be baked in tape and reel carriers at any temperature.

5.3.2 Electrostatic discharge

Electrostatic discharge (ESD) occurs naturally in laboratory and factory environments. An
established high-voltage potential is always at risk of discharging to a lower potential. If this
discharge path is through a semiconductor device, destructive damage may result.

ESD countermeasures and handling methods must be developed and used to control the factory
environment at each manufacturing site.

Products must be handled according to the ESD Association standard: ANSI/ESD S20.20-1999,
Protection of Electrical and Electronic Parts, Assemblies, and Equipment.

Refer to Section 7.1 for the ESD ratings.

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5.4 Barcode label and packing for shipment

Refer to the ASIC Packing and Materials Specification (80-VK055-1) document for all packing-
related information, including barcode label details.

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 6 PCB mounting guidelines

6.1 RoHS compliance

The IPQ6000 complies with the requirements of the EU RoHS directive. Its SnAgCu solder balls
use SAC305 composition. A Product Material Declaration (PMD), which provides RoHS and
other product environmental governance information, will be published when the data are
available.

6.2 SMT assembly guidelines

For recommendations on SMT process development, see the SMT Assembly Guidelines 
(SM80-P0982-1).

NOTE: Click the following link to download the SMT Assembly Guidelines (SM80-P0982-1)
from the CreatePoint website.

https://createpoint.qti.qualcomm.com/search/contentdocument/stream/dcn/SM80-P0982-1
After successfully logging in, the document is downloaded.

NOTE: Make this document a favorite to be notified of any changes.

6.3 High-temperature warpage

Qualcomm measures high-temperature warpage using a shadow moire system. For detailed data,
refer to High-Temperature Warpage 519 FCBGA (WR80-Y0791-1).

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 7 Part reliability

7.1 Reliability qualifications summary

Table 7-1 IPQ6000 silicon reliability results

Tests, standards, and conditions Sample size Result
ELFR in DPPM
Pass
HTOL: JESD22-A108-A >1k
DPPM < 1000 DPPM
(Total samples from three different wafer lots)
HTOL in FIT () failure in billion device hours
Pass
HTOL: JESD22-A108-A 77x3 lots
FIT < 50
(Total samples from three different wafer lots)
Mean time to failure (MTTF) t = 1/ in million hours
77x3 lots > 20
(Total samples from three different wafer lots)
ESD – human-body model (HBM) rating
ESDA/JEDEC JS-001-2017 3 Pass +/-1kV
(Total samples from one wafer lot)
ESD – charged-device model (CDM) rating
ESDA/JEDEC JS-002-2018 3 Pass +/-250V
(Total samples from one wafer lot)
Latch-up (I-test): JEDEC78E
Trigger current: ±100 mA; temperature: 85°C 3 Pass
(Total samples from one wafer lot)
Latch-up (Vsupply overvoltage): JEDEC78E
Trigger voltage: Each VDD pin, stress at 1.5 × Vddmax per device
3 Pass
specification; temperature: 85°C
(Total samples from one wafer lot)

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Table 7-2 IPQ6000 package reliability results

Tests, standards, and conditions ASE SCK Result

sample size sample size
Moisture resistance test (MRT): J-STD-020/JESD22-A113-F
Reflow at 260 +0/-5°C 154x2 lots 154x2 lots Pass
(Total samples from three different assembly lots)
Temperature cycle: JESD22-A104
Temperature: -55°C to 125°C; number of cycles: 500, 1000
Soak time at minimum/maximum temperature: 8–10 minutes
Cycle rate: 2 cycles per hour (CPH) 77x2 lots 77x2 lots Pass
Preconditioning: JESD22-A113-F
MSL 3, reflow temperature: 260 +0/-5°C
(Total samples from three different assembly lots)
Unbiased highly accelerated stress test: JESD22-A118
130°C/85% RH and 96-hour duration
Preconditioning: JESD22-A113 77x2 lots 77x2 lots Pass
MSL 3, reflow temperature: 260 +0/-5°C
(Total samples from three different assembly lots)
High-temperature storage life: JESD22-A103
Temperature 150°C, 500, 1000 hours 77x2 lots 77x2 lots Pass
(Total samples from three different assembly lots)

7.2 Qualification sample description

 Device name: IPQ6000
 Package type: FCBGA570
 Package body size: 18.1 mm × 18.1 mm × 1.7 mm
 Lead count: 570
 Lead pitch: 0.65 mm

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