APPLICATION NOTE

R
Dynamic Reconfiguration

XAPP093 November 10, 1997 (Version 1.1) 0 14* Application Note by Peter Alfke

Introduction Important Considerations

All Xilinx SRAM-based FPGAs can be in-system config- • Reconfiguration is “all or nothing”. There is no way to
ured and re-configured an unlimited number of times. restrict reconfiguration to a part of the chip.

• Reconfiguration takes a specific time, determined only

by device type, size and clock speed, independent of
the particular configuration pattern. Configuration takes
This application note describes the procedures for recon-
from tens to hundreds of milliseconds. During that time,
figuring the more traditional Xilinx FPGAs of the XC3000,
all user-outputs of the device, or the whole daisy-chain
XC4000, and XC5200 families.
of devices, are 3-stated with weak internal pull-ups,
All configuration information is stored in latches that are except for HDC and LDC, which are active High or Low
loaded serially, conceptually like a shift register. There are respectively.
several different bit-serial or byte-parallel configuration • All user-data stored in registers, flip-flops or latches is
data interfaces, selected by logic levels on three mode erased. There is no way to retain data inside the device
inputs, but – with the exception of the XC5200 Express from one configuration to the next.
mode – they all result in the bit-serial loading of the config-
These limitations are absolute. If they are not acceptable,
uration latches. The byte-parallel interfaces in Master Par-
the user must resort to creative solutions, like piggy-back-
allel and Peripheral modes act just as an 8-bit
ing multiple devices.
parallel-to-serial converter. Between devices in a
daisy-chain, the configuration information is transmitted The designer of reconfigurable applications should be
bit-serially with a common Configuration Clock (CCLK). In familiar with the normal configuration process of each
Master and Peripheral modes, CCLK is generated by the device, as described in the individual product descriptions.
lead FPGA device, in Slave Serial mode, CCLK comes There is also pertinent information about daisy-chain oper-
from an external source. ation, especially about mixed daisy chains, in other applica-
tion notes.
Reconfiguration of an operational device, or a daisy-chain
of devices, goes through the following sequence of events: Interconnecting the INIT pins of all devices in a daisy-chain
is mandatory for reconfiguration, since this is the only way
• Reconfiguration is initiated by pulling a specific device
to guarantee that the master device does wait for the rest of
pin Low.
the daisy-chain to be cleared, before starting the reconfigu-
• First, all outputs are 3-stated, except HDC = High, LDC
and DONE = Low ration. Only the first configuration after power-up makes the
• Then, all internal registers, flip-flops and latches, as master device spend four times as many clock periods as
any slave during the initial clear operation, so that the mas-
well as the configuration storage latches are cleared.
ter cannot possibly get ahead of the slaves. Reconfigura-
During this time, the INIT output is being pulled Low.
tion, however, does not slow down the master this way, so
• Then, the Mode inputs and RESET or PROGRAM
the interconnection of all INIT pins must serve that same
inputs are sampled to determine the selected
configuration mode and whether to start the new purpose.
configuration process, or to wait. In Master Serial mode, it is highly recommended that the
• Then configuration data is accepted and loaded into the active Low level of INIT be used to reset the XC1700-family
14
internal latches and distributed through the daisy-chain. Serial PROM.
• When all configuration information has been entered,
the user outputs are activated, DONE goes High and
the internal reset is released, all in the order specified in
the configuration bitstream. All devices in a daisy-chain
perform each of these operations in synchronism.

XAPP093 November 10, 1997 (Version 1.1) 14-44

 R

Dynamic Reconfiguration

Reconfiguration Time This is the simplest scheme, but it precludes the use of
RESET to clear the flip-flops and latches in the operating
Reconfiguration time is usually more critical than the origi- user-design. RESET must be pulled Low for more than six
nal power-on configuration time, which is often masked by microseconds to overcome its internal low-pass filtering.
the general power-on delays. Configuration starts when RESET has gone High again.
Here are some suggestions to reduce reconfiguration time. 2. Pull DONE Low with an open-drain (“open-collector”)
• A daisy-chain is obviously not conducive to fast output. This assumes that DONE was High, i.e. that the
configuration, it should be broken up into shorter previous configuration was successful. Reconfiguration
blocks, perhaps single devices. Multiple devices can be starts as soon as the internal memory has been cleared.
configured in parallel, but can still use a common DONE can be released anytime.
CCLK, and can also be made to start up together. If the 3. Pull DONE Low with an open-drain (“open-collector”)
devices differ in size or family, they should all be given output and pull RESET Low. Keep RESET Low for at least
the same length count as the largest device in the six microseconds while DONE is Low. DONE can be
group. released anytime after that, or not released at all. See alter-
• Configuration Mode native 1.
Parallel and Peripheral modes are not any faster than
Master Serial mode, since all modes (with the exception XC4000 Series and XC5200 Family
of XC5200 Express mode) internally operate on serial
Pull the PROGRAM input Low for at least 0.3 microsec-
data. The internally generated CCLK frequency is
onds to initiate clearing the configuration memory, then pull
guard-banded to never approach the upper limit of what
the device can tolerate. Therefore, the fastest possible PROGRAM up to start the new configuration process.
configuration mode for XC3000 and XC4000-series While PROGRAM is held Low, a Low level on INIT indi-
devices is Slave Serial, with an external well-controlled cates that the device is continuously clearing the configura-
source for CCLK. Its frequency can be up to 10 MHz for tion memory. When PROGRAM has been pulled up, INIT
all 5-V devices, and there are ways to increase the stays Low during one more clear operation, then goes
average clock rate well beyond that, but they require High.
dynamic clock frequency changes and an intimate
All device families, except the original XC4000, have a con-
understanding of the configuration frame structure. tinuously active pull-up resistor on the PROGRAM pin.
At 10 MHz, configuration time per device ranges from
1.5 ms for the XC3020A to 42 ms for the XC4025E and
192 ms for the XC4085XL.
• Possible Contention Problems:
Certain user outputs become active during the configu-
ration process:
Address outputs during Master Parallel mode, Chip
Select and Ready/Busy during Peripheral modes.
The designer must make sure that these active outputs
do not cause contention with other logic that might use
the same pins as device inputs.

Initiating Reconfiguration in
Different Xilinx Device Families
XC3000 Series
There are three alternatives: 14
1. Pull RESET Low while DONE is permanently grounded
externally.

XAPP093 November 10, 1997 (Version 1.1) 14-45