Operational Amplifier (Op-amp) Equivalent Circuit of an Ideal Operational Amplifier:

Operational amplifiers are linear devices that have all the properties required for nearly ideal DC
amplification and are therefore used extensively in signal conditioning, filtering or to perform
mathematical operations such as add, subtract, integration and differentiation.
An Operational Amplifier, or op-amp for short, is fundamentally a voltage amplifying device designed to
be used with external feedback components such as resistors and capacitors between its output and input
terminals. These feedback components determine the resulting function or “operation” of the amplifier and
by virtue of the different feedback configurations whether resistive, capacitive or both, the amplifier can
perform a variety of different operations, giving rise to its name of “Operational Amplifier”.
An Operational Amplifier is basically a three-terminal device which consists of two high impedance inputs: The equivalent circuit of an ideal op-amp is shown above. The input voltage V DIFF is the difference

 One of the inputs is called the Inverting Input, marked with a negative or “minus” sign, (–). voltage (V1 -V2 ). Z in is the input impedance and Zout is the output impedance.

 The other input is called the Non-inverting Input, marked with a positive or “plus” sign (+). The gain parameter A is called the open loop gain. If an op-amp does not have any feedback from
 A third terminal represents the operational amplifiers output port which can both sink and source the output to either of the inputs, it is said to be operating in open-loop configuration.
either a voltage or a current. An ideal op-amp exhibits infinite open loop gain, infinite input impedance, zero output impedance,
In a linear operational amplifier, the output signal is the amplification factor, known as the amplifiers gain infinite voltage swing, infinite bandwidth, infinite slew rate and zero input offset voltage.
( A ) multiplied by the value of the input signal and depending on the nature of these input and output
signals. Op-Amp Parameter and Characteristics:
Open Loop Gain (Avo):
Open-loop gain of an op-amp is defined as the gain of the op-amp when there is no feedback from the
output to either of its inputs. For an ideal op-amp, the gain will be infinite theoretically, but practical value
range from 20,000 to 200,000.
Input impedance (ZIN):
Input impedance is the ratio of input voltage to input current and is assumed to be infinite to prevent any
current flowing from the source supply into the amplifiers input circuitry ( I IN = 0 ). Real op-amps have
Op-Amp Operation:
input leakage currents from a few pico-amps to a few milli-amps.
Ideally, an op-amp amplifies only the difference in voltage between the two, also called differential
Output impedance (ZOUT):
input voltage. The output voltage of the op-amp Vout is given by the equation: Vout = AOL (V+ – V–)
The output impedance of the ideal operational amplifier is assumed to be zero acting as a perfect internal
Where AOL is the open-loop gain of the amplifier.
voltage source with no internal resistance so that it can supply as much current as necessary to the load.
In a linear operational amplifier, the output signal is the amplification factor, known as the amplifier’s
This internal resistance is effectively in series with the load thereby reducing the output voltage available to
gain (A) multiplied by the value of the input signal.
the load. Real op-amps have output impedances in the 100-20kΩ range.
There are four ways to classify operational amplifiers:
Bandwidth (BW):
 Voltage amplifiers take voltage in and produce a voltage at the output.
An ideal operational amplifier has an infinite frequency response and can amplify any frequency signal
 Current amplifiers receive a current input and produce a current output.
from DC to the highest AC frequencies so it is therefore assumed to have an infinite bandwidth. With real
 Transconductance amplifiers convert a voltage input to a current output.
op-amps, the bandwidth is limited by the Gain-Bandwidth product (GB), which is equal to the frequency
 Transresistance amplifiers convert a current input and produce a voltage output.
where the amplifiers gain becomes unity.
Common-Mode Input Voltage Range: Common-Mode Rejection Ratio:
All op-amps have limitations on the range of voltages over which they will operate. The common-mode The common-mode rejection ratio (CMRR), as discussed in conjunction with the diff-amp, is a measure of
input voltage range is the range of input voltages which, when applied to both inputs, will not cause an op-amp's ability to reject common-mode signals. An infinite value of CMRR means that the output is
clipping or other output distortion. Many op-amps have common-mode input voltage ranges of + or - 10 V zero when the same signal is applied to both inputs (common-mode).
with dc supply voltages of + o r - 15 V. An infinite CMRR is never achieved in practice, but a good op-amp does have a very high value of CMRR.
Offset Voltage (VIO): Common-mode signals are undesired interference voltages such as 50 Hz power-supply ripple and noise
The amplifiers output will be zero when the voltage difference between the inverting and the non-inverting voltages due to pick-up of radiated energy. A high CMRR enables the op-amp to virtually eliminate these
inputs is zero, the same or when both inputs are grounded. Real op-amps have some amount of output interference signals from the output.
offset voltage. The accepted definition of CMRR for an op-amp is the open-loop voltage gain (AOL) divided by the
Input Offset Current: common-mode gain (ACM).
Ideally, the two input bias currents are equal, and thus their difference is zero. In a practical op-amp, CMRR = AOL / ACM
however, the bias currents are not exactly equal. It is commonly expressed in decibels as follows:
The input offset current; Ios is the difference of the input bias currents, expressed as an absolute CMRR = 20 log [AOL / ACM]
value. Slew Rate:
IOS = |I1 – I2 | The maximum rate of change of the output voltage in response to a step input voltage is the slew rate of an
Actual magnitudes of offset current are usually at least an order of magnitude (ten times) less than the bias op-amp. The slew rate is dependent upon the high-frequency response of the amplifier stages within the op-
current. In many applications, the offset current can be neglected. However, high-gain, high-input amp.
impedance amplifiers should have as little Ios as possible because the difference in currents thr ough large Slew rate is measured with an op-amp connected as shown in Figure. This particular op-amp connection is
input resistances develops a substantial offset voltage, as shown in figure. a unity-gain, non-inverting configuration, which will be discussed later. It gives a worst-case (slowest) slew
rate. Recall that the high-frequency components of a voltage step are contained in the rising edge and that
the upper critical frequency of an amplifier limits its response to step input. The lower the upper critical
frequency is, the more slope there is on the output for a step input.

Input Bias Current:

You have seen that the input terminals of a bipolar differential amplifier are the transistor bases and,
therefore, the input currents are the base currents.
The input bias current is the dc current required by the inputs of the amplifier to properly operate the first
stage. By definition, the input bias current is the average of both input currents and is calculated as follows:
IBIAS = (I1 + I2 ) / 2
The concept of input bias current is illustrated in Figure,
A pulse is applied to the input as shown, and the ideal output voltage is measured as indicated in figure (b).
The width of the input pulse must be sufficient to allow the output to "slew" from its lower limit to its
upper limit, as shown. As you can see, a certain time interval, At, is required for the output voltage to go
from its lower limit -Vmax to its upper limit +Vmax, once the input step is applied. The slew rate is
expressed as,
 Slew rate = [ΔVout / Δ t]
Where
ΔVout = +Vmax – (- Vmax)
The unit of slew rate is volts per microseconds (V / µs).
Now the ideal and practical value of operational amplifier,

Features of Differential Amplifier:

 High differential voltage gain
 Low common mode gain
 High CMRR
 Two input terminals
 High input impedance
 Large bandwidth
 Low offset voltages and currents
Derivation of closed loop gain :
Inverting amplifier: As node B is grounded, node A is also at ground potential, from the concept of virtual ground, so V A =0.
In this configuration the input signal is applied to the inverting input terminal of the op-amp and the non- I = Vin – VA / R1
inverting input terminal is connected to the ground. Figure shows the circuit of an open – loop inverting I = Vin / R1 ... (2.21.1)
amplifier. The output voltage is 1800 out of phase with respect to the input and hence, the output voltage V0 Now from the output side, considering the direction of current I we can write,
is given by, I = VA – Vo / Rf

V0 = - AVi I = - Vo / Rf …. (2.21.2)
Entire current I passes through Rf as op-amp input current is zero.
Thus, in an inverting amplifier, the input signal is amplified by the open-loop gain A and in phase shifted by 180 0.
Equating equations (2.21.1) and (2.21.2) we get,
Vin / R1 = Vo / Rf
 Derivation of closed loop gain :
The node B is at potential Vin, hence the potential of point A is same as B which is V in, from the concept of virtual
share.
The Rf / R1 is the gain of the amplifier while negative sign indicates that the polarity of output is opposite to that of VA = VB = Vin … (2.22.1)
input. Hence it is called inverting amplifier. From the output side we can write,
The input and output waveforms are shown in the Fig. 2.21.1 (b). I = Vo – VA / rf
Observations : I = Vo – Vin / rf … (2.22.2)
1. The output is inverted with respect to input, which is indicated by minus sign. At the inverting terminal,
2. The voltage gain is independent of open loop gain of the op-amp, which is assumed to be large. I = VA – 0 / R1 i,e. I = Vin / R1 … (2.22.3)
3. The voltage gain depends on the ratio of the two resistances. Hence selecting R f and R1, the required value of Entire current passes through R1 as input current of op-amp is zero.
gain can be easily obtained. Equating equations (2.22.2) and (2.22.3),
4. If Rf > R1, the gain is greater than 1.
If Rf < R1, the gain is less than 1.
If Rf = R1 the gain is unity.
Thus the output voltage can be greater than, less than or equal to the input voltage, in magnitude.
5. If the ratio of R f and R1 is K which is other than one, the circuit is called scale changer while for R f / R1 = 1 it is
called phase inverter.
6. The closed loop gain is denoted as AVF or AVCL i.e. gain with feedback.
1. Sign Changer
In the ideal inverting amplifier if R f ≠ R1 then the gain is ACL = -1 Thus the magnitude of output is same as that of
the input but its sign is opposite to that of the input.
Vo = -Vin for Rf = R1
This circuit is called sign changer or phase inverter. The positive sign indicates that there is no phase shift between input and output.
2. Scale Changer The input and output waveforms are shown in the Fig. 2.22.1 (b).
In the ideal inverting amplifier if R f ≠ R1 then the gain is ACL = -K where K = Rf/R1. Thus the circuit is used to
multiply input by a constant K called scaling factor. Vo = -K Vin

Non-Inverting amplifier:
An amplifier which amplifies the input without producing any phase shift between input and output is called non-
inverting amplifier. The basic circuit diagram of a non-inverting amplifier using op-amp is shown in the Fig. 2.22.1
(a). The input is applied to the non-inverting input terminal of the op-amp.
Observations
1. The voltage gain is always greater than one.
2. The voltage gain is positive indicating that for a.c. input, the output and input are in phase while for d.c. input,
the output polarity is same as that of input.
3. The voltage gain is independent of open loop gain of op-amp, but depends only on the two resistance values.
Applying KCL at node A and as input op-amp current is zero,
4. The desired voltage gain can be obtained by selecting proper values of Rf and R1
I = I1 + I2 ….. (2.27.4)
From the output side,
I = VA – Vo / Rf = - Vo / Rf …. (2.27.5)
Substituting equations (2.27.5), (2.27.2) and (2.27.3) in equation (2.27.4),

Summer or Adder Circuit:

If the three resistances are equal, R 1 = R2 = Rf
As the input impedance of an op-amp is extremely large, more than one input signal can be applied to the inverting
Vo = - ( V1 + V2 ) …. (2.27.7)
amplifier. Such circuit gives the addition of the applied signals at the output. Hence it is called summer or adder
By properly selecting Rf, R1 and R2, we can have weighted addition of the input signals like aVf + bV2, as
circuit. Depending upon the sign of the output, the summer circuits are classified as inverting summer and non-
indicated by the equation (2.27.6).
inverting summer.
Infact in such a way, n input voltages can be added.
1. Inverting Summer
Key Point Thus the magnitude of the ouput voltage is the sum of the input voltages and hence circuit is called
In this circuit, all the input signals to be added are applied to the inverting input terminal of the op-amp. The circuit
summer or adder circuit.
with two input signals is shown in the Fig. 2.27.1.
2. Non-inverting Summing Amplifier
The circuit discussed above is inverting summing amplifier, which can be noticed from the negative sign in the
equation (2.27.6). But a summer that gives non-inverted sum of the input signals is called non-inverting summing
amplifier. The circuit is shown in the Fig. 2.27.2

As point B is grounded, due to virtual ground concept the node A is also at virtual ground potential.
VA = 0 .... (2.27.1)
Now from the input side,
Let the voltage of node B is VB. NOW the node A is at the same potential as that of B, due to virtual ground.
VA = VB …. (2.27.8)
 If R1 = R2 = R = Rf, we get
Vo = V1 + V2 …. (2.27.16)
Key Point As there is no phase difference between input and output, it is called non-inverting summer amplifier.
3. Average Circuit
If in the inverting summer circuit, the values of resistance are selected as,
R1 = R2 = R
and Rf = R / 2
Then from the equation (2.27.6) we get,

Key Point Thus the magnitude of the output voltage is the average of the two input voltages. So circuit acts like an
average.
Similarly average of n inputs can be calculated by selecting,
R1 = R2 = R3 = ... = Rn = R and Rf = R / n

Integrator
In an integrator circuit, the output voltage is the integration of the input voltage. The integrator circuit can be
obtained without using active devices like op-amp, transistors etc. In such a case an integrator is called passive
integrator. While an integrator using an active devices like op-amp is called active integrator. In this section, we
will discuss the operation of active op-amp integrator circuit.
1. Ideal Active Op-amp Integrator
Consider the op-amp integrator circuit as shown in the Fig. 2.29.1.

The equation (2.27.15) shows that the output is weighted sum of the inputs. The node B is grounded. The node A is also at the ground potential from the concept of virtual ground.
VA = 0 = VB As the input current of op-amp is zero, the node B is still can be treated at ground potential in this circuit.
As input current of op-amp is zero, the entire current I flowing through R 1, also flows through Cf, as shown in the Key Point Hence the above analysis is equally applicable to the integrator circuit with bias compensation. And the
Fig. 2.29.1. output is the perfect integration of the input.

2. Input and Output Waveforms

Let us see the output waveforms, for various input signals. For simplicity of understanding, assume that the time
constant R1Cf = 1 and the initial voltage Vo (0) = 0V
i) Step input signal
Let the input waveform is of step type, with a magnitude of A units as shown in the Fig. 2.29.3

where Vo (0) is the constant of integration, indicating the initial output Voltage.
The equation (2.29.5) shows that the output is - 1/ R1 Cf times the integral of input and R 1 Cf is called time constant
of the integrator. Mathematically the step input can be expressed as,
The negative sign indicates that there is a phase shift of 180° between input and output. The main advantage of Vin (t) = A for t ≥ 0
such an active integrator is the large time constant. By Miller's theorem the effective capacitance between input And = 0 for t ≤ 0
terminal A and the ground becomes C f (1-Av ) where Av is the gain of the op-amp which is very large. Due to such From equation (2.29.5), with R1Cf = 1 and Vo(0) = 0,
large effective capacitance, time constant is very large and thus a perfect integration results due to such circuit. We can write,
Sometimes a resistance Rcomp = R1 is connected to the non-inverting terminal to provide the bias compensation.
This is shown in the Fig. 2.29.2.

Thus output waveform is a straight line with a slope of -A where A is magnitude of the step input. The output
waveform is shown in the Fig. 2.29.4.
 = + A t T/2 < t < T ….. (2.29.9)
The output waveform is shown in the Fig. 2.29.6.

ii) Square wave input signal iii) Sine wave input signal
Let the input waveform is a square wave as shown in the Fig. 2.29.5 Let the input waveform is purely sinusoidal with a frequency of co rad/sec. Mathematically it can be expressed as,
Vin (t) = Vm Sin ω t ... (2.29.10)
where Vm is the amplitude of the sine wave and T be the period of the waveform.
To find the output waveform, use the equation (2.29.5) with R 1Cf = 1 and Vo(0) = 0 V.

Thus it can be seen that the output of an integrator is a cosine waveform for a input. Due to inverting integrator, the
output waveform is as shown in the Fig. 2.29.7.

It can be observed that the square wave is made up of steps i.e. a step of A between time period of 0 to T/2 while a
step of - A units between a time period of T/2 to T and so on.
Mathematically it can be expressed as,
Vin(t)= A, 0 < t < T/2 ….. (2.29.8)
= - A, T/2 < t < T
This is the expression for the input signal for one period.
The output for step input is a straight line with a slope of -A. So for the period 0 to T/2 output will be straight line
with slope - A. From t = T/2 till t = T, the slope of the straight line will become - (-A) i.e. + A.
So the output can be expressed Fig. 2.29.6 Output waveform for square wave input mathematically for one period
as,
Vo(t)= - A t 0 < t < T/2
3. Errors in an Ideal Integrator The resistance Rf reduces the low frequency gain of the op-amp.
The operation amplifier has input offset voltage (Vios) and the input bias current (Ib)- In the absence of input
voltage or at zero frequency (d.c.), op-amp gain is very high. The input offset voltage gets amplified and appears at 5. The Analysis of Practical Integrator
the output as an error voltage. The bias current also results in a capacitor charging current and adds its effect in an As the input current of op-amp is zero, the node B is still at ground potential. Hence the node A is also at the
output error voltage. ground potential from the concept of virtual ground.
The two components, due to high d.c. gain of op-amp cause output to ramp up or down, depending upon the So VA = 0.
polarities of offset voltage and/or bias current. After some time, output of op-amp may achieve its saturation level.
Hence there is a possibility of op-amp saturation due to such an error voltage and it is very difficult to pull op-amp
out of saturation. Thus the output of an ideal integrator in the absence of input signal is likely to be offset towards
the positive or negative saturation levels.
In the presence of the input signal also, the two components namely offset voltage and bias current, contribute an
error voltage at the output. Thus it is not possible to get a true integration of the input signal at the output. Output
waveform may be distorted due to such an error voltage.
Another limitation of an ideal integrator is its bandwidth, which is very small. Hence an ideal integrator can be
used for a very small frequency range of the input only.
Due to all these limitations, an ideal integrator is not used in practice. Some additional components are used along
with the basic integrator circuit to reduce the effect of an error voltage, in practice. Such an integrator is called
Practical Integrator Circuit.

4. Practical Integrator
The limitations of an ideal integrator can be minimized in the practical integrator circuit, which uses a resistance R f
in parallel with the capacitor C f.
The practical integrator circuit is shown in the Fig. 2.29.8.

When Rf is very large then R1/Rf can be neglected and hence circuit behaves like an ideal integrator as,

The resistance Rcomp is also used to overcome the errors due to the bias current.
6. Frequency Response of Practical Integrator frequencies greater than fa and less than fb. Thus in between and practical integrator acts as an integrator. Below fa,
To determine the frequency response, let us obtain the expression for the gain of the practical integrator interms of integration does not take place. The frequency response is shown in the Fig. 2.29.9
the frequency.
From the equation (2.29.18) we can write,

Key Point It can be seen from the frequency response that the bandwidth of practical integrator is f a which is
This is the break frequency or the comer frequency of the practical integrator. Thus in the frequency response, d.c.
much higher than an ideal integrator.
gain remains constant for all frequencies less than fa and from the frequency fa onwards, as frequency increases,
B.W. of Practical Integrator = fa … (2.29.30)
gain reduces at a rate of 20 dB/decade.
For any input bias current or current due to offset voltage, the path of current is through Rf rather than through the
The magnitude of the gain A is,
capacitor Cf. Thus the output voltage is decided by the resistance ratio (R f/ R1) which is typically selected as ≥ 10.
For (Rf/ R1) of 10, the frequency fa becomes (fb/10), this ensures the true integration of the input signal.
For proper integration, the time period T of the input signal has to be larger than or equal to RfC f, so
T ≥ RfCf ... (2.29.31)
where RfCf = 1 / 2π fa
The practical integrator circuit is also called lossy integrator as it behaves as integrator only over the upper
frequency range.
7. Applications of Practical Integrator
The integrator circuits are most commonly used in the following applications :
Thus an infinite d.c. gain of op-amp in case of an ideal integrator, gets limited to R f /R1 in the practical integrator. a) In the analog computers,
Similarly at f = f a we get, b) In solving the differential equations,
c) In analog to digital converters.
d) Various signal wave shaping circuits,
e) In ramp generators.

8. Why Integrators are Preferred in Analog Computers ?

It is important to note that the differentiators are avoided in the analog computer while integrators are widely used
Thus the magnitude of gain drops by 3 dB at the frequency f = fa which is R 60 the break frequency. Now for the
in the analog computers. Let us see the reasons why the integrators are preferred in the analog computers.
integration, the frequency response must be straight line of slope -20 dB/decade, which is possible for the
i) The gain of the integrator decreases with increase in the frequency while that of the differentiator increases with
increase in the frequency. Hence it is very easy to stabilise the integrator with respect to the spurious oscillations.
ii) The input impedance of the integrator is constant and not a function of frequency. While the input impedance of
the differentiator decreases as the frequency increases. So at high frequency the input impedance is very small. If
the input waveform changes rapidly then due to small input impedance, there is every possibility that the amplifier
of the differentiator gets overloaded.
iii) The differentiator has a tendency to amplify the noise and drifts which may result in the oscillations. The
bandwidth of an integrator is small hence the integrator is less sensitive to noise voltages.
iv) The initial voltages present at the output before integration takes place are called as initial conditions. It is very
easy to introduce the initial conditions in the integrator rather than the differentiator.
v) Overall the integrator is more stable than the differentiator and less sensitive to noise and hence chances of
oscillations are much less in the integrator.
Due to all these reasons the integrators are preferred in the analog computers. The equation shows that the output is C 1Rf times the differentiation of the input and product C 1Rf is called time
constant of the differentiator.
Differentiator The negative sign indicates that there is a phase shift of 180° between input and output. The main advantage of
The circuit which produces the differentiation of the input voltage at its output is called differentiator. The such an active differentiator is the small time constant required for differentiation.
differentiator circuit which does not use any active device is called passive differentiator. While the differentiator By Miller's theorem, the effective resistance between input node A and ground becomes R f / 1 + Av ≈ Rf / Av where
using an active device like op-amp is called an active differentiator. Let us discuss first the operation of ideal active Av is the gain of the op-amp which is very large. Hence effective Rf becomes very very small and hence the
op-amp differentiator circuit. condition Rf C1 << T gets satisfied at all the frequencies.
In practice a resistance Rcomp = Rf is connected to the non-inverting terminal to provide the bias compensation.
1. Ideal Active Op-amp Differentiator This is shown in the Fig. 2.30.2.
The active differentiator circuit can be obtained by exchanging the positions of R and C in the basic active
integrator circuit. The op-amp differentiator circuit is shown in the Fig. 2.30.1.

The active differentiator circuit can be obtained by exchanging the positions of R and C in the basic active 2. Input and Output Waveforms
integrator circuit. The op-amp differentiator circuit is shown in the Fig. 2.30.1. Let us study the output waveforms, for various input signals.
The node B is grounded. The node A is also at the ground potential hence V A = 0. For simplicity of understanding, assume that the values of R f and C1 are selected to have time constant (R fC1) as
As input current of op-amp is zero, entire current I flows through the resistance Rf. unity.
From the input side we can write, i) Step input signal
Let the input waveform is of step type with a magnitude of A units. Mathematically it is expressed as,
Vin (t) = A for t ≥ 0 ... (2.30.5)
Now mathematically, the output of the differentiator must be,
Vo (t) = - dVin / dt = - d(A) / dt = 0 …. (2.30.6)
This is because A is constant.
Actually the step input takes a finite time to rise from 0 to A volts.
Due to this finite time, the differentiator output is not zero but appears in the form of a spike at t = 0.
As the circuit acts as an inverting differentiator, the negative going spike or impulse appears at t = 0 and after that
output remains zero.
Both input and output waveforms of the differentiator with a step input, are shown in the Fig. 2.30.3.

iii) Sine wave input

Let the input waveform be purely
sinusoidal with a frequency of ω rad/sec. Mathematically it can be expressed as,
Vin(t) = Vm sin ωt …. (2.30.8)
where Vm is the amplitude of the sine wave and T is the period of the waveform. Let us find out the expression for
the output.

ii) Square wave input signal

Input and output for square wave input
The square wave is made of steps i.e. step of A volts from t = 0 to t = T/2, while a step of -A volts from t = T/2tot =
T and so on. and so on.
Mathematically it can be expressed as, Thus the output of the differentiator is a cosine waveform, for a sine wave input. The input and output waveform is
Vin (t) = A 0 < t < T/2 shown in the Fig. 2.30.5.
= - A T/2 < t < T … (2.30.7)
The differentiator behaves similar to its behaviour to step input.
For positive going impulse, the output shows negative going impulse and for negative going input, the output
shows positive going impulse.
Hence the total output for the square wave input is in the form of train of impulses or spikes.
The input and output waveforms are shown in the Fig. 2.30.4
 5. The Analysis of the Practical Differentiator
As the input current of op-amp is zero, there is no current input at node B. Hence it is at the ground potential. From
the concept of the virtual ground, node A is also at the ground potential and hence V B = VA = 0 V.
For the current I, we can write
I = Vin -VA / Z1 = Vin / Z1 …. (2.30.10)
where Z1 = R1 in series with C1
So in Laplace domain we can write,

3. Disadvantages of an Ideal Differentiator

The gain of the differentiator increases as frequency increases. Thus at some high frequency, the differentiator may
become unstable and break into the oscillations. There is possibility that op-amp may go into the saturation.
Also the input impedance Xc1= (1 /2π f C1) decreases as frequency increases. This makes the circuit very much
sensitive to the noise. Thus when such noise gets amplified due to high gain at high frequency, noise may
completely override the differentiated output.
Hence the differentiator circuit suffers from the limitations on its stability and noise problems, at high frequencies.
These problems can be corrected using some additional parameters in the basic differentiator circuit. Such a
differentiator circuit is called

4. Practical Differentiator
The noise and stability at high frequency can be corrected, in the practical differentiator circuit using the resistance
R1 in series with C1 and the capacitor C f in parallel with resistance Rf.
The circuit is shown in the Fig. 2.30.6. The resistance R comp is used for bias compensation.
 It may be noted that though R fC1 is much larger than RfCf or R1C1 it is less than or equal to the time period T of the
input, for the true differentiation.
RfC1 ≤ T ….. (2.30.22)

6. Frequency Response of Practical Differentiator

To determine the frequency response, let us obtain the expression for the gain of the practical differentiator interms
of the frequency.
From the equation (2.30.20) we can write,

The time constant RfC1 is much greater than RfC1 or RfCf and hence the equation (2.30.20) reduces to,

Thus the output voltage is the RfC 1 times the differentiation of the input.
Now as RfC1 is much larger than R1C1 we can write The practical differentiator circuits are most commonly used in :
fa < fb ... (2.30.29) i) In the wave shaping circuits to detect the high frequency components in the input signal.
Hence as frequency increases, the gain increases till f = f b at a rate of +20 dB/decade. However after f = f b the gain ii) As a rate-of-change detector in the FM demodulators.
decreases at a rate of 20 dB/decade. This 40 dB/decade change at f = f b occurs due to the combination of R 1C1 and The differentiator circuit is avoided in the analog computers.
RfCf.
So for RfC1 << T, the true differentiation results. Sample and Hold Circuit
The frequency response is shown in the Fig. 2.30.7. Refer Fig. 2.30.7. As its name implies, the sample and hold (S/H) circuit samples the value of the input signal in response to a
sampling command and hold it at the output until arrival of the next command. It samples an analog input voltage
in a very short period, generally in the range of 1 to 10 ps, and holds the sampled voltage level for an extended
period, which can range from a few millisecond to several seconds. Fig. 3.24.1 shows input and output response of
the sample and hold circuit.

Key Point It can be observed from the frequency response that the gain reduces as frequency increases greater
than fb- Hence the problem of instability at high frequency gets eliminated.
Also the combination of RiCi and RfCf help to reduce effectively the impact of high frequency noise and offsets.
It is important to remember that if fc is the Unity Gain Bandwidth (UGB) then the values of f a and fb must be
selected in such a way that,
Fa < fb < fc ….. (2.30.30)
where fc is UGB of op-amp in the open loop configuration.

7. Steps to Design Practical Differentiator

By using following steps, a good practical differentiator can be designed :
i) Choose fa as the highest frequency of the input signal.
ii) Choose C1 to be less than 1 µF and calculate the value of R f.
iii) Choose fb as 10 times fa which ensures that fa < fb
iv) Finally calculate the values of R 1 and Cf from the expression R1C1 = RfCf.
v) The Rcomp can be selected as R1 || Rf but practically it is almost equal to R 1.
8. Applications of Practical Differentiator
The sample and hold circuit uses to basic components analog switch and capacitor. The Fig. 3.24.2 shows the basic
sample and hold circuit. Therefore the acquisition time for this circuit is limited by maximum output current and slew rate of the op-amp,
rather than the RC time constant.

The circuit tracks the analog signal until the sample command causes the digital switch isolate the capacitor from to
the signal, and the capacitor holds this analog voltage during A/D conversion.
Sample and Hold Circuits
The S/H circuit of Fig. 3.24.3 (c) performs in a fashion similar to that of Fig. 3.24.3 (b) but it offers the additional
Four basic sample and hold circuits are shown in Fig. 3.24.3. In these circuits a JFET is used as switch. During the
feature of providing voltage gain. The voltage gain of this circuit can be given as A = 1 + (R F/R1). Therefore, the
sampling time the JFET switch is turned on, and the holding capacitor charges up to the level of the analog input
sampled output voltage is equal to the sampled input voltage multiplied by the voltage gain factor 1 + (R F/R1).
voltage. At the end of this short sampling period, the JFET switch is turned off. This isolates the holding capacitor
CH from the input signal. As a result, the voltage across capacitor C H and hence the output voltage will remain
essentially constant at the value of the input voltage at the end of the sampling time. However, there will be a small
drop-off or drop of the capacitor voltage during the hold period due to the various leakage currents. To avoid this,
input and output buffers (voltage follower) circuits are used.
Fig. 3.24.3 (a) shows the open loop architecture of the sample and hold circuit. Remaining figures show the closed
loop architecture of the sample and hold circuit. Open loop type sample and hold circuits are faster than closed loop
types which have delayed output feedback to the input buffer. However, closed loop architectures provide higher dc
accuracy because of this feedback, cancelling the output amplifier offset errors.
The acquisition time of a S/H circuit is the time required for the holding capacitor CH to charge up to a level close
to the input voltage during sampling. The acquisition time for S/H circuit should be as low as possible. In the
circuit of Fig. 3.24.3 (a) there are three principle factors that will control the acquisition time. These factors are :

The S/H circuit of Fig. 3.24.3 (d) offers two advantages. The faster capacitor charging rate provides shorter
acquisition time. This is because the voltage at the inverting input terminal of A 2 is equal to the capacitor voltage
• RC time constant where R is the rds (ON), i.e. on resistance of JFET and C is the holding capacitance C H divided by the open loop gain of A2. In this circuit, the summing input of A2 remains at virtual ground. Due to this,
• Maximum output current, which can be source or sunk by the operational amplifier. the charge removed from the summing junction via Cgd is constant regardless of the input and output signal levels.
• Slew rate of the op-amp. The circuit shown in Fig. 3.24.3 (b) V° offers some advantage over that of Fig. 3.24.3 (a) This removed charge appears as a constant offset at the output. However, as it is constant, it can be nulled by any
in terms of the acquisition time since the rds (ON) of the JFET switch is inside the feedback loop of A i and A 2. standard offset trimming technique.
Advantages of Sample and Hold Circuits b. Inverted R-2R Ladder I Current Mode R-2R Ladder D/A Converter
1. The primary use of the sample and hold circuit to hold the sampled analog input voltage constant during R/2R ladder D/A converter uses only two resistor values. This avoids resistance spread drawback of binary
conversion time of A/D converter. weighted D/A converter. Fig. 3.25.3 shows R/2R ladder DAC. Like binary weighted resistor DAC, it also uses
2. In case of multichannel ADCs, synchronization can be achieved by sampling signals from all channels at the shunt resistors to generate n binary weighted currents; however it uses voltage scaling and identical resistors
same time. instead of resistor scaling and common voltage reference used in binary weighted resistor DAC. Voltage scaling
3. It also reduces the crosstalk in the multiplexer. requires an additional set of voltage dropping series resistances between adjacent nodes, as shown in the Fig.
3.25.3.
Applications of Sample and Hold Circuits
The applications of such sample and hold circuit are :
i) Digital interfacing.
ii) Analog to digital converter circuits.
iii) Pulse modulation systems.
iv) In storage of outputs of a multiplexer between updates in data distribution systems.
v) In reset-stabilised op-amps.
vi) In analog demultiplexers.

D/A Converters
A DAC (Digital to Analog Converter) accepts an n-bit input word b1, b2, b3, ... bn in binary and produce an analog
Here, each bit of the binary word connects the corresponding switch either to ground or to the inverting input
signal proportional to it. Fig. 3.25.1 shows circuit symbol and input-output characteristics of a 4-bit DAC. There
terminal of the op-amp which is at the virtual ground. Since both the positions of switches are at ground potential,
are four digital inputs, indicating 4-bit DAC. Each digital input requires an electrical signal representing either a
the current flowing through resistances is constant and it is independent of switch position. These currents can be
logic 1 or a logic 0. The bn is the least significant bit, LSB, whereas b 1 is the most significant bit, MSB.
given as,

Types of D/A Converter

There are mainly two techniques used for analog to digital conversion
• Binary weighted resistor D/A converter
• R/2R ladder D/A converter
In these techniques, the shunt resistors are used to generate n binary weighted currents. These currents are added
according to switch positions controlled by the digital input and then converted into voltage to give analog voltage
equivalent to the digital input. Therefore, such digital to analog converters are called current driven DACs.
Let us consider 4-bit binary DAC with binary input 1001 and Rf = R, as shown in the Fig. 3.25.4.

Here, output voltage is given as

Reducing above network to the left by Thevenin's theorem we get,

The inverting R/2R ladder DAC works on the principle of summing currents and it is also said to operate in the
current steering mode. An important advantage of the current mode is that all ladder node voltages remain constant
with changing input codes, thus avoiding any shutdown effects by stray capacitances.
c. R-2R Ladder I Voltage Mode R-2R Ladder D/A Converter
In this type, reference voltage is applied to one of the switch positions, and other switch position is connected to
ground, as shown in the Fig. 3.25.5.

Let us consider 3-bit R/2R ladder DAC with binary input 001, as shown in the Fig. 3.25.6.
Therefore, the output voltage is VR/8 which is equivalent to binary input 001. For binary input 100 the network can The coefficient of D is the voltage resolution and can be called simple resolution.
be reduced as follows : Vo = - Resolution ×D (Binary data) ... (3.25.12)
In terms of actual circuit elements, output can be written as,
Vo = - (VR / R × 1 / 2n Rf ….. (3.25.13)
The resolution of R/2R ladder type DAC with current output is,
Resolution = 1 / 2n × VR / R … (3.25.15)
while the resolution for R/2R ladder type DAC with voltage output is,
Resolution = (1 / 2 n × VR / R) × Rf … (3.15.15)

A/D Converters
The A/D conversion is a quantizing process whereby an analog signal is converted into equivalent binary word.
Thus the A/D converter is exactly opposite function that of the D/A converter.
Fig. 3.26.1 shows symbol for A/D converter.

Analog to digital converter are classified into two general groups based on the conversion techniques. One
technique involves comparing a given analog signal with the internally generated reference voltages. This group
includes successive approximation, flash, delta modulated (DM), adaptive delta modulated and flash type
converters. The another technique involves changing an analog signal into time or frequency and comparing these
new parameters against known values. This group includes integrator converters and voltage-to-frequency
Therefore, the output voltage is VR/2, which is equivalent to binary input 100. In general, the voltage is given by converters.
The following types of ADCs using various conversion techniques :
1. Single ramp or single slope
The expression for Vo can be obtained as, 2. Dual slope
Let Iout - Output current 3. Successive approximation
Rf = Feedback resistance of op-amp 4. Flash
Vo = - Iout Rf 5. Delta modulation
Now Iout = Current resolution × D 6. Adaptive delta modulation
Vo = (Current resolution × D) Rf
Vo = (Current resolution × Rf) × D ….. (3.25.11)
Flash ADC The comparators give output "1" or "0" state depending on whether the input signal is above or below the reference
When system designs call for the highest speed available, flash-type A/D converters (ADCs) are likely to be the level at that instant. Those comparators referred above the input signal, remain tumed-off, representing a "0" state.
right choice. They get their names from their ability to do the conversion very rapidly. Flash A/D converters, also The comparators at or below the input signal conversely become a "1" state. The code resulting from this
known as a simultaneous or parallel comparator ADC, because the fast conversion speed is accomplished by comparator is converted to a binary code by the encoder.
providing 2n - 1 comparators and simultaneously comparing the input signal with unique reference levels spaced 1 The number of comparators required for n bit resolution is,
LSB apart. Number of comparators = 2 n – 1 ... (3.26.9)
As seen earlier the quantization error is ± 2 LSB. Thus for an ADC, the maximum frequency for a sine wave to be
digitised within an accuracy of ± 2 LSB is,
fmax ≅ 1/ 2π(TC)2n ... (3.26.10)
where fmax = Maximum input frequency
TC = Conversion time and n = Number of bits

Fig. 3.26.8 shows 3-bit flash A/D converter. For this ADC, seven (2 3 -1) comparators are required. As shown in the
Fig. 3.26.8, one input of each comparator is connected to the input signal and other input to the reference voltage
level generated by the reference voltage divider. The reference voltage (V REF) is equal to the full scale input signal
voltage. The manner in which the flash A/D converter performs a quantization is relatively simple.