Ece 211 Lect 14
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akshat28 mittalEce 211 Lect 14
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akshat28 mittalECE211: Electronic Circuits and Network
Analysis
Lecture 14
Dr. Ananda Y R
Assistant Professor
Department of Electronics and Communication Engineering
IIIT Bangalore
25th September 2024
Lecture 14 Dr. Ananda Y R Assistant Professor ECE211: Electronic Circuits and Network Analysis
Non-idealities in an Op-Amp
Input offset voltage: A non-zero DC voltage present between the two input
differential terminals which causes a DC shift in the output if the gain is
sufficiently high. Occurs due to mismatch between the transistor bias voltages
inside the op-amp.
Input bias current: The non-zero current required to drive the base terminal of
the input transistors of the op-amp. Can cause a DC shift in the output,
depending on the circuit components.
Finite gain: An ideal op-amp has infinite gain. However, the 3-4 stages inside
the 741 op-amp are able to provide a gain of about 2 × 105 , which becomes
significant as the designed amplifier gain using the 741 is increased.
Finite bandwidth: Due to internal parasitic capacitances, the output stage of
the op-amp behaves like a low-pass R-C circuit, and hence the gain drops as the
frequency is increased.
Other parameters such as non-infinite input impedance, non-zero output
impedance, common-mode rejection etc. are also important, though we will not
be measuring these in the lab.
Lecture 14 Dr. Ananda Y R Assistant Professor ECE211: Electronic Circuits and Network Analysis
Representation of a Non-ideal Op-Amp
Lecture 14 Dr. Ananda Y R Assistant Professor ECE211: Electronic Circuits and Network Analysis
Effects on a Circuit
Lecture 14 Dr. Ananda Y R Assistant Professor ECE211: Electronic Circuits and Network Analysis
Minimizing the Effects of Bias Currents
Lecture 14 Dr. Ananda Y R Assistant Professor ECE211: Electronic Circuits and Network Analysis
Measuring the Offset Voltage and Bias Currents
Lecture 14 Dr. Ananda Y R Assistant Professor ECE211: Electronic Circuits and Network Analysis
Measuring the Offset Voltage and Bias Currents
Lecture 14 Dr. Ananda Y R Assistant Professor ECE211: Electronic Circuits and Network Analysis
Measuring the Offset Voltage and Bias Currents
The error in this configuration arises entirely from the input
bias current source on the inverting input which flows into the
feedback network of R1 and RF .
If we perform a nodal analysis, we can see that the output
voltage caused by IB is equal to IB multiplied by RF .
We can then calculate the output caused by IB and the
output from the input signal. Using superposition, we can add
the output signal from the bias current (equal to 20mV), and
the output signal from the input source (100mV), since they
are independent. In this example, the total output voltage
equals 120mV and the error introduced by the input bias
current is 20%.
Lecture 14 Dr. Ananda Y R Assistant Professor ECE211: Electronic Circuits and Network Analysis