ARM Instruction Set
Done by
Priyanga KR
Assistant Professor
• Instruction sets can be categorized into
– Data Processing Instructions
– Values in registers
– Data Transfer Instructions
– Moves values between registers and memory
– Control Flow Instructions
– Changes the value of the Program counter
a) Data Processing Instructions
• All operands are 32 bits in size
• All operand and result registers are
independently specified as part of the
instruction.
• One exception: long multiply
Arithmetic Instructions
• ADD r0,r1,r2 r0=r1+r2
• ADC r0,r1,r2 r0=r1+r2+C (carry bit)
• SUB r0,r1,r2 r0=r1-r2
• SBC r0,r1,r2 r0=r1+r2-C-1
• RSB r0,r1,r2 r0=r2-r1
• RSC r0,r1,r2 r0=r2-r1+c-1
Bit wise Logical Instructions
• AND r0,r1,r2 r0=r1 and r2
• ORR r0,r1,r2 r0=r1 or r2
• EOR r0,r1,r2 r0=r1 xor r2
• BIC r0,r1,r2 r0=r1 and not r2
BIC = Bit clear
Register-register move instructions
• MOV r0,r2 r0= r2
• MVN r0,r2 r0= not r2
MVN Move Negated
Comparison Instructions
• CMP r1,r2 set cc on (r1-r2)
• CMN r1,r2 set cc on (r1+r2)
• TST r1,r2 set cc on (r1 and r2)
• TEQ r1,r2 set cc on (r1 xor r2)
Based on flags N,Z,C,V
Do not produce any result in r0.
Specifying Immediate Operands
• ADD r1,r2,#2 r1=r2+2
• SUB r3,r3,#1 r3=r3-1
• AND r6,r4,#&0f r6=r4[3:0]
# = Immediate Value
& = hexadecimal notation
Shifted Register Operands
• ADD r1,r2,r3,LSL #3 r1=r2 + (r3 << 3)
• ADD r1,r2,r3,LSL r5 r1=r2 + (r3 << r5)
– LSL = Logical Shift Left
– LSR = Logical Shift Right
– ROR = rotate right
– RRX = rotate right extended by 1 bit
– ASL = arithmetic shift left
– ASR = arithmetic shift right
Multiplication Instruction
• MUL r1,r2,r3 r1 = r2*r3 [31:0]
– LSB values
– Immediate operands are not supported
Multiply Accumulate Instruction
• MLA r1,r2,r3,r4 r1 = (r2*r3+r4) [31:0]
used in DSP applications
b) Date Transfer Instructions
• Single register
• Loads and stores
• Flexible, Byte, half word and word transfer
• Multiple Register
• Loads and stores
• Less Flexible, multiple words, higher transfer rate
• Memory Mapped I/O
• Use register indirect addressing
• ADRL r1,Table r1=memory address of table
• Single register Load and Store
• LDR r0,[r1] r0 = mem[r1]
• STR r0,[r1] mem[r1] = r0
• Register Indirect with offset
»LDR r0, [r1,#4] r0 = mem[r1+4]
»STR r0, [r1,#12] mem[r1+12] = r0
• Auto Indexing in addition
• LDR r0, [r1,#4]! r0= mem[r1+4] r1 = r1+4
• STR r0, [r1,#12]! mem[r1+12] = r0 r1 = r1+12
• Post Indexing
»LDR r0, [r1] ,#4 r0= mem[r1] r1 = r1+4
»STR r0, [r1], #12 mem[r1] = r0 r1 = r1+12
Byte or Half word
• LDRB r0,[r1] r0 = mem8[r1]
• STRB r0,[r1] mem8[r1] = r0
• LDRSH r0, [r1] r0 = mem16[r1]
• STRSH r0,[r1] mem16[r1] = r0
Multiple register load and store
• LDMIA r1, {r3,r5,r6} r3 = mem[r1]
r5 = mem [r1 + 4]
r6 = mem [r1 + 8]
• LDMIB r1 + 4, r1 + 8, r1 + 12
Block Copy Addressing
Increment, Decrement, After, Before
• LDMIA, STMIA
– Increment After
• LDMIB,STMIB
– Increment Before
• LDMDA,STMDA
– Decrement After
• LDMDB,STMDB
– Decrement Before
Memory Mapped I/O
C) Control flow instructions
• Changes the order of execution
• Types
– Unconditional Branch
– Conditional Branch
– Branch and Link
– Conditional execution
• Unconditional :
B Target
…….
…….
Target ……..
• Conditional:
MOV r2,#0
LOOP ….
….
ADD r2,r2,#1
CMP r2,#20
BNE LOOP
Branch Conditions
• B, BAL Unconditional
• BEQ,BNE
• BPL, BMI
• BCC,BCS
• BVC,BVS
• BGT,BGE
• BLT,BLE
Branch and Link
• Used for Calling subroutines in ARM
• Return address is saved in register 14
• To return from the subroutine, we have to
jump back to address stored in r14.
Conditional Execution
• Unique feature
• All instructions can be made conditional
• Helps in removing many short branch
instructions
Instruction Postfix
Thank You
