Verilog HDL Design

• Timing Controls
• Delay Based Timing Controls
• Event Based Timing Controls
Verilog® HDL • Level Sensitive Control
• Conditional Statements - if...else/case
• Loop Statements
• Break Statement

Verilog HDL IIT Guwahati 1

 Timing Controls
▪ Various behavioral timing control constructs prove to be an vital concept in
Verilog. if there are no timing control statements, the simulation time does not
advance.

▪ Timing controls provide a way to specify the simulation time at which

procedural statements will execute.

▪ There are three methods of timing control:

- delay-based timing control,
- event-based timing control,
- level-sensitive timing control.

Verilog HDL IIT Guwahati 2

 Delay Based Timing Controls

▪ Specifies the time duration between when the statement

is encountered and when it is executed.

▪ Delays are specified by symbol ‘#’.

▪ Syntax:

<delay> :: = # <number>
|| = # <identifier>
|| = # (<mintypemax_expression>)

Verilog HDL IIT Guwahati 3

 Regular Delay Controls
▪ Regular delay control is used when a non-zero delay is
specified to the left of a procedural assignment.
//define parameters
parameter latency = 20;
parameter delta = 2;
reg x, y, z, p, q; //define register variables
initial
begin
x = 0; // no delay control
#10 y = 1; // delay control with a number. Delay execution of
// y = 1 by 10 units
#latency z = 0; // Delay control with identifier. Delay of 20 units
#(latency + delta) p = 1; // Delay control with expression
#y x = x + 1; // Delay control with identifier. Take value of y.
#(4:5:6) q = 0; // Minimum, typical and maximum delay values.
//Discussed in gate-level modeling chapter.
end

Verilog HDL IIT Guwahati 4

 Intra – Assignment Delay Controls
▪ Instead of specifying delay control to the left of the assignment, it is
possible to assign a delay to the right of the assignment operator.

▪ Such delay specification alters the flow of activity in a different

manner.

//define register variables

reg x, y, z;
//intra assignment delays
initial
begin
x = 0; z = 0;
y = #5 x + z; //Take value of x and z at the time=0, evaluate
//x + z and then wait 5-time units to assign value
//to y.
end

Verilog HDL IIT Guwahati 5

 Zero Delay Controls
▪ Procedural statements in different always-initial blocks may be
evaluated at the same simulation time.
▪ The order of execution of these statements in different always-initial
blocks is nondeterministic.

//define register variables

reg x, y, z;
//intra assignment delays
initial
fork
#0 x = 0;
#1 x = 0;
join

Verilog HDL IIT Guwahati 6

 Event – Based Timing Controls
▪ An event is the change in the value on a register or a net.

▪ Events can be utilized to trigger execution of a statement or a

block of statements.

▪ There are four types of event-based 139 timing control:

Regular event control,

Named event control,
Event OR control,
Level sensitive timing control.

Verilog HDL IIT Guwahati 7

 Regular Event Control
▪ The @ symbol is used to specify an event control.
▪ Statements can be executed on changes in signal value or at a
positive or negative transition of the signal value.

@(clock) q = d; //q = d is executed whenever signal clock changes value

@(posedge clock) q = d; //q = d is executed whenever signal clock does
//a positive transition ( 0 to 1,x or z,
// x to 1, z to 1 )
@(negedge clock) q = d; //q = d is executed whenever signal clock does
//a negative transition ( 1 to 0,x or z,
//x to 0, z to 0)
q = @(posedge clock) d; //d is evaluated immediately and assigned
//to q at the positive edge of clock

Verilog HDL IIT Guwahati 8

 Named Event Control
▪ Verilog provides the capability to declare an event and then trigger
and recognize the occurrence of that event.
▪ The event does not hold any data.
▪ A named event is declared by the keyword event.
▪ An event is triggered by the symbol ->.
▪ The triggering of the event is recognized by the symbol @.
//This is an example of a data buffer storing data after the
//last packet of data has arrived.
event received_data; //Define an event called received_data
always @(posedge clock) //check at each positive clock edge
begin
if(last_data_packet) //If this is the last data packet
->received_data; //trigger the event received_data
end
always @(received_data) //Await triggering of event received_data
data_buf = {data_pkt[0], data_pkt[1], data_pkt[2], data_pkt[3]};

Verilog HDL IIT Guwahati 9

 Event Or Control
▪ Sometimes a transition on any one of multiple signals or events can
trigger the execution of a statement or a block of statements.
▪ This is expressed as an OR of events or signals.
▪ The keyword or is used to specify multiple triggers

//A level-sensitive latch with asynchronous reset

always @( reset or clock or d)
//Wait for reset or clock or d to change
begin
if (reset) //if reset signal is high, set q to 0.
q = 1'b0;
else if(clock) //if clock is high, latch input
q = d;
end

Verilog HDL IIT Guwahati 10

 Level Sensitive Control
▪ The symbol @ provided edge-sensitive control.
▪ Verilog also allows level sensitive timing control, that is, the ability to
wait for a certain condition to be true before a statement or a block of
statements is executed.
▪ The keyword wait is used for level sensitive constructs.

always
wait (count_enable)
#20 count = count + 1;

Count will be incremented when count_enable is high.

Verilog HDL IIT Guwahati 11

 Conditional Statement - if
▪ Conditional statements are used for making decisions based upon certain conditions.
▪ These conditions are used to decide whether or not a statement should be executed.
▪ Keywords if and else are used for conditional statements.
There are three types of conditional statements.

//Type 1 conditional statement. No else statement.

//Statement executes or does not execute.

If (<expression>) true_statement;

Verilog HDL IIT Guwahati 12

 Conditional Statement - if
▪ Type 2 conditional statement. One else statement.
▪ Either true_statement or false_statement is evaluated

If (<expression>) true_statement;
else false_statement;

▪ Type 3 conditional statement. Nested if-else-if.

▪ Choice of multiple statements. Only one is executed.

if (<expression1>) true_statement1 ;
else if (<expression2>) true_statement2 ;
else if (<expression3>) true_statement3 ;
else default_statement ;

Verilog HDL IIT Guwahati 13

 Conditional Statement – if (Example)
//Type 1 statements
if(!lock) buffer = data; //Type 3 statements
if(enable) out = in; //Execute statements based on ALU //control
signal.

//Type 2 statements if (alu_control == 0)

if (number_queued < MAX_Q_DEPTH) y = x + z;
begin else if(alu_control == 1)
data_queue = data; y = x - z;
number_queued = number_queued + 1; else if(alu_control == 2)
end y = x * z;
else else
$display("Queue Full. Try again"); $display("Invalid ALU control signal");

Verilog HDL IIT Guwahati 14

 Conditional Statement – if (Example)

module Flip_flop (q, data_in, clk, rst );

output q;
reg q;
input data_in, clk, rst;
always @ ( posedge clk )
begin
if ( rst == 1)
q = 0;
else
q = data_in;
end
endmodule

Verilog HDL IIT Guwahati 15

 Conditional Statement – Case
▪ Case statement does an infinity comparision (including x & z).
▪ The expression is compared to the alternatives in the order they
are written.
▪ If none of the alternatives matches, the default_statement is
executed.

//Execute statements based on the ALU control signal

reg [1:0] alu_control;
case (expression) ...
alternative1: statement1; ...
alternative2: statement2; case (alu_control)
alternative3: statement3; 2'd0 : y = x + z;
... 2'd1 : y = x - z;
... 2'd2 : y = x * z;
default: default_statement; default : $display("Invalid ALU control signal");
endcase endcase

Verilog HDL IIT Guwahati 16

 Conditional Statement – Case

▪ Modeling a 4x1 MUX

module mux4x1 (out, s, a, b, c, d);
output reg out;
input a, b, c, d;
input [1:0] s;
always @(a or b or c or d or s)
begin
case (s)
2'b00 : out = a;
2'b01 : out = b;
2'b10 : out = c;
default : out = d;
endcase
end
endmodule

Verilog HDL IIT Guwahati 17

 Conditional Statement – Case
▪ BCD to 7 segment code converter

Verilog HDL IIT Guwahati 18

 Conditional Statement – Case
▪ Designing arithmetic blocks

Verilog HDL IIT Guwahati 19

 Conditional Statement – Case

case :
Bit-by-bit comparison
All bits must match exactly
casex :
Bit-by-bit comparison
z’s, x’s are treated as don’t cares
Useful for sparse truth tables
casez :
Bit-by-bit comparison
All z’s are treated as don’t cares
Useful for tri-state signals

Verilog HDL IIT Guwahati 20

 Conditional Statement – Case
module case_compare; always @ (sel) begin
reg sel; case (sel)
initial begin 1’b0 : $display(“Normal : Logic 0 on sel”);
#10 $display(“\n Driving 0”); 1'b1 : $display("Normal : Logic 1 on sel");
sel = 0; 1’bx : $display(“Normal : Logic x on sel”);
#10 $display(“\n Driving 1”); 1’bz : $display(“Normal : Logix z on sel”);
sel = 1; endcase
#10 $display(“\n Driving x”); end
end always @ (sel) begin
always @ (sel) begin casez (sel)
casex (sel) 1’b0 : $display(“CASEZ : Logic 0 on sel”);
1’b0 : $display(“CASEX : Logic 0 on sel”); 1'b1 : $display(“CASEZ : Logic 1 on sel");
1'b1 : $display(“CASEX : Logic 1 on sel"); 1’bx : $display(“CASEZ : Logic x on sel”);
1’bx : $display(“CASEX : Logic x on sel”); 1’bz : $display(“CASEZ : Logix z on sel”);
1’bz : $display(“CASEX : Logix z on sel”); endcase
sel = 1’bx; endmodule
#10 $display(“\n Driving z”);
sel = 1’bz;
#10 $finish;
endcase
end

Verilog HDL IIT Guwahati 21