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Department of Electronics & Communication Engineering: Tutorial-2 (UNIT - I)

This document is a tutorial sheet for a Digital Design course at Kakatiya Institute of Technology & Science, covering topics such as RTL, DCTL, I2L, and DTL logic gates. It includes several tutorial problems related to circuit analysis and behavior, with specific parameters and figures referenced for each problem. The tutorial is scheduled for January 4, 2025, and is led by Dr. B. Rama Devi.

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15 views3 pages

Department of Electronics & Communication Engineering: Tutorial-2 (UNIT - I)

This document is a tutorial sheet for a Digital Design course at Kakatiya Institute of Technology & Science, covering topics such as RTL, DCTL, I2L, and DTL logic gates. It includes several tutorial problems related to circuit analysis and behavior, with specific parameters and figures referenced for each problem. The tutorial is scheduled for January 4, 2025, and is led by Dr. B. Rama Devi.

Uploaded by

vaishnavikoduri03
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

KAKATIYA INSTITUTE OF TECHNOLOGY & SCIENCE, WARANGAL


(An Autonomous Institute under Kakatiya University, Warangal)
Tutorial-2 (UNIT - I)

Course code – Name U18EC407 – Digital Design Branch –Section ECE-I


Tutorial Sheet posted in Tutorial class
19.12.2024 scheduled on 4.1.2025
Course Web on
Topics covered RTL, DCTL, I2L, DTL family of logic gates.
Faculty Name Dr. B. Rama Devi

Problem
Tutorial Tutorial Problems CO CDLL
No
1. Identify the output low and high voltages for the level shifted diode CO1 [Ap]
resistor AND gate shown in the figure 1. Use VCC = 4V, -VEE = -4V,
VD(ON)= 0.7V, RH = 1 kΩ and RL = 2kΩ.

T-2

Fig. 1
2. Determine the current I through the branch in figure 2. Also, find the CO1 [An]
voltage at the base of the transistor Q. Assume the BJT base current is
negligible.

Fig. 2
3. Each gate in the circuit has TPLH=4ns and TPHL =4ns. If a positive going CO1 [An]
pulse is applied to the input. Inspect the time taken for the output pulse
to appear?

Fig. 3
A) 16ns
B) 8ns
C) 4ns
D)2ns
4. Evaluate the behavior of the circuit shown in the Fig. 4 CO1 [Ap]
A) AND gate
B) NAND gate
C) OR gate
D) NOR gate

Fig. 4
5. Inspect the behavior of the following circuit Fig. 5. [An]

Fig. 5
A) NAND gate with positive level logic system
B) NOR gate with negative level logic system
C) NOR gate with positive level logic system
D) All the above
6. Identify the maximum fan-in for the basic RTL NAND gate of figure 5, CO1 [Ap]
if all stack BJTs have VCE(SAT) =0.17 V and all load gates have
VBE(FA)=0.7 V.

Fig. 6
7. Identify the maximum fan-out for a basic RTL gate with VCC = 5 V, CO1 [Ap]
RB=10kΩ, and RC = 1kΩ. let βF= 25, VBE(SAT)=0.8V, VCE(SAT) =0.2 V

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