ECE 3103

Digital Electronics
Combinational Logic Circuits

Course Teacher
Dr Rafia Nishat Toma
Associate Professor
ECE Discipline,
Khulna University
Syllabus (Section A)
• Information & Digital Systems
✓ Introduction to digital systems, number systems, weighted and non-weighted
codes, code conversion, binary addition and subtraction, 2‟s complement method.
• Boolean Algebra
✓ Digital logic, Boolean algebra, Boolean function, canonical forms, Karnaugh
maps, minimization of Boolean functions, logic gates and their truth tables, design
methodologies,
• Combinational Logic Circuits
✓ Combinational logic circuit design, arithmetic and data handling logic
circuits, decoder, encoder, multiplexer, demultiplexer.
• Sequential Logic Circuits
✓ SR, JK, T, and D flip-flops, master-slave JK flip-flop, timing diagrams of
different flip-flops, edge-triggered and level triggered timing diagrams, counters, registers,
memory, finite state machine, asynchronous & synchronous sequential systems, reliable
design and fault diagnosis.
2
 Outline
❑ Digital Arithmetic: Operations and Circuits
• Full Adder & Half Adder
• Full Subtractor & Half Subtractor
• Parallel Binary Adder

❑ MSI Logic Circuits

• Decoders
• Encoders
• Multiplexers
• Demultiplexers

3
 Digital Arithmetic: Operations and Circuits
❑ Half Adder:
• A half adder is a device capable of performing addition of two bits. It has two
binary inputs, A and B, and two outputs, sum (S) and carry (C0). (Note that
there is no carry input (Cin) into the half adder). Figure 6 represents the
truth table for half adder.

Figure 6. Truth table of half adder.

• The k-maps for S and C0 are shown in Figure 7. Figure 7(a) shows the k-
map for S and Figure 7(b) shows the k-map for C0.

S = AB + AB = A  B [Figure 7(a)]
C0 = AB [Figure 7(b)]

• The complete circuit for a half adder is shown in Figure 7(c). 4

 Digital Arithmetic: Operations and Circuits
❑ Half Adder:

Figure 7. Half adder. (a) K-map of S; (b) k-map of C0; (c) circuit diagram.

5
 Digital Arithmetic: Operations and Circuits
❑ Full Adder:
• First of all, we must construct a truth table showing the various input and
output values for all possible cases. Figure 3 shows the truth table having
three inputs A, B, and Cin and two outputs, S and Cout.

Figure 3. (a) Truth table and (b) logic symbol of a full adder.
• There are eight possible cases for the three inputs, and for each case the
6
designed output values are listed.
 Digital Arithmetic: Operations and Circuits
❑ Full Adder:
✓ K-map Simplification:-
• Figure 4(a) and Figure 4(b) represent the k-map for S and Cout.

Figure 4. K-map for (a) S and (b) Cout of a full adder.

 S = ABCin + ABCin +ABCin + ABCin = A(BCin + BCin ) + A(BCin + BCin )
= A(B  Cin ) + A(B  Cin ) = A [B  Cin ]
and Cout = AB + ACin + BCin
• The equations of S and Cout can be implemented as shown in Figure 5
(complete circuitry for a full adder).
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 Digital Arithmetic: Operations and Circuits
❑ Full Adder:

Figure 5. Complete circuit diagram of a full adder.

8
 Digital Arithmetic: Operations and Circuits

❑ Full Adder using Two Half Adders:

• A full adder can be constructed using two half adders. The basic block
diagram for a full adder using two half adders is shown in Figure 8(a). The
truth table for a full adder using two half adders is shown in Figure 8(b).
The complete circuit for a full adder using two half adders is shown in
Figure 8(c).
• From Figure 8(c) we find that, the final sum is found in Sf and output carry
is found in C0.

Figure 8. Full adder using two half adders

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 Digital Arithmetic: Operations and Circuits
❑ Full Adder using Two Half Adders:

(a)

(b)
10
Figure 8. Full adder using two half adders. (a) Basic block diagram; (b) truth table.
 Digital Arithmetic: Operations and Circuits
❑ Full Adder using Two Half Adders:
Here, S f = ( A  B)  Cin S f = S1  Cin = ( A  B)  Cin

and C0 = AB + ( A  B).Cin C0 = C1 + C2 = AB + S1.Cin = AB + ( A  B).Cin

• From the truth table of Figure 8(b) we find that, the circuit of Figure 8(c)
operates as a full adder.

(c)
Figure 8(c). Circuit diagram of a full adder using two half adders. 11
 Digital Arithmetic: Operations and Circuits
❑ Parallel Binary Adder:
• Computers and calculators perform the addition operation on two binary
numbers at a time, where each binary number can have several binary digits.
• Figure 1 illustrates the addition of two five-bit numbers.

Figure 1. Typical binary addition process.

• The augend is stored in the accumulator register, that is, the accumulator
contains five flip-flops, storing the values 10101 in successive flip-flops.
Similarly, the addend, the number that is to be added to the augend, is stored
in the B register (in this case, 00111). 12
 Digital Arithmetic: Operations and Circuits
❑ Parallel Binary Adder:
• The addition process starts by adding the least significant bits of the augend
and addend. Thus, 1 + 1 = 10, which means that the sum for that position is 0,
with a carry of 1.
• This carry must be added to the next position along with the augend and
addend bits in that position. Thus, in the second position 1 + 0 + 1 = 10,
which is again a sum of 0 and a carry of 1. This carry is added to the next
position together with the augend and addend bits in that position, and so on,
for the remaining positions, as shown in Figure 1.
• At each step in this addition process we are performing the addition of three
bits: the augend bit, the addend bit, and a carry bit from the previous
position. The result of the addition of these three bits produces two bits: a sum
bit and a carry bit that is to be added to the next position. The identical block
diagram is shown in Figure 2.
• In this diagram, the variables A4, A3, A2, A1, and A0 represent the bits of the
augend that are stored in the accumulator (which is also called the A register).
• The variables B4, B3, B2, B1, and B0 represent the bits of the addend stored in
the B register. The variables C4, C3, C2, C1, and C0 represent the carry bits
13
into the corresponding positions.
 Digital Arithmetic: Operations and Circuits
❑ Parallel Binary Adder:

Figure 2. Block diagram of five-bit parallel adder circuit using full adders.
• The variables S4, S3, S2, S1, and S0 are the sum output bits for each position.
Corresponding bits of the augend and addend are fed to a logic circuit fed to a
logic circuit called a full adder, along with a carry bit from the previous
position.
• For example, bits A1 and B1 are fed into full adder 1 along with C1, which is
the carry bit produced by the addition of the A0 and B0. 14
 Digital Arithmetic: Operations and Circuits
❑ Parallel Binary Adder:
• Since A0 and B0 are the LSBs of the augend and addend, it appears that C0
would always have to be 0, since there can be no carry into that position.
• The arrangement in Figure 2 is called a parallel adder because all of the bits
of the augend and addend are present and are fed into the adder circuits
simultaneously.

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 Digital Arithmetic: Operations and Circuits
❑ Half Subtractor:
• A half subtractor is a combinational circuit that subtracts two bits and
produces their difference. It also has an output to specify if a 1 has been
borrowed. The truth table for a half subtractor is shown in Figure 9.

Figure 9. Truth table of a half subtractor.

• Designate the minuend bit by A the subtrahend bit by B. To perform A – B,
we have to check the relative magnitudes of A and B. If A  B, we have three
possibilities: 0 – 0 = 0, 1 – 0 = 1, and 1 – 1 = 0. The result is called the
difference bit. If A < B, we have 0 – 1, and it is necessary to borrow a 1 from
the next higher stage. The 1 borrowed from the next higher stage adds 2 to the
minuend bit, just as in the decimal system a borrow adds 10 to a minuend
digit. With the minuend equal to 2, the difference becomes 2 – 1 = 1. The k-
map for borrow (b) is shown in Figure 10(a) and the k-map for difference
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(d) is shown in Figure 10(b).
 Digital Arithmetic: Operations and Circuits
❑ Half Subtractor:

Figure 10. Half subtractor. (a) K-map fot b; (b) k-map for d; (c) circuit diagram.
• Here,
b = AB [Figure 10(a)]
and d = AB + AB = A  B [Figure 10(b)]
• The complete circuit diagram of half subtractor is shown in Figure 10(c).

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 Digital Arithmetic: Operations and Circuits
❑ Full Subtractor:
• A full-subtractor is a combinational logic circuit that performs a subtraction
between two bits, taking into account that a 1 may have been borrowed by a
lower significant stage. This circuit has three inputs and two outputs.
• The three inputs A (minuend), B (subtrahend), Bin (borrow in) and two
outputs, D (difference) and Bout (borrow out), respectively. The truth table for
full subtractor is shown in Figure 11.

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Figure 11. Truth table of full subtractor.
 Digital Arithmetic: Operations and Circuits
❑ Full Subtractor:
• The k-map for Bout is shown in Figure 12(a) and the k-map for difference is
shown in Figure 12(b).

(a) (b)

(c)
Figure 12. Full subtractor. (a) K-map for Bout; (b) k-map for difference; (c) circuit diagram.
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 Digital Arithmetic: Operations and Circuits
❑ Full Subtractor:
• Here,
Bout = AB + BBin + ABin = A(B + Bin ) + BBin
D = ABBin + ABBin + ABBin + ABBin
= A(BBin + BBin ) + A(BBin + BBin )
= A(B  Bin ) + A(B  Bin )
= A  (B  Bin )
• The complete circuit diagram of a full subtractor is shown in Figure 12(c).

Figure 12. circuit diagram of Full subtractor. . 20

 MSI Logic Circuits
❑ Decoders:
• A decoder is a logic circuit that accepts a set of inputs that represents a binary
number and activates only the output that corresponds to that input number.
• In other words, a decoder circuit looks at its inputs, determines which binary
number is present there, and activates the one output that corresponds to that
number; all other outputs remain inactive.
• The diagram for a general decoder is shown in Figure 13 with N inputs and
M outputs. Since each of the N inputs can be 0 or 1, there are 2N possible
input combinations or codes. For each of these input combinations only one of
the M outputs will be active (HIGH); all the other outputs are LOW.

Figure 13. General decoder diagram. 21

 MSI Logic Circuits
❑ Decoders:

(a) (b)
Figure 14. A 3-line-to-8-line (or 1-of-8) decoder. (a) Circuit diagram; (b) truth table.
• It is also referred to as a 1-of-8 decoder, because only 1 of 8 outputs is
activated at a time.

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 MSI Logic Circuits
❑ Decoders:
• Many decoders are designed to produce active-low outputs, where only the
selected output is LOW while all others are HIGH. This would be indicated
by the presence of small circles on the output lines in the decoder diagram.
• Some decoders do not utilize all of the 2N possible input codes but only
certain ones. For example, a BCD-to-decimal decoder has a four-bit input
code and ten output lines that correspond to the ten BCD code groups 0000 to
1001. Decoders of this type are often designed so that if any of the unused
codes are applied to the input, none of the outputs will be activated.
• Figure 14(a) shows the circuitry for a decoder with three inputs and 23 = 8
outputs. It uses all AND gates, and so the outputs are active-HIGH. The truth
table is shown in Figure 14(b). Note that for a given input code, the only
output that is active (HIGH) is the one corresponding to the decimal
equivalent of the binary input code (e.g., output O6 goes HIGH only when
CBA = 1102 = 610).
• This decoder can be referred to in several ways. It can be called a 3-line-to-8-line
decoder, because it has three input lines and eight output lines. It could also be called
a binary-to-octal decoder or converter because it takes a three-bit binary input code
and activates the one of the eight (octal) outputs corresponding to that code. 23
 MSI Logic Circuits
❑ Decoders:
✓ Example (1): Implement a BCD-to-Decimal Decoder Using AND gates
Solution:
• The elements of information in this case are the ten decimal digits represented
by the BCD code. The code itself has four bits. Therefore, the decoder
should have four inputs to accept the coded digit and ten outputs, one
for each decimal digit. This will give a 4 line to 10 line BCD-to-Decimal
decoder.
• Since the circuit has 10 outputs, it would be necessary to draw ten maps to
simplify each one of the output functions. There are 6 don’t-care conditions
here, and they must be taken into consideration when we simplify each of the
output functions.
• Instead of drawing 10 maps, we will draw only one map and write each of the
output variables, D0 to D9 as shown in Figure 15. Six input combinations will
never occur, so we mark their corresponding minterm squares with X’s.
• It is the designer’s responsibility to decide on how to treat the don’t-care
conditions. Assume that it is decided to use them in such a way as to simplify the
functions to the minimum number of literals.
• D0 and D1 cannot be combined with any don’t-care minterms. So D0 = w/x/y/z/
and D1 = w/x/y/z 24
 MSI Logic Circuits
❑ Decoders:
✓ Example (1): Implement a BCD-to-Decimal Decoder Using AND gates
Solution:

Figure 15. Map for simplifying a BCD-to-decimal decoder.

• D2 can be combined with the don’t-care minterm m10 to give: D2 = x/yz/

• Similarly, D3 = x/yz; D4 = xy/z/; D5 = xy/z; D6 = xyz/; D7 = xyz.
• The square with D8 and D9 can be combined with three other don’t-care squares
to give: D8 = wz/ and D9 = wz.
• The logic diagram of a BCD-to-Decimal decoder is illustrated in Figure 16.
25
 MSI Logic Circuits
❑ Decoders:
✓ Example (1): Implement a BCD-to-Decimal Decoder Using AND gates
✓Solution:

26
Figure 16. Logic diagram of a BCD-to-Decimal decoder.
 MSI Logic Circuits
❑ Decoders:
✓ Example (1): Implement a BCD-to-Decimal Decoder Using AND gates
Solution:
• An analysis of the circuit of Figure 16 shows that the six invalid input
combinations will produce outputs as listed Figure 17.

Figure 17. Partial truth table for a BCD-to-decimal decoder.

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 MSI Logic Circuits
❑ Decoders:
✓ Example (2): Implement a full adder circuit with a decoder and two OR gates
Solution:
• The truth table of the full adder is shown in Figure 18(a). From the truth
table, we obtain the functions for this combinational circuit in sum of
minterms:
S( A, B, C in ) =  (1,2, 4, 7)
C( A, B, Cin ) = (3,5, 6, 7)

(a) (b)
Figure 18. Implementation of full adder using a 38 decoder; (a) Truth table; (b) logic diagram.
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 MSI Logic Circuits
❑ Decoders:
✓ Example (2): Implement a full adder circuit with a decoder and two OR
gates
Solution:
• Since there are three inputs and a total of eight minterms, we need a 3-to-8
line decoder. The implementatuion is shown in Figure 18(b). The decoder
generates the eight minterms for A, B, Cin. The OR gate for output S forms
the sum of minterms 1, 2, 4, and 7. The OR gate for output Cout forms the
sum of minterms 3, 5, 6, and 7.
S( A, B, C ) = (1,2, 4, 7)
C( A, B, Cin ) = (3,5, 6, 7)

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 MSI Logic Circuits
❑ Decoders:
✓ Example (3): Design a 416 decoder with two 38 decoders Solution:
• The 416 decoder is shown in Figure 19. Here B input determines which one
of the decoder will be enabled, while A2A1A0 determines which output of the
enabled decoder will be activated.
• For example, when B is 0, then decoder 1 will be activated and if A2A1A0 =
101 then O5 of decoder 1 will be activated.
• Again, when B is 1, then the decoder 2 will be activated and if A2A1A0 = 101
then the fifth output of Decoder 2 i.e. O12 will be activated.

Figure 19. Implementation of a 416 decoder using two 38 decoders. 30

 MSI Logic Circuits
❑ Decoders:
✓ Example (4): Design a 24 decoder with enable input E
Solution:
• The truth table, circuit diagram, and symbol of the 24 decoder is shown in
Figures 20(a), 20(b), and 20(c), respectively.

Figure 20. 24 decoder with enable input E. (a) Truth table; (b) circuit diagram; (c) symbol.
31
 MSI Logic Circuits
❑ Decoders:
✓ Example (4): Design a 24 decoder with enable input E
Solution:
• Here the inputs are I1 and I2 and the outputs are O0, O1, O2, and O3. The
enable input is E. Therefore, the output expressions are:

O0 = I1.I 2
O1 = I1.I2
O2 = I1.I 2
O3 = I1.I2

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 MSI Logic Circuits
❑ Decoders:
✓ Example (5): Use 2-to-4 decoder modules to realize (a) 3-to-8 decoder and
(b) 4-to-16 decoder.
Solution:
• (a)

Figure 21(a). Logic diagram of 3-to-8 decoder using 2-to-4 decoder. 33

 MSI Logic Circuits
❑ Decoders:
✓ Example (5): Use 2-to-4 decoder modules to realize (a) 3-to-8 decoder and
(b) 4-to-16 decoder.
Solution:
• (b)

Figure 21(b). Logic diagram of 4-to-16 decoder using 2-to-4 decoder. 34

 MSI Logic Circuits
❑ Encoders:
• An encoder is a combinational logic module that assigns a unique output code
(a binary number) for each input signal applied to the device; as such, it is the
opposite of a decoder.
• An encoder has 2n (or less) input lines and n output lines. The output lines
generate the binary code for the 2n input variables. Figure 22 is the general
diagram for an encoder with M inputs and N outputs. If an encoder module
has n inputs, the number of outputs S musty satisfy the expression ~
2S  n
or, S  log2 n

35
Figure 22. General encoder diagram.
 MSI Logic Circuits
❑ Encoders:
• Figure 23 shows the logic circuit and the truth table for an octal-to-binary (8 line-
to-3 line) encoder accepts eight input lines and produces a three-bit output code
corresponding to the activated input.

(a)

(b)

36
Figure 23. (a) Logic diagram; (b) truth table.
 MSI Logic Circuits
❑ Encoders:
• By following through the logic, you can verify that a HIGH at any single input
will produce the output binary code corresponding to that input.
• For instance, a HIGH at D3 will produce O2 = 0, O1 = 1 and O0 = 1, which is the
binary code for 3.
• Notice that D0 is not connected to the logic gates because the encoder outputs
will normally be at 000 when none of the inputs D1 to D7 is HIGH.
✓ Example (6): Design a four-line encoder that outputs a zero code unless
only one and only one input line is active.

Solution:
• Let us define the code:

37
 MSI Logic Circuits
❑ Multiplexers:
• A digital multiplexer or data selector is a logic circuit that accepts several
digital data inputs and selects one of them at any given time to pass on to a
single output line.
• The routing of the desired data input to the output is controlled by SELECT
inputs (often referred to as ADDRESS inputs). Figure 1 shows the functional
diagram of a general digital multiplexer. The inputs and outputs are drawn as
wide arrows rather than lines; this indicates that they may actually be more
than one signal line.

41
Figure 26. Functional diagram of a digital multiplexer (MUX).
 MSI Logic Circuits
❑ Multiplexers:
• The multiplexer acts like a digitally controlled multiposition switch where the
digital code applied to the SELECT inputs controls which data inputs will be
switched to the output. For example, output Z will equal data input I0 to for
some particular SELECT input code; Z will equal data input I1 for another
particular SELECT input code and so on. The process is called multiplexing.
✓ Basic Two-Input (2-to-1) Multiplexer:-
• Figure 27 shows the logic circuitry for a two-input multiplexer with data
input I0 and I1 and SELECT input S. The logic level applied to the S input
determines which AND gate is enabled so that its data input passes through the OR
gate to output Z. Looking at it another way, the Boolean expression for the output is
~

• With S = 0, this expression becomes:

• Which means that Z will be identical

to input signal I0. 42
Figure 27. 2-to-1 multiplexer.
 MSI Logic Circuits
❑ Multiplexers:
✓ Basic Two-Input (2-to-1) Multiplexer:-
• With S = 1, the expression becomes ~
• Which means that output Z will be identical to input signal I1.
✓ Four-Input (4-to-1) Multiplexer:-
• Figure 28 shows the logic circuitry for a four input multiplexer with data
inputs I0, I1, I2, and I3 which are selectively transmitted to the output,
according to the four possible combinations of the S1S0 select inputs.

43
Figure 28. 4-to-1 multiplexer.
 MSI Logic Circuits
❑ Multiplexers:
✓ Four-Input (4-to-1) Multiplexer:-
• Each data input is gated with a different combination of select input levels. I0
is gated with so that I0 will pass through its AND gate to output Z only
when S1 = 0 and S0 = 0. The table in the figure gives the outputs for the other
three input-select codes.
✓ Eight-Input (8-to-1) Multiplexer:-
• Figure 4(a) shows the logic diagram for the 74ALS151 (74HC151) eight
input (8-to-1) multiplexer. The multiplexer has an enable input and
provides both the normal and inverted outputs.
• When the select inputs S2S1S0 will select one data input (from I0 through
I7) for passage to output Z. When the multiplexer is disabled so that Z =
0 regardless of the select input code.
• This operation is summarized in Figure 4(b), and the 74151 logic symbol is
shown in Figure 4(c).

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 MSI Logic Circuits
❑ Multiplexers:
✓ Eight-Input (8-to-1) Multiplexer:-

Figure 29. (a) Logic diagram of 8-to-1 multiplexer (74ALS151); (b) truth table; (c) logic symbol.
45
 MSI Logic Circuits
❑ Multiplexers:
✓ Example (7): Construct a 16-input (16-to-1) multiplexer using two
74HC151s, an INVERTER, and an OR gate. Describe the circuit’s operation.
Solution:
• This circuit has a total of 16 data inputs, eight applied to each multiplexer.

Figure 30. Two 74HC151s are combined to form a 16-to-1 multiplexer. 46

 MSI Logic Circuits
❑ Multiplexers:
✓ Example (7): Construct a 16-input (16-to-1) multiplexer using two
74HC151s, an INVERTER, and an OR gate. Describe the circuit’s operation.
Solution:
• The two multiplexer outputs are combined in the OR gate to produce a single
output X. The circuit functions as a 16-to-1 multiplexer. The four select
inputs S3S2S1S0 will select one of the 16 inputs to pass through to X.
• The S3 input determines which multiplexer is enabled. When S3 = 0,
multiplexer-1 is enabled. And S2S1S0 inputs determine which of the data
inputs will appear at its output and pass through the OR gate to X.
• When S3 = 1, multiplexer-2 is enabled, and the S2S1S0 input select one of its
data inputs for passage to output X.

47
 MSI Logic Circuits
❑ Multiplexers:
✓ Example (8): Design a 16-to-1 multiplexer using 4-to-1 multiplexers.
Solution:
• The implementation is shown in Figure 31.
• In order to select 16 data inputs 4-bit
(24 = 16) selectors S3S2S1S0 are needed.
• S3S2 is the selection code for higher-order bits
which is used to select the outputs of
the multiplexers 1 through 4.
• On the other hand, S1S0 is the selection code
for lower-order bits which is used to select the
inputs of each multiplexer (multiplexers 1
through 4).

Figure 31. A 16-to-1 multiplexer using 4-to-1

multiplexers.
48
 MSI Logic Circuits
❑ Multiplexers:
✓ Example (8): Design a 16-to-1 multiplexer using 4-to-1 multiplexers.
Solution:
• For example, when S3S2S1S0 = 0000, then the Mux-5 will select D0 , i.e. the
output of Mux-1 and selects the input I0 (D0 in case of Mux-1)
• Again, when S3S2S1S0 = 1001, then the Mux-5 will select D2 i.e. the output of
Mux-3 and selects the input I9 (D1 of Mux-3).

49
 MSI Logic Circuits
❑ Multiplexers:
✓ Example (9): Implement the expression F(A,B,C) =  (1,3,5,6) using a
multiplexer.
Solution:
• The Truth Table is shown in Figure 32(b). There are 4 minterms. So, two of the
variables, B and C, are applied to the selection lines where B is connected to S1 and C
is connected to S0. The remaining single variable of the function A is used for the
inputs of the multiplexer, as shown in Figure 32(a).

Figure 32. Implementation of F(A,B,C) =  (1,3,5,6) using a multiplexer. 50

 MSI Logic Circuits
❑ Multiplexers:
✓ Example (9): Implement the expression F(A,B,C) =  (1,3,5,6) using a
multiplexer.
Solution:
• The implementation table is shown in Figure 32(c). The inputs of the
multiplexer are 0, 1, A, and A . When BC = 00, output F = 0 since I0 = 0.
Therefore, both minterms m0 =A B C and m4 = A B C produce a 0 output, since
the output is 0 when BC = 0 regardless of the value of A.
• When BC = 01, output F = 1, since I1 = 1. Therefore both minterms m1 =A B C
and m5 =A B C produce a 1 output, since the output is 1 when BC = 01
regardless the value of A.
• When BC = 10, input I2 is selected. Since A is connected to this input, the
output will be equal to 1 only for minterm m6 =A B C , but not for minterm
because when A = 1, the A = 0, and since I2 = 0, we have F = 0.
m2 = A B C ,

• Finally, when BC = 11, input I3 is selected. Since A is connected to the input,

the output will be equal to 1 only for mintermm3 = A B C but not for m7 =A B C .
• This information is summarized in Figure 32(a). 51
 MSI Logic Circuits
❑ Multiplexers:
✓ Example (10): Implement the following function with a multiplexer.
F(A, B, C, D) = (0,1,3,4,8,9,15).
Solution:
• The implementation is summarized in Figure 33(b). This is a four variable
function and therefore we need a multiplexer with three selection lines and 8
inputs.

52
Figure 33. Implementation of F(A, B, C, D) = (0,1,3,4,8,9,15) using a multiplexer.
 MSI Logic Circuits
❑ Multiplexers:
✓ Example (10): Implement the following function with a multiplexer.
F(A, B, C, D) = (0,1,3,4,8,9,15).
Solution:
• Thus we need one 8-to-1 Mux. We choose variables B, C, and D to the
selection lines S2, S1, and S0, respectively. The table is shown in Figure 33(a).
• The first half of the minterms are associated withA and the second half with A.
By cycling the minterms of the function and applying the rules for finding
values for the multiplexer inputs, we obtain the implementation shown.

N.B.: In some cases, you will be provided the Truth Table. In that case, the
function should be written in the form of minterms. Afterwards, the solution
can be achieved using the process shown in Examples (9) and (10).

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 MSI Logic Circuits
❑ Demultiplexers:
• A demultiplexer connects a single input line to one of the n output lines, the
specific output line being determined by an s-bit selection code, where ~
2S  n
• Figure 34 shows the functional diagram for a digital demultiplexer.

Figure 34. Functional diagram of a digital demultiplexer.

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• The select input code determines to which output the DATA input will be transmitted.
 MSI Logic Circuits
❑ Demultiplexers:
• In other words, the demultiplexer takes one input data source and selectively
distributes it to 1 of N output channels just like a multi-position switch.
❑ 1-Line-to-8-Line Demultiplexers:
• Figure 35 shows the logic diagram for a demultiplexer that distributes one
input line to eight output lines. The single data input line is connected to all
eight AND gates, but only one of these gates will be eneabled by the
SELECT input lines.
• For example, with S2S1S0 = 000, only AND gate 0 will be enabled, and data
input I will appear at output O0. Other SELECT codes cause input I to reach
the other outputs. The Truth Table summarizes the operation.

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 MSI Logic Circuits
❑ 1-Line-to-8-Line Demultiplexers:

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Figure 35. (a) Functional diagram of a 1-line-to-8-line demultiplexer; (b) truth table.
 MSI Logic Circuits
❑ Demultiplexers:
✓ Example (11): Design a 1-to-4 demultiplexer with enable.
Solution:
• The implementation is shown in Figure 36. This 1-to-4 data distributor has an
enable signal (E) that controls the operation of the circuit. When E = 1, the
circuit is operational. I is the input signal to be distributed to the n output
lines. When BA = 00, the m0 output of the 2-to-4 decoder will be activated
and the input I will be connected to the output line Y0 and so on.

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Figure 36. Functional diagram of the 1-to-4 demultiplexer.
 MSI Logic Circuits
❑ Homework:
• R. P. Jain: Chapter 6 → Example 6.3 (Page 239), Demultiplexer Tree (Page
240), Page 241.

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 References
1 “Digital Systems: Principles and Applications,” Neal S. Widmer, Gregory L.
Moss, and Ronald J. Tocci, 12th Ed., Pearson (2018).

2 “Digital Logic and Computer Design,” M. Morris Mano, Pearson (2016).

3 “Modern Digital Electronics,” R P Jain, 4th Ed., Tata McGraw Hill

Education Private Limited (2010).

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