International Journal of All Research Education and Scientific Methods (IJARESM),

ISSN: 2455-6211, Volume 12, Issue 10, October-2024, Available online at: www.ijaresm.com

Design and Implementation of 8T SRAM Cell and

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ABSTRACT

SRAM (static random-access memory) is used to store the cache memory or data in static form. Unlike DRAM
(dynamic random-access memory) it needs not to be refreshed. SRAM gives faster access than DRAM and it retains
data bits as long as power is being supplied. DRAM uses capacitor to store the data bits whereas SRAM uses
latching circuit (flip-flop). The latching circuit consists of four transistors (two CMOS inverters which are cross
coupled) act as memory part. This paper compares 8TSRAM Cell with 6T and 7T SRAM using Tanner EDA tools
on 90 nm technology. For all SRAMs, all the parameters such as Read noise margin, W-rite noise margin, and Hold
noise margin are calculated and compared at different cell ratios. In our simulation we found that 8T SRAM cells
have a larger noise margin than 6T SRAM cells and 7T SRAM Cell at the same cell ratio, and as the cell ratio
increases noise margins also increase.

Keywords: SRAM CELL, CMOS Inverters, DRAM, Power consumption, Propagation delay

INTRODUCTION

SRAM is preferred over DRAM as it provides faster access of data and unlike DRAM it needs not to be refreshed. It is
designed for low power consumption. SRAM uses numbers of transistors with compressed circuit design which leads to the
high cost of SRAM’s. 8T SRAM cell uses eight transistors. The combination of four transistors creates two CMOS
inverters, while the remaining transistors serve as access transistors, connected to the bit line and bit line bar. A 7T SRAM
cell is constructed with dual CMOS inverters inter connected with a NMOS transistor, which is connected to read line. A
pair of NMOS transistors acts as access transistors tethered to bit line and bit line bar.6T SRAM cell uses six transistors.
The combination of four transistors creates two CMOS inverters, while the remaining transistors serve as access transistors,
connected to the bit line and bit line bar. In this paper 8T SRAM Cell, 6T SRAM Cell and 7T SRAM cells are designed at
90nm technology to compare in terms of Read, Write and Static noise margins at different cell ratios.

Existing Techniques
2.1 6t Sram
6T SRAM Six transistors are used in a 6T SRAM, two PMOS transistors and the remaining four NMOS transistors. The
cell's memory element is two CMOS inverters formed by cross coupling two PMOS transistors with two NMOS transistors.
Bit line and bit line bar are connected to the remaining two NMOS transistors, which are controlled by the word line. The
word line is used because it provides the current for selecting which bit row should be written or read, and the bit line is
used to read the bit on the word line or to programmed it with current.

Figure 1 6T SRAM Cell

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 International Journal of All Research Education and Scientific Methods (IJARESM),
ISSN: 2455-6211, Volume 12, Issue 10, October-2024, Available online at: www.ijaresm.com

2.2 7 T SRAM
In a 7T SRAM cell, two CMOS inverters are cross connected with one NMOS transistor connected to the read line. An
access transistor in a 7T SRAM cell is a pass NMOS transistor tethered to the bit line and the bit line bar.

Figure 2 7T SRAM Cell

Proposed 8t Sram Cell

The schematic of the proposed 8T SRAM cell is presented in Figure which uses single bit-line for read and write operations
but has an extra world-line (RWL) for read. For a conventional 6T cell the worst-case Static Noise Margin (SNM) occurs in
the read condition. This structural change is to improve the stability of the cell and eliminate the read disturb existing in the
conventional 6T SRAM cell. In this SRAM cell design, transistor P3 is used to enhance the write margin and low power
consumption of the circuit by breaking-up the feedback loop of the inverter pair. In next two subsections, we will introduce
the operating principles of the proposed 8T cell in detail.

Figure 3: Proposed 8T SRAM Cell

3. Simulation Results

Figure 4:6T SRAM Cell Schematic diagram and output waveform

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International Journal of All Research Education and Scientific Methods (IJARESM),
ISSN: 2455-6211, Volume 12, Issue 10, October-2024, Available online at: www.ijaresm.com

Figure 5:6T SRAM Cell Output waveform

Figure 6:7T SRAM Cell Schematic diagram

Figure 7:7T SRAM Cell Output waveform

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 International Journal of All Research Education and Scientific Methods (IJARESM),
ISSN: 2455-6211, Volume 12, Issue 10, October-2024, Available online at: www.ijaresm.com

Figure 8:8T SRAM Cell Schematic diagram

Figure 9:8T SRAM Cell Output waveform

The above figures provides the simulation result for the newly designed 8T SRAM along with existing like 6T SRAM and
7T SRAM. The design is implemented in Tanner EDA tool. The waveform representing various voltage levels for the
existing 6T, 7T and 8T SRAM are given here. From the waveform it can be inferred that in the 8T SRAM structure, the
stored value is preserved during read operation.

CONCLUSION

The design and analysis of SRAM cells with varying transistor counts, specifically 6T, 7T, and 8T, reveal notable
differences in terms of stability, power consumption, area, and performance, making each configuration suitable for
different applications.The 8T SRAM cell demonstrated superior stability due to the decoupling of read and write
operations, reducing the chances of data corruption during read operations. This was evident in a higher read stability
compared to the 6T and 7T designs. The 6T cell, while compact and efficient, showed reduced stability, especially in sub-
threshold operations, making it less reliable in low-power scenarios. The 7T cell improved stability somewhat over the 6T
cell but did not match the 8T’s performance.The 8T cell, with its improved read decoupling, provides faster and more
reliable read access, beneficial for applications requiring higher performance and reduced latency. In contrast, the 6T and
7T cells offer a trade-off between area and read stability, with the 6T design being more vulnerable to variability at smaller
nodes.

REFERENCES

[1]. EzeoguChinonsoApollos, “Performance Analysis of 6t and 9t Sram”, International Journal Of Engineering Trends and
Technology (Ijett) – Volume 67 Issue 4 - April 2019.
[2]. Varanasi Koundinya, JithendraPulivarthi, Madanu Karun Chand, D.Jayanth Sai Kumar, “Performance Evaluation of
6T SRAM cell using 90 nm Technology”, International Journal of Engineering Research & Technology (IJERT) Vol.
10 Issue 09, September-2021.

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 International Journal of All Research Education and Scientific Methods (IJARESM),
ISSN: 2455-6211, Volume 12, Issue 10, October-2024, Available online at: www.ijaresm.com

[3]. AjjayGaadhe, Ujwal Shirode, Rajendra Kanphade, “The Stability Performance Analysis of SRAM Cell Topologies in
90nm and 130nm CMOS technology”, 2021 International Conference on Emerging Smart Computing and Informatics
(ESCI) AISSMS Institute of Information Technology, Pune, India. Mar 5-7, 2021.
[4]. Sahan Panguluru, Jai Gopal Pandey, “A Highly Stable and Robust 7T SRAM Cell using Memristor”, 24th International
Symposium on VLSI Design and Test (VDAT), 23-25 July 2020.
[5]. FarshadMoradi, Mohammad Tohidi, BehzadZeinali, and Jens K. Madsen, “8T-SRAM Cell with Improved Read and
Write Margins in 65 nm CMOS Technology”, 22nd International Conference on Very Large Scale Integration (VLSI-
SoC), 6-8 Oct. 2014.

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