explain boundry scan in detail

Boundary scan, also known as JTAG (Joint Test Action Group) testing, is a method of testing and
debugging electronic devices, such as integrated circuits (ICs) and printed circuit boards (PCBs),
by providing a standardized way to access the internal pins of a device. JTAG is a standard
defined by the IEEE 1149.1 specification.

Boundary scan testing allows for the device's internal pins to be accessed and controlled through
a test access port (TAP) that is built into the device. This allows for the testing of interconnections
between ICs on a PCB, as well as testing of the ICs themselves. The TAP is essentially a small
processor that is built into the IC or PCB and can be used to shift data in and out of the device's
internal registers, and control the device's internal logic.

The boundary scan testing process typically involves several steps:

1. The device is connected to a boundary scan controller, which is typically a piece of test
equipment.
2. The boundary scan controller uses the TAP to access the device's internal registers and
shift in a series of test patterns.
3. The device's internal logic is then exercised and the resulting outputs are captured by the
boundary scan controller.
4. The captured outputs are compared to the expected results to determine if there are any
faults.

Boundary scan testing can be useful for several reasons:

• It can detect and diagnose faults that might be difficult to find with other types of testing,
such as intermittent or hard-to-reach connections.
• It can be performed without the need to physically probe the device, which can be useful
for devices that are difficult to access, such as those that are embedded in a larger system
or are located in hard-to-reach places.
• It can be used to test devices during the manufacturing process and in-field.

While boundary scan testing can be a useful method for testing and debugging electronic
devices, it is not a replacement for other types of testing and is typically used in conjunction with
other testing methods such as functional testing and in-circuit testing.

explain TAP Controller. in detail

A TAP (Test Access Port) controller is a component of the JTAG (Joint Test Action Group) testing
method, which is used to access and control the internal pins of an electronic device for the
purpose of testing and debugging.

A TAP controller is a small processor that is built into the device being tested, and it is
responsible for controlling the TAP and providing a means of communication between the device
and the boundary scan controller.

The TAP controller is essentially a finite state machine (FSM) that is controlled by a set of
instructions called JTAG instructions, which are used to access the device's internal registers and
shift data in and out of the device. The TAP controller is also responsible for managing the TAP's
state, which can be in one of four possible states:

• Test-Logic-Reset
• Run-Test/Idle
• Select-DR-Scan
• Select-IR-Scan

In Test-Logic-Reset state, TAP controller is reset and then it goes to Run-Test/Idle state. In this
state, the instruction register and data register can be selected. Select-DR-Scan state is where the
data register is selected and data can be shifted in and out of the device, and in Select-IR-Scan
state instruction register is selected and JTAG instruction can be shifted in the device.

The TAP controller is a crucial component of JTAG testing because it allows the boundary scan
controller to communicate with the device and access its internal pins and registers. This allows
for the testing of interconnections between ICs on a PCB, as well as testing of the ICs themselves.
Because the TAP controller is built into the device, it can also be used for in-system
programming, which is a process of programming an IC after it has been mounted on a PCB.

However, not all ICs have built-in TAP controllers, for such ICs external TAP controller can be
used. External TAP controller can be attached to the device and it can simulate TAP controller
operations.

explain JTAG in detail

JTAG (Joint Test Action Group) is a standard for testing and debugging electronic devices, such as
integrated circuits (ICs) and printed circuit boards (PCBs). The JTAG standard, which is defined by
the IEEE 1149.1 specification, provides a standardized method for accessing the internal pins of a
device for the purpose of testing and debugging.

The JTAG standard is based on the use of a TAP (Test Access Port) controller, which is a small
processor that is built into the device being tested. The TAP controller controls the TAP and
provides a means of communication between the device and a boundary scan controller, which is
typically a piece of test equipment. The TAP controller is a finite state machine (FSM) controlled
by a set of instructions called JTAG instructions, which are used to access the device's internal
registers and shift data in and out of the device.

JTAG testing typically involves several steps:

1. Connecting the device to a boundary scan controller.

2. Using the TAP controller to access the device's internal registers and shift in a series of
test patterns.
3. Exercising the device's internal logic and capturing the resulting outputs using the
boundary scan controller.
4. Comparing the captured outputs to the expected results to determine if there are any
faults.

JTAG testing can be useful for several reasons:

 • It can detect and diagnose faults that might be difficult to find with other types of testing,
such as intermittent or hard-to-reach connections.
• It can be performed without the need to physically probe the device, which can be useful
for devices that are difficult to access, such as those that are embedded in a larger system
or are located in hard-to-reach places.
• It can be used to test devices during the manufacturing process and in the field.

JTAG testing is not a replacement for other types of testing and is typically used in conjunction
with other testing methods such as functional testing and in-circuit testing.

JTAG also defined a standard for On-Chip Debugging (OCD) using JTAG as well. It helps to debug
a software running on a microcontroller or microprocessor. It allows a developer to halt a running
program, single-step through the code, read and write memory and registers and even modify
the program flow by writing to memory. JTAG has become the de facto standard for OCD and it
is supported by most of the processors.

In summary JTAG is a widely used standard that provides a standardized way to access and
control the internal pins of a device for the purpose of testing and debugging, whether it be for
just testing, or debugging the software running on the device.

explain Built In Self Test in detail

Built-In Self Test (BIST) is a method of testing electronic devices, such as integrated circuits (ICs)
and printed circuit boards (PCBs), by incorporating test logic into the device itself. The purpose of
BIST is to detect and diagnose faults within the device, without the need for external test
equipment.

BIST typically involves the following steps:

1. The device is initialized and configured for testing.

2. Test patterns are generated and applied to the device's inputs.
3. The device's internal logic and interconnections are exercised, and the resulting outputs
are captured.
4. The captured outputs are compared to expected results to determine if there are any
faults.

There are several types of BIST approaches that can be used, including:

• Stuck-at fault testing: This type of testing involves applying a set of test patterns to the
device and checking the outputs for any stuck-at faults, which occur when a signal is
stuck at a logic high or low level.
• Signature analysis: This type of testing involves applying a set of test patterns to the
device and capturing the resulting outputs as a signature. The signature is then compared
to expected results to determine if there are any faults.
• Pseudorandom pattern testing: This type of testing involves applying a sequence of
pseudorandom patterns to the device and checking the outputs for any errors.

BIST is useful for several reasons:

 • It allows for the testing of devices during the manufacturing process, which can help to
reduce the number of defective devices that are shipped to customers.
• It can be used to test devices in the field, which can help to reduce the number of devices
that need to be returned for repairs.
• It can be used to test devices that are difficult to access, such as those that are embedded
in a larger system or are located in hard-to-reach places.

However, BIST has some limitations too, such as it might not be able to detect all possible types
of faults and also it adds additional complexity and cost to the device.

In summary, BIST is a method of testing electronic devices by incorporating test logic into the
device itself. It allows for the detection and diagnosis of faults within the device without the need
for external test equipment. It can be used to test devices during the manufacturing process, in
the field, or for devices that are difficult to access.

explain Sequential circuit test in detail

Sequential circuit testing is a method of testing sequential circuits, such as flip-flops and state
machines, to ensure that they are functioning properly. A sequential circuit is a type of digital
circuit that has memory elements, such as flip-flops, which store the previous state of the circuit.

There are several methods that can be used for sequential circuit testing, including:

• Stimulus-response testing: This method involves applying a stimulus, or input, to the

circuit and observing the response, or output. The response is then compared to the
expected result to determine if the circuit is functioning properly.
• State transition testing: This method involves testing the circuit's ability to transition
between different states. The circuit is initialized to a known state, and test patterns are
applied to the inputs to force the circuit to transition through a series of states. The
circuit's output and the sequence of states visited are compared to the expected results
to determine if the circuit is functioning properly.
• Path delay testing: This method is used to test the delay of the paths inside the circuit. By
applying a sequence of input patterns, the delay of each path can be measured and
compared to expected values.

In addition to these testing methods, there are several other techniques that can be used to test
sequential circuits, such as:

• formal verification: using mathematical logic or model checking to prove that the circuit
is equivalent to a model.
• fault simulation: simulating faults in the circuit to see if they can be detected.

Sequential circuit testing is important because it helps to ensure that the circuit is functioning
properly and that it will work correctly in the end application. This can help to reduce the number
of defective circuits that are shipped to customers and improve the overall reliability of the
circuit.
In summary, sequential circuit testing is a method of ensuring that sequential circuits, such as
flip-flops and state machines, are functioning properly. There are several methods that can be
used for sequential circuit testing, including stimulus-response testing, state transition testing,
path delay testing, formal verification, and fault simulation. These testing methods help to ensure
that the circuit will work correctly in the end application and improve the overall reliability of the
circuit.

explain Test pattern generation in detail

Test pattern generation is the process of creating a set of test inputs for a digital circuit or
system, with the goal of providing comprehensive coverage of the circuit's functionality. The
process of generating test patterns is often used in the manufacturing process for electronic
devices and also in functional verification of digital systems.

There are several methods that can be used for test pattern generation, including:

• Manual test pattern generation: This method involves creating test patterns manually by
a designer or engineer. It is a time-consuming and error-prone process and is typically
used for small or simple circuits.
• Pseudorandom test pattern generation: This method involves using a pseudorandom
number generator to create test patterns. The test patterns generated by this method are
random, but they can be reproduced if necessary. This method is useful for detecting
random faults, but it may not provide comprehensive coverage of the circuit's
functionality.
• Deterministic test pattern generation: This method involves using a formal algorithm or
mathematical model to create test patterns. The test patterns generated by this method
are completely determined by a set of initial conditions and the algorithm or model used.
This method is useful for providing comprehensive coverage of the circuit's functionality,
but it can be computationally expensive and may not be suitable for very large circuits.

When generating test patterns, it is important to consider the types of faults that the circuit is
likely to encounter and to create test patterns that will detect those faults. For example, stuck-at
faults, which occur when a signal is stuck at a logic high or low level, can be detected by applying
test patterns that force the signal to transition between the two levels. Similarly, transition faults,
which occur when a signal does not transition at the expected time, can be detected by applying
test patterns that force the signal to transition at different times.

One of the most widely used method for test pattern generation is Automatic Test Pattern
Generation (ATPG) this method uses various algorithms and approaches to generate test patterns
that will detect a wide range of faults in the circuit.

In summary, Test pattern generation is the process of creating a set of test inputs for a digital
circuit or system, with the goal of providing comprehensive coverage of the circuit's functionality.
There are several methods that can be used for test pattern generation, including manual,
pseudorandom, deterministic, and Automatic Test Pattern Generation (ATPG) methods. ATPG
method is widely used and provides comprehensive coverage of the circuit's functionality. It is
important to consider the types of faults that the circuit is likely to encounter when generating
test patterns, in order to create test patterns that will detect those faults.
explain Path sensitizing in detail
Path sensitizing is a technique used in Automatic Test Pattern Generation (ATPG) to generate test
patterns for a digital circuit. The goal of path sensitizing is to generate test patterns that can
detect as many faults as possible in the circuit by selectively stimulating specific paths in the
circuit.

The ATPG process generally starts by identifying all the possible faults in the circuit, then the
ATPG tool tries to find a test pattern that can detect each fault. Path sensitizing is used to
generate test patterns that will detect specific faults by stimulating specific paths in the circuit.
The basic idea is that a fault can only be detected if it is stimulated and the output is observed, so
the goal is to find the right input pattern that will stimulate the fault.

There are several types of path sensitizing techniques that can be used:

• Directed path sensitizing: This method involves using the logic of the circuit to selectively
stimulate specific paths in the circuit. The goal is to create test patterns that will stimulate
the fault directly, without also stimulating any other faults.
• Plg crLimited path sensitizing: This method involves using a limited number of test
patterns to stimulate a specific path in the circuit. The goal is to create test patterns that
will stimulate the fault with a high probability, without also stimulating any other faults.

Path sensitizing can be an effective technique for detecting faults in a digital circuit, but it can
also be a computationally intensive process. It is also important to note that path sensitizing
alone may not cover all possible faults in a circuit and needs to be used in conjunction with other
ATPG techniques like Random testing and/or fault simulation.

In summary, Path sensitizing is a technique used in Automatic Test Pattern Generation (ATPG) to
generate test patterns for a digital circuit. The goal of path sensitizing is to generate test patterns
that can detect as many faults as possible in the circuit by selectively stimulating specific paths in
the circuit. There are several types of path sensitizing techniques that can be used, including
Directed path sensitizing and Limited path sensitizing. Path sensitizing can be an effective
technique for detecting faults in a digital circuit, but it can also be a computationally intensive
process and it should be used in conjunction with other ATPG techniques to provide
comprehensive coverage.

explain DFT Guidelines

Design for Test (DFT) guidelines refer to a set of best practices and techniques that can be used
to design digital circuits in a way that makes them more easily testable. The goal of DFT is to
make it easier to generate test patterns and to detect faults in the circuit.

Here are some of the key DFT guidelines:

• scan design: One of the most widely used DFT technique is Scan Design. A scan design is
an efficient way to shift in test patterns and shift out results to check if the design
behaves correctly. In this method, the Flip-flops of a circuit are grouped into a scan chain
 where the input of the first flip-flop is connected to the output of the last flip-flop. This
allows all the flip-flop's internal state to be serially shifted into the scan chain, making it
easy to test all the internal states of the circuit.
• Built-in self-test (BIST): By incorporating test logic into the device, BIST can detect and
diagnose faults within the device without the need for external test equipment. This
technique reduces the test time and equipment cost while increasing the test coverage.
• Boundary scan: JTAG (Joint Test Action Group) testing, also known as boundary scan
testing, provides a standardized way to access the internal pins of a device for the
purpose of testing and debugging.
• Adequate observability and controllability: To make the design testable, it's important to
have access to the internal signals of the design. This can be achieved by adding test
points, scan cells, and multiplexers to the design.
• Keep it simple: Simple designs are usually easier to test than complex designs. This means
that the design should be kept as simple as possible and that unnecessary complexity
should be avoided.
• Use industry standard: By following industry standard, it will be easier to generate test
patterns and to interface the design with test equipment.

In summary, DFT guidelines are a set of best practices and techniques that can be used to design
digital circuits in a way that makes them more easily testable. The goal of DFT is to make it easier
to generate test patterns and to detect faults in the circuit. Some of the key DFT guidelines

Need of Design for Testability

Design for Testability (DFT) is an important aspect of digital circuit design because it helps to
ensure that the circuit will be easy to test and that any faults in the circuit can be quickly and
easily detected.

Here are some reasons why DFT is important:

• Cost savings: By making a circuit easy to test, it can save money on test equipment and
reduce the overall cost of testing the circuit. It also reduces the number of defective
circuits that are shipped to customers, which can save money on warranty repairs and
replacements.
• Improved quality: DFT helps to ensure that the circuit is functioning properly, which can
improve the overall quality of the circuit. This can help to reduce the number of defective
circuits that are shipped to customers and improve the overall reliability of the circuit.
• Reduced time to market: By making a circuit easy to test, it can help to speed up the
testing process and reduce the overall time to market for the product.
• In-system programming: By incorporating scan design, it allows for the in-system
programming of integrated circuits, which eliminates the need to remove the circuit from
the board for programming.
• Efficient test development: DFT techniques such as scan design and built-in self-test
(BIST) allows for the automatic generation of test patterns, which can save time and
resources during test development.
• Improved fault coverage: DFT techniques such as scan design and built-in self-test (BIST)
can improve the fault coverage of the design, as they enable detection of faults that
might be missed by traditional testing methods.
In summary, DFT is an important aspect of digital circuit design because it helps to ensure that
the circuit will be easy to test and that any faults in the circuit can be quickly and easily detected.
It can save money on test equipment, reduce the overall cost of testing the circuit, improve the
quality, reduce the time to market, allows for in-system programming, efficient test development
and improve the fault coverage of the design.

explain stuck at 0 and stuck at 1 fault

Stuck-at faults are one of the most common types of faults that can occur in digital circuits. They
refer to faults where a logic element, such as a gate or flip-flop, is stuck in a particular logic state.
There are two types of stuck-at faults: stuck-at-0 and stuck-at-1.

• Stuck-at-0 faults: A stuck-at-0 fault occurs when a logic element is stuck at a logic low or
zero level. This means that the output of the logic element will always be 0, regardless of
the input. This type of fault can cause the circuit to behave incorrectly and may cause
other logic elements in the circuit to also malfunction.
• Stuck-at-1 faults: A stuck-at-1 fault occurs when a logic element is stuck at a logic high or
one level. This means that the output of the logic element will always be 1, regardless of
the input. Like the stuck-at-0 faults, this type of fault can cause the circuit to behave
incorrectly and may cause other logic elements in the circuit to also malfunction.

Both stuck-at-0 and stuck-at-1 faults can be detected by applying test patterns that force the
logic element to transition between the two levels and observing the resulting output. This can
be done through manual testing, or automated testing methods such as Automatic Test Pattern
Generation (ATPG) or fault simulation.

In summary, Stuck-at faults are a common type of faults that can occur in digital circuits. They
refer to faults where a logic element is stuck in a particular logic state. The two types of Stuck-at
faults are Stuck-at-0 (stuck at logic 0 level) and Stuck-at-1 (stuck at logic 1 level) , both can cause
the circuit to behave incorrectly and may cause other logic elements in the circuit to also
malfunction. Both can be detected by applying test patterns that force the logic element to
transition between the two levels and observing the resulting output.

explain Testability
Testability refers to the ability to test a system or device to determine if it is functioning correctly.
In the context of digital circuits, testability refers to the ability to generate test patterns and to
observe the response of the circuit, in order to detect any faults or defects.

There are several factors that can affect testability, such as:

• Circuit design: The design of the circuit can affect testability. For example, a circuit that is
well-structured and has clearly defined inputs and outputs will be easier to test than a
circuit that is poorly structured or has a complex topology.
• Observability and controllability: The ability to observe and control the internal signals of
a circuit is important for testability. This can be achieved by adding test points, scan cells,
and multiplexers to the design.
 • Built-in self-test (BIST): The inclusion of BIST can improve testability by allowing the
circuit to perform self-tests without the need for external test equipment.
• Test equipment: The availability and quality of test equipment can also affect testability.
Having access to advanced test equipment can make testing faster and more efficient,
while a lack of or poorly functioning equipment can make testing difficult or impossible.
• Testability standards: Adhering to industry testability standards, such as JTAG (Joint Test
Action Group), can make it easier to generate test patterns and interface with test
equipment.

In summary, Testability refers to the ability to test a system or device to determine if it is

functioning correctly. Factors that can affect testability include circuit design, observability and
controllability, built-in self-test, test equipment, and adherence to industry testability standards.
Good design for testability (DFT) practices aim to improve testability by reducing the need for
external test equipment and making it easier to observe and control the internal signals of the
circuit.

explain controlablity
Controllability refers to the ability to control the input signals of a system or device during
testing. In the context of digital circuits, controllability refers to the ability to apply specific test
patterns to the inputs of a circuit, in order to observe the response of the circuit and detect any
faults or defects.

Controllability is an important aspect of testability, as it allows the tester to apply specific test
patterns to the inputs of a circuit in order to stimulate the circuit and observe its response. This is
important for detecting faults and verifying that the circuit is functioning correctly.

There are several factors that can affect controllability, such as:

• Circuit design: The design of the circuit can affect controllability. For example, a circuit
that has clearly defined inputs and outputs will be easier to control than a circuit that has
complex or undefined inputs and outputs.
• Test points: The inclusion of test points in the circuit can improve controllability by
allowing the tester to more easily apply test patterns to the inputs of the circuit.
• Multiplexers: The use of multiplexers in the circuit can also improve controllability by
allowing the tester to more easily apply test patterns to specific inputs of the circuit.
• Scan chains: Scan chains are a widely used technique to improve controllability, by
allowing to shift in test patterns and shift out results to check if the design behaves
correctly.
• Power state : Controllability is also affected by the power state of the circuit. It is
important to have the ability to control the power state of the circuit in order to test it in
different operating conditions

In summary, Controllability refers to the ability to control the input signals of a system or device
during testing. It is an important aspect of testability, as it allows the tester to apply specific test
patterns to the inputs of a circuit in order to stimulate the circuit and observe its response.
Factors that can affect controllability include circuit design, test points, multiplexers, scan chains
and power state. Good design for testability (DFT) practices aim to improve controllability by
providing clear defined inputs and outputs and including test points, multiplexers and scan
chains to the design.

explain observablity
Observability refers to the ability to observe and measure the internal signals of a system or
device during testing. In the context of digital circuits, observability refers to the ability to access
and measure the internal signals of a circuit, in order to detect any faults or defects.

Observability is an important aspect of testability, as it allows the tester to observe the response
of the circuit to specific test patterns and detect any faults. It also allows the tester to evaluate
the circuit's internal state, making it possible to detect internal faults such as stuck-at, or
transition faults.

There are several factors that can affect observability, such as:

• Circuit design: The design of the circuit can affect observability. For example, a circuit that
has well-defined internal signals and clear access to them will be more observable than a
circuit that has complex or poorly defined internal signals.
• Test points: The inclusion of test points in the circuit can improve observability by
allowing the tester to more easily measure the internal signals of the circuit.
• Scan chains: Scan chains are a widely used technique to improve observability, by
allowing to shift in test patterns and shift out results to check if the design behaves
correctly.
• On-chip instrumentation: On-chip instrumentation can improve observability by allowing
the internal signals to be monitored and analyzed during test mode.
• Fault simulation: Observability can also be improved by simulating different types of
faults and observing the circuit's response, this allows the designer to check if the circuit's
response is as expected or if it needs to be modified.

In summary, Observability refers to the ability to observe and measure the internal signals of a
system or device during testing. It is an important aspect of testability, as it allows the tester to
observe the response of the circuit to specific test patterns and detect any faults. Factors that can
affect observability include circuit design, test points, scan chains, on-chip instrumentation and
fault simulation. Good design for testability (DFT) practices aim to improve observability by
providing clear defined internal signals and access to them and including test points, scan chains,
on-chip instrumentation.