Verilog
HDL
Content Course
› Day one : Syntax and Rules
› Day Two : Synthesis
› Day Three: Test Bensh
› Day Four :FSM
› Day Five :TOP Level integrated
Evolution of Computer-Aided Digital Design
Digital circuit design has evolved rapidly over the last 25 years. The first
integrated circuit (IC) chips were SSI chips where the gate count was very small,
Then after As technologies became sophisticated place circuits with hundreds of
gates on a chip These chips were called MSI, With the advent of LSI , designers
could put thousands of gates on a single chip, With the advent of VLSI
technology designers could design single chips with more than 100,000
transistors.
SSI MSI LSI VLSI
Small Scale Medium Scale Large Scale Very large Scale
Integration Integration Integration integration
Hardware Description Language (HDL)
Because of increase of number of gates in Chip and More
Complexity of chip it is more difficult using traditional method
[Schematic by GUI] in the digital design field, designers became
felt the need for a standard language to describe digital circuits.
Hardware description languages such as Verilog HDL and VHDL
became popular. Verilog HDL is an accepted IEEE standard. In
1995.The latest Verilog HDL standard that made significant
improvements to the original standard in 2001.
Digital circuits could be described at a register transfer level (RTL) by use of an HDL. Thus, the
designer had to specify how the data flows between registers and how the design processes
the data. The details of gates and their interconnections to implement the circuit were
automatically extracted by logic synthesis tools from the RTL description.
Designers no longer had to manually place gates to build digital circuits. They could describe
complex circuits at an abstract level in terms of functionality and data flow by designing those
circuits in HDLs.
A common approach is to design each IC chip, using an HDL, and then verify system
functionality via simulation.
ASIC FLOW VS FPGA Flow
• Spending 70-80% of the ASIC/FPGA commonly in design cycle writing and simulating
Verilog at and above the register transfer level.
ASIC FLOW FPGA FLOW
EDA TOOLS
EDA tools have emerged to
simulate behavioral
descriptions of circuits.
although EDA tools are EDA Tools
available to automate the
processes and cut design Xillinx Model
VIVADO Quarts VCS
cycle times, the designer is ISE sim
still the person who
controls how the tool will
perform. Simulation ONLY
FPGA ONLY
Design module
Design Module :
Typically, a design consists of either some or all of these parts .
//Name Module (ports )
//define parameter
//declaration inputs and outputs port
//internal wire and internal reg
//implementation (Combination or sequential or mixes )
//endmodule
Example
module example_circuit( clk ,reset , a , y ) Module name
and ports
parameter width = 3 ; Parameter define
input wire clk ;
input wire reset ;
input wire [width-1 : 0] a ; Ports declaration
(direction, type, size)
output wire [width-1 : 0] y ;
reg [width-1 : 0] q ,r ; Internal
always @(posedge clk, posedge reset)
if (reset) begin
q <= 0;
r <= 0; Module
end else begin implementation
q <= a;
r <= q + 1;
end
assign y = q | r;
endmodule endmodule
Verilog Syntax
Verilog:
It is a Hardware Description Language (HDL) to describe digital electronic systems
at different abstract levels:
Behavior
Structural
Functional (Register-Transfer Level (RTL))
Verilog:
Behavior:
- Describes a system by concurrent algorithms (describes the behavior of a design without implying any specific internal architecture.)
Structural:
- Describes the design architecture in sufficient detail that a synthesis tool can construct the circuit.
- Any code that is synthesizable is called RTL code
Functional (Register-Transfer Level (RTL)):
-RTL is used to describe the behavior of the circuit from a register to the next one using the data flow through basic components like
mux, adders, ..etc.
- RTL is defined as any synthesizable code, any code that can be converted to hardware
Verilog primitive :
The Verilog language offers 26 built-in primitives.
&
|
~
^
~&
~|
~^
Logic gates
Verilog primitive :
Structural model Example:
module aoi_gate ( a1 , a2 , b1, b2 , o ) ;
input a1,a2,b1,b2;
output o;
//internal wire
wire o1,o2;
and g1(o1,a1,a2);
and g2(o2,b1,b2);
nor g3(o,o1,o2);
} implementation
describing its Structure
endmodule
Behavior model Example:
module aoi_gate ( a1 , a2 , b1, b2 , o ) ;
input a1,a2,b1,b2;
output o;
//internal wire
wire o1,o2;
assign o1=a1 & a2 ;
assign o2=b1 & b2 ;
assign o =o1 ~| o2 ;
} implementation
describing its Behavior
endmodule
Verilog Syntax :
Basic unit in Verilog is module.
Module starts with keyword “module”.
Sensitive
Module ends with keyword “endmodule”.
Verilog is case sensitive language. module half_adder(A, B, a, b);
input A, B;
output a, b;
xor my_xor(a,A,B);
NOTE: Case Sensitive A != a and my_and(b,A,B);
endmodule
Verilog Syntax : Parameter Width = 3
wire [Width -1 : 0] internal_wire ;
reg [ 2* Width - 1 : 0] internal_reg 2 ;
assign bus = {Width {1’b1}} ;
Parameters :
- Used for module instances configuration
-It is a constant value declared within the module structure.
-it used by different methods {size of number , size of wire and reg }
Verilog Syntax :
Port Declaration :
direction type size port_name
Directions
-input : input a; //should be wire
-output : output cout; //can be wire or reg
-inout : inout somepath; //should be wire
If direction is not mentioned, it will give an error!!
Type
-wire : input wire a;
-reg : output reg cout;
If type is not mentioned, default is wire
Verilog Syntax :
Port Declaration :
direction type size port_name
Size
- direction [MSB:LSB] //integer : integer
- input [3:0] x; //x is 4-bits, where MSB is of index 3
- input [5:3] y; // y is 3-bits
- input [2**2:3] q; //q is 2-bit, where MSB is of index 4
Note : If size is not mentioned, default is 1 bit
Verilog Syntax :
Port Declaration :
There are two methods for Declaration
module half_adder ( module half_adder(A, B, a, b);
input A, B; } Port Declaration input A, B;
}
output wire a, b ); output wire a, b;
Port Declaration
Verilog Syntax :
There are two methods
Comment : comment line or comment
it hasn't any effect on implementation code it is only for Explain some of lines
some of notes // Comment line
/* Line 1
Line 2
module half_adder ( Line 3
input A, B; */
output wire a, b );
// port Declartion
Verilog Syntax :
Semicolon:
Every definition and statement ends with a semicolon
Module names :
Can be lower or upper case or a mixture of the two, but are
case sensitive.
Keywords:
Keywords in Verilog are written in lower case.
-wire ,reg,parameter,
Verilog Syntax :
Keywords:
Keywords in Verilog are written in lower case.
{module,input,output,inout,wire,reg,assign,always,if,else,case,for,while,initial,parameter
,function,task,posedge,negedge,$display }
Keywords: above disable idt notif1 supply0
abs discipline idtmod or supply1
absdelay driver_update if output table
ac_stim edge ifnone parameter tan
acos else inf pmos tanh
acosh end initial posedge task
always endcase initial_step potential time
analog endconnectrules inout pow timer
analysis enddiscipline input primitive tran
and endfunction integer pull0 tranif0
asin endmodule join pull1 tranif1
asinh endnature laplace_nd pulldown transition
assign endprimitive laplace_np pullup tri
atan endspecify laplace_zd rcmos tri0
atan2 endtable laplace_zp real tri1
atanh endtask large realtime triand
begin event last_crossing reg trior
branch exclude limexp release trireg
buf exp ln repeat vectored
bufif0 final_step log rnmos wait
bufif1 flicker_noise macromodule rpmos wand
case flow max rtran weak0
casex for medium rtranif0 weak1
casez force min rtranif1 while
ceil forever module scalared white_noise
cmos fork nand sin wire
connectrules from nature sinh wor
cos function negedge slew wreal
cosh generate net_resolution small xnor
cross genvar nmos specify xor
ddt ground noise_table specparam zi_nd
deassign highz0 nor sqrt zi_np
default highz1 not strong0 zi_zd
defparam hypot notif0 strong1 zi_zp
Interactive Example
module half_adder (A, B, a, b); module half_adder (A, B, a, b);
input A, B; input A, B;
output a,b; output a , b;
assign a = A ^ B; xor my_xor(s,A,B);
assign b = A & B; and my_and(c,A,B);
endmodule endmodule
HALF ADDER BEHAVIORAL
Module name
module half_adder (A, B, a, b);
input A, B; Ports declaration
(direction, type, size)
output a,b;
assign a = A ^ B; Module
implementation
assign b = A & B;
endmodule
HALF ADDER STRUCTURE
Module name
module half_adder(A, B, a, b);
input A, B; Ports declaration
(direction, type, size)
output a , b;
xor my_xor(s,A,B); Module
and my_and(c,A,B); implementation
endmodule
