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Scheme of Valuation/Answer Key
(Scheme of evaluation (marks in brackets) and answers of problems/key)
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
FOURTH SEMESTER B.TECH DEGREE (S) EXAMINATION, JUNE 2023 (2019 Scheme)
Course Code: ECT206
Course Name: COMPUTER ARCHITECTURE AND MICROCONTROLLERS
Max. Marks: 100 Duration: 3 Hours
Note:-Appropriate share of marks can be given for the steps of the programs.
PART A
(Answer all questions; each question carries 3 marks) Marks

1 Explanation about accumulator and program counter 3

2 Execution of instruction is a two-step procedure. 3
In the first step, the instruction is fetched from memory. Explanation about use of
program counter. (1.5 Marks)
In the second step, the instruction is executed. Explanation about use of Instruction
register. (1.5 Marks)
3 Explanation about of use of timer in 8051(1 Mark), Timer 0 and 1 register. (1 Mark) 3
Explanation of TMOD register. (1 Marks)

4 SP is pointed towards RAM location 07. 3

MOV R6, #55h
PUSH 6. This instruction increments SP by 1(SP=08) and loads value 55 to RAM location
08.
POP 5. This instruction copies data from the location pointed by stack (SP=08) to R5 and
decrements SP by 1 (SP=07) Explanation with instructions-3 Marks
5 8 bit(AA) X 8(BB) bit multiplication 3
MOV R1,#0
MOV A,#0
MOV RO,#BBH
L1: ADD A,#0AAH
JNC L2

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INC R1
L2: DJNZ R0, L1 Result: R1 –(Higher 8 bit), R2-(Lower 8 bit)
MOV R2, A
Program and necessary comments/explanation=3 marks
6 Main program in C to toggle the bits of P0 continuously. -2 Marks 3
Delay function with any delay value-1 Mark
7 3

28800/3=9600 (baud rate) If FDH(-3 -decimal)is loaded in TH1

Explanation of baud rate setting as shown above-3 Marks

8 3

Diagram -1.5 Marks

Explanation about registers-1.5 Mark
9 3

Diagram- 1 Marks
Explanation – 2 Mark

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10 3

Diagram – 1 Marks
Explanation -2 Marks
Cache is implemented to make main memory appears faster to processor.
PART B
(Answer one full question from each module, each question carries 14 marks)

Module -1
11 a) 9

Diagram of Von Neumann and Harvard computer architecture-4 Marks

Explanation of Von Neumann and Harvard computer architecture-3 Marks
 In Von Neumann Memory holds both programs and data. Program consists of a
sequence of instructions. Instructions are executed in order they are stored in
memory.
 In Harvard Memory for data was separated from the memory for instruction.
Advantages and Disadvantages- 2 Marks
b) Explanation of shift and add method operation-2 Marks 5
Step by step explanation of one example using 8-bit multiplier and multiplicand - 3 Marks

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A3 A2 A1 A0
x B3 B2 B1 B0
A3B0 A2B0 A1B0 A0B0
A3B1 A2B1 A1B1 A0B1
A3B2 A2B2 A1B2 A0B2
+ A3B3 A2B3 A1B3 A0B3
P7 P6 P5 P4 P3 P2 P1 P0

12 a) 10

Timing Diagram-5 Marks

Explanation about the Buses and Control Signals - 5 Marks
Higher Order Address Bus, Lower Address/Data bus, ALE, RD, WR, IO/M
b) Explanation about purpose of program counter and stack pointer- 4 Marks 4
Module -2
13 a) PSW Format -1 Mark. Explanation of each bit -3 Marks 4

b) The various addressing modes of a microprocessor are 10

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(1) immediate
(2) register
(3) direct
(4) register indirect
(5) indexed
Explanation of above modes with examples for each. (2 Marks for each mode)
14 a) Write logical instructions in the format and explain the operation —ANL, ORL, XRL, 5
CPL, RL, RLC, RR, RRC –5 Marks
b) 9

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Explanation of Interrupts of 8051 and vector address – 4 Marks

IE register and its explanation-3 Marks
Concept of Interrupt priority and IP register- 2 Marks

Module -3
15 a) For crystal frequency of 11 MHz, one machine cycle is 1.09 μSec. 4
MOV A, #55H
L1: MOV P1, A
ACALL DELAY
CPL A
SJMP L1
Main program- 2 Marks
Delay program and calculation steps of delay subroutine- 2 Marks
b) LCD interface diagram- 3 Marks 10
Main program in C code with LCD initialisation steps and display function calls
- 3 Marks
LCD command and data - program steps- 3 Marks
Delay program- 1 Marks
16 a) C program that shows the ASCII to packed BCD conversion. 3 Marks 4

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Sending value to Port 2 – 1 Mark

b) Block diagram of 8051 interfacing with ADC- 3 Marks 10
Explanation about ADC pins, resolution, start of conversion, end of conversion-3 Marks
C Program to convert analog data to digital value – 4 Marks
Module -4
17 a) Characteristics of Mode 2 :- 8 bits auto reload; TR, TF bit explanation-2 Marks 4
Steps for program in mode 2 – 2 Marks

b) SBUF is 8it serial communication register -holds the data to be transmitted/received 10

SCON- 8bit serial control register

SCON and SBUF explanation- 4 Marks

Embedded C program with proper comments for serial transmission- 6 Marks

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18 a) 4

Explanation with diagram- 4 Marks

b) 10

Programming steps to transfer character bytes serially – 4 Marks

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8051 assembly language program for reading and transferring data serially with proper
comments - 6 Marks
(Marks can be given for those students who have written programs in
embedded C also.)

Module -5
19 a) 8

Mapping diagram- 3 Marks

Explanation- 5 Marks
 Blocks of cache are grouped into sets.
 Mapping function allows a block of the main memory to reside in any block of a
specific set.
 Divide the cache into 64 sets, with two blocks per set.
 Memory block 0, 64, 128...4032 (64 blocks) etc. map to block 0, and they can
occupy either of the two positions of a set. ( j modulo 64 )

b) Relevance of TLB -2 Marks 6

Associative mapped TLB organisation diagram- 2 Marks , Explanation – 2 Marks

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20 a) 5

Diagram 2 Marks
Explanation 3 Marks
• Memory management unit (MMU) translates virtual addresses into physical
addresses.
• If the desired data or instructions are in the main memory they are fetched as
described previously.
• If the desired data or instructions are not in the main memory, they must be
transferred from secondary storage to the main memory.
• MMU causes the operating system to bring the data from the secondary storage
into the main memory.

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b) 9

Block Diagram- 3Marks

Explanation of Programmed I/O -data register, Flag bit status-3 Marks
Explanation to input a sequence of data bytes and then storing it to memory- 3 Marks
*********

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