Control unit design and I/O

SUBSYSTEMS
module-3

By
Soumya Das
Asst prof. Dept of CSE
GCE Kalahandi.
 Control unit design
• Control Unit is the part of the computer’s central processing unit
(CPU), which directs the operation of the processor. It was included
as part of the Von Neumann Architecture by John von Neumann. It
is the responsibility of the Control Unit to tell the computer’s
memory, arithmetic/logic unit and input and output devices how to
respond to the instructions that have been sent to the processor. It
fetches internal instructions of the programs from the main
memory to the processor instruction register, and based on this
register contents, the control unit generates a control signal that
supervises the execution of these instructions.
• A control unit works by receiving input information to which it
converts into control signals, which are then sent to the central
processor. The computer’s processor then tells the attached
hardware what operations to perform. The functions that a control
unit performs are dependent on the type of CPU because the
architecture of CPU varies from manufacturer to manufacturer.
• Types of Control Unit –
There are two types of control units: Hardwired control unit and
Microprogrammable control unit.
• Hardwired Control Unit –
In the Hardwired control unit, the control signals that are important for instruction
execution control are generated by specially designed hardware logical circuits, in
which we can not modify the signal generation method without physical change of
the circuit structure. The operation code of an instruction contains the basic data
for control signal generation. In the instruction decoder, the operation code is
decoded. The instruction decoder constitutes a set of many decoders that decode
different fields of the instruction opcode.As a result, few output lines going out
from the instruction decoder obtains active signal values. These output lines are
connected to the inputs of the matrix that generates control signals for executive
units of the computer. This matrix implements logical combinations of the
decoded signals from the instruction opcode with the outputs from the matrix that
generates signals representing consecutive control unit states and with signals
coming from the outside of the processor, e.g. interrupt signals. The matrices are
built in a similar way as a programmable logic arrays.
2. Microprogrammable control unit –
The fundamental difference between these unit
structures and the structure of the hardwired control
unit is the existence of the control store that is used for
storing words containing encoded control signals
mandatory for instruction execution. In
microprogrammed control units, subsequent
instruction words are fetched into the instruction
register in a normal way. However, the operation code
of each instruction is not directly decoded to enable
immediate control signal generation but it comprises
the initial address of a microprogram contained in the
control store.
 I/O subsystem
• I/O Interface (Interrupt and DMA Mode)
• The method that is used to transfer information between internal storage
and external I/O devices is known as I/O interface. The CPU is interfaced
using special communication links by the peripherals connected to any
computer system. These communication links are used to resolve the
differences between CPU and peripheral. There exists special hardware
components between CPU and peripherals to supervise and synchronize
all the input and output transfers that are called interface units.
• Mode of Transfer:
• The binary information that is received from an external device is usually
stored in the memory unit. The information that is transferred from the
CPU to the external device is originated from the memory unit. CPU
merely processes the information but the source and target is always the
memory unit. Data transfer between CPU and the I/O devices may be
done in different modes.
• Data transfer to and from the peripherals may be done in any of the three
possible ways
Programmed I/O.
Interrupt- initiated I/O.
Direct memory access( DMA).
Programmed I/O: It is due to the result of the I/O instructions that are written in the computer
program. Each data item transfer is initiated by an instruction in the program. Usually the transfer is
from a CPU register and memory. In this case it requires constant monitoring by the CPU of the
peripheral devices.Example of Programmed I/O: In this case, the I/O device does not have direct
access to the memory unit. A transfer from I/O device to memory requires the execution of several
instructions by the CPU, including an input instruction to transfer the data from device to the CPU
and store instruction to transfer the data from CPU to memory. In programmed I/O, the CPU stays
in the program loop until the I/O unit indicates that it is ready for data transfer. This is a time
consuming process since it needlessly keeps the CPU busy. This situation can be avoided by using an
interrupt facility. This is discussed below.
Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy unnecessarily. This
situation can very well be avoided by using an interrupt driven method for data transfer. By using
interrupt facility and special commands to inform the interface to issue an interrupt request signal
whenever data is available from any device. In the meantime the CPU can proceed for any other
program execution. The interface meanwhile keeps monitoring the device. Whenever it is
determined that the device is ready for data transfer it initiates an interrupt request signal to the
computer. Upon detection of an external interrupt signal the CPU stops momentarily the task that it
was already performing, branches to the service program to process the I/O transfer, and then
return to the task it was originally performing.
• Direct Memory Access: The data transfer
between a fast storage media such as magnetic
disk and memory unit is limited by the speed of
the CPU. Thus we can allow the peripherals
directly communicate with each other using the
memory buses, removing the intervention of the
CPU. This type of data transfer technique is
known as DMA or direct memory access. During
DMA the CPU is idle and it has no control over
the memory buses. The DMA controller takes
over the buses to manage the transfer directly
between the I/O devices and the memory unit.
• Bus Request : It is used by the DMA controller to request the CPU to
relinquish the control of the buses.
• Bus Grant : It is activated by the CPU to Inform the external DMA
controller that the buses are in high impedance state and the requesting
DMA can take control of the buses. Once the DMA has taken the control of
the buses it transfers the data. This transfer can take place in many ways.
• Types of DMA transfer using DMA controller:
• Burst Transfer :
DMA returns the bus after complete data transfer. A register is used as a
byte count,
being decremented for each byte transfer, and upon the byte count
reaching zero, the DMAC will
release the bus. When the DMAC operates in burst mode, the CPU is
halted for the duration of the data
transfer.
• Steps involved are:
– Bus grant request time.
– Transfer the entire block of data at transfer rate of
device because the device is usually slow than the
speed at which the data can be transferred to
CPU.
– Release the control of the bus back to CPU
So, total time taken to transfer the N bytes
= Bus grant request time + (N) * (memory transfer
rate) + Bus release control time.
• Where,
• X µsec =data transfer time or preparation time
(words/block)
• Y µsec =memory cycle time or cycle time or
transfer time (words/block)
• % CPU idle (Blocked)=(Y/X+Y)*100
• % CPU Busy=(X/X+Y)*100
• Cyclic Stealing :
An alternative method in which DMA
controller transfers one word at a time after
which it must return the control of the buses
to the CPU. The CPU delays its operation only
for one memory cycle to allow the direct
memory I/O transfer to “steal” one memory
cycle.
Steps Involved are:
 – Buffer the byte into the buffer
– Inform the CPU that the device has 1 byte to transfer (i.e. bus
grant request)
– Transfer the byte (at system bus speed)
– Release the control of the bus back to CPU.
• Before moving on transfer next byte of data, device
performs step 1 again so that bus isn’t tied up and
the transfer won’t depend upon the transfer rate of device.
So, for 1 byte of transfer of data, time taken by using cycle
stealing mode (T).
= time required for bus grant + 1 bus cycle to transfer data
+ time required to release the bus, it will be
NxT
In cycle stealing mode we always follow pipelining
concept that when one byte is getting transferred then
Device is parallel preparing the next byte. “The fraction
of CPU time to the data transfer time” if asked then
cycle stealing mode is used.
Where,
• X µsec =data transfer time or preparation time
(words/block)
• Y µsec =memory cycle time or cycle time or transfer
time (words/block)
• % CPU idle (Blocked) =(Y/X)*100
• % CPU busy=(X/Y)*100
• Interleaved mode: In this technique , the
DMA controller takes over the system bus
when the microprocessor is not using it.An
alternate half cycle i.e. half cycle DMA + half
cycle processor.