UNIT-V
Sequential Circuits
The combinational circuit does not use any memory. Hence the previous state of input does not
have any effect on the present state of the circuit. But sequential circuit has memory so output
can vary based on input. This type of circuits uses previous input, output, clock and a memory
element.
Block diagram
Flip Flop
Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only at
particular instants of time and not continuously. Flip flop is said to be edge sensitive or edge
triggered rather than being level triggered like latches.
S-R Flip Flop
It is basically S-R latch using NAND gates with an additional enable input. It is also called as level
triggered SR-FF. For this circuit in output will take place if and only if the enable input (E) is
made active. In short this circuit will operate as an S-R latch if E= 1 but there is no change in the
output if E = 0.
Block Diagram
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Circuit Diagram
Truth Table
Operation
S.N. Condition Operation
If S = R = 0 then output of NAND gates 3 and 4 are forced to
S = R = 0 : No
1 become 1.
change
Hence R' and S' both will be equal to 1. Since S' and R' are the
input of the basic S-R latch using NAND gates, there will be no
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change in the state of outputs.
Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output of
2 S = 0, R = 1, E = 1 NAND-4 i.e. S' = 0.
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.
Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.
3 S = 1, R = 0, E = 1 Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0.
This is the reset condition.
As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both
4 S = 1, R = 1, E = 1 are 0 i.e. S' = R' = 0.
Hence the Race condition will occur in the basic NAND latch.
Master Slave JK Flip Flop
Master slave JK FF is a cascade of two S-R FF with feedback from the output of second to input
of first. Master is a positive level triggered. But due to the presence of the inverter in the clock
line, the slave will respond to the negative level. Hence when the clock = 1 (positive level) the
master is active and the slave is inactive. Whereas when clock = 0 (low level) the slave is active
and master is inactive.
Circuit Diagram
Truth Table
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Operation
S.N. Condition Operation
When clock = 0, the slave becomes active and master is
J = K = 0 (No inactive. But since the S and R inputs have not changed, the
1
change) slave outputs will also remain unchanged. Therefore outputs
will not change if J = K =0.
Clock = 1: Master active, slave inactive. Therefore outputs of
the master become Q1 = 0 and Q1 bar = 1. That means S = 0 and
R =1.
Clock = 0: Slave active, master inactive Therefore outputs of the
slave become Q = 0 and Q bar = 1.
J = 0 and K = 1 Again clock = 1: Master active, slave inactive. Therefore even
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(Reset) with the changed outputs Q = 0 and Q bar = 1 fed back to
master, its outputs will Q1 = 0 and Q1 bar = 1. That means S = 0
and R = 1.
Hence with clock = 0 and slave becoming active the outputs of
slave will remain Q = 0 and Q bar = 1. Thus we get a stable
output from the Master slave.
Clock = 1: Master active, slave inactive. Therefore outputs of
the master become Q1 = 1 and Q1 bar = 0. That means S = 1 and
R =0.
3 J = 1 and K = 0 (Set) Clock = 0: Slave active, master inactive Therefore outputs of the
slave become Q = 1 and Q bar = 0.
Again clock = 1: then it can be shown that the outputs of the
slave are stabilized to Q = 1 and Q bar = 0.
Clock = 1: Master active, slave inactive. Outputs of master will
4 J = K = 1 (Toggle)
toggle. So S and R also will be inverted.
Clock = 0: Slave active, master inactive. Outputs of slave will
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toggle.
These changed output are returned back to the master inputs.
But since clock = 0, the master is still inactive. So it does not
respond to these changed outputs. This avoids the multiple
toggling which leads to the race around condition. The master
slave flip flop will avoid the race around condition.
Delay Flip Flop / D Flip Flop
Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected
between S and R inputs. It has only one input. The input data is appearing at the output after
some time. Due to this data delay between i/p and o/p, it is called delay flip flop. S and R will be
the complements of each other due to NAND inverter. Hence S = R = 0 or S = R = 1,these input
condition will never appear. This problem is avoid by SR = 00 and SR = 1 conditions.
Block Diagram
Circuit Diagram
Truth Table
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Operation
S.N. Condition Operation
1 E=0 Latch is disabled. Hence is no change in output.
If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the
2 E = 1 and D = 0 present state, the next state is Qn+1 = 0 and Qn+1 bar = 1. This is
the reset condition.
if E = 1 and D = 1, then S = 1 and R = 0. This will set the latch and
3 E = 1 and D = 1
Qn+1 = 1 and Qn+1 bar = 0 irrespective of the present state.
Toggle Flip Flop / T Flip Flop
Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected together.
It has only input denoted by T is shown in the Symbol Diagram. The symbol for positive edge
triggered T flip flop is shown in the Block Diagram.
Symbol Diagram
Block Diagram
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Truth Table
Operation
S.N. Condition Operation
1 T = 0, J = K = 0 The output Q and Q bar won't change
output will toggle corresponding to every leading edge of clock
2 T = 1 ,J = K = 1
signal.
Flip flops are actually an application of logic gates. With the help of Boolean logic you can
create memory with them. Flip flops can also be considered as the most basic idea of a Random
Access Memory [RAM]. When a certain input value is given to them, they will be remembered
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and executed, if the logic gates are designed correctly. A higher application of flip flops is
helpful in designing better electronic circuits.
The most commonly used application of flip flops is in the implementation of a feedback circuit.
As a memory relies on the feedback concept, flip flops can be used to design it.
There are mainly four types of flip flops that are used in electronic circuits.
They are
1. The basic Flip Flop or S-R Flip Flop
2. Delay Flip Flop [D Flip Flop]
3. J-K Flip Flop
4. T Flip Flop
1. S-R Flip Flop
The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND gates.
These flip flops are also called S-R Latch.
S-R Flip Flop using NOR Gate
The design of such a flip flop includes two inputs, called the SET [S] and RESET [R]. There are
also two outputs, Q and Q’. The diagram and truth table is shown below.
From the diagram it is evident that the flip flop has mainly four states. They are
S=1, R=0—Q=1, Q’=0
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This state is also called the SET state.
S=0, R=1—Q=0, Q’=1
This state is known as the RESET state.
In both the states you can see that the outputs are just compliments of each other and that the
value of Q follows the value of S.
S=0, R=0—Q & Q’ = Remember
If both the values of S and R are switched to 0, then the circuit remembers the value of S and R
in their previous state.
S=1, R=1—Q=0, Q’=0 [Invalid]
This is an invalid state because the values of both Q and Q’ are 0. They are supposed to be
compliments of each other. Normally, this state must be avoided.
S-R Flip Flop using NAND Gate
The circuit of the S-R flip flop using NAND Gate and its truth table is shown below.
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Like the NOR Gate S-R flip flop, this one also has four states. They are
S=1, R=0—Q=0, Q’=1
This state is also called the SET state.
S=0, R=1—Q=1, Q’=0
This state is known as the RESET state.
In both the states you can see that the outputs are just compliments of each other and that the
value of Q follows the compliment value of S.
S=0, R=0—Q=1, & Q’ =1 [Invalid]
If both the values of S and R are switched to 0 it is an invalid state because the values of both Q
and Q’ are 1. They are supposed to be compliments of each other. Normally, this state must be
avoided.
S=1, R=1—Q & Q’= Remember
If both the values of S and R are switched to 1, then the circuit remembers the value of S and R
in their previous state.
Clocked S-R Flip Flop
It is also called a Gated S-R flip flop.
The problems with S-R flip flops using NOR and NAND gate is the invalid state. This problem can
be overcome by using a bistable SR flip-flop that can change outputs when certain invalid states
are met, regardless of the condition of either the Set or the Reset inputs. For this, a clocked S-R
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flip flop is designed by adding two AND gates to a basic NOR Gate flip flop. The circuit diagram
and truth table is shown below.
A clock pulse [CP] is given to the inputs of the AND Gate. When the value of the clock pulse is
’0′, the outputs of both the AND Gates remain ’0′. As soon as a pulse is given the value of CP
turns ’1′. This makes the values at S and R to pass through the NOR Gate flip flop. But when the
values of both S and R values turn ’1′, the HIGH value of CP causes both of them to turn to ’0′
for a short moment. As soon as the pulse is removed, the flip flop state becomes intermediate.
Thus either of the two states may be caused, and it depends on whether the set or reset input
of the flip-flop remains a ’1′ longer than the transition to ’0′ at the end of the pulse. Thus the
invalid states can be eliminated.
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2. D Flip Flop
The circuit diagram and truth table is given below.
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D flip flop is actually a slight modification of the above explained clocked SR flip-flop. From the
figure you can see that the D input is connected to the S input and the complement of the D
input is connected to the R input. The D input is passed on to the flip flop when the value of CP
is ’1′. When CP is HIGH, the flip flop moves to the SET state. If it is ’0′, the flip flop switches to
the CLEAR state.
3. J-K Flip Flop
The circuit diagram and truth-table of a J-K flip flop is shown below.
A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference is
that the intermediate state is more refined and precise than that of a S-R flip flop.
The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter J
stands for SET and the letter K stands for CLEAR.
When both the inputs J and K have a HIGH state, the flip-flop switch to the complement state.
So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1.
The circuit includes two 3-input AND gates. The output Q of the flip flop is returned back as a
feedback to the input of the AND along with other inputs like K and clock pulse [CP]. So, if the
value of CP is ’1′, the flip flop gets a CLEAR signal and with the condition that the value of Q was
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earlier 1. Similarly output Q’ of the flip flop is given as a feedback to the input of the AND along
with other inputs like J and clock pulse [CP]. So the output becomes SET when the value of CP is
1 only if the value of Q’ was earlier 1.
The output may be repeated in transitions once they have been complimented for J=K=1
because of the feedback connection in the JK flip-flop. This can be avoided by setting a time
duration lesser than the propagation delay through the flip-flop. The restriction on the pulse
width can be eliminated with a master-slave or edge-triggered construction.
4. T Flip Flop
This is a much simpler version of the J-K flip flop. Both the J and K inputs are connected
together and thus are also called a single input J-K flip flop. When clock pulse is given to the flip
flop, the output begins to toggle. Here also the restriction on the pulse width can be eliminated
with a master-slave or edge-triggered construction. Take a look at the circuit and truth table
below.
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Flip Flop Conversion:
For the conversion of one flip flop to another, a combinational circuit has to be designed first. If
a JK Flip Flop is required, the inputs are given to the combinational circuit and the output of the
combinational circuit is connected to the inputs of the actual flip flop. Thus, the output of the
actual flip flop is the output of the required flip flop. In this post, the following flip flop
conversions will be explained.
SR Flip Flop to JK Flip Flop
JK Flip Flop to SR Flip Flop
SR Flip Flop to D Flip Flop
D Flip Flop to SR Flip Flop
JK Flip Flop to T Flip Flop
JK Flip Flop to D Flip Flop
D Flip Flop to JK Flip Flop
SR Flip Flop to JK Flip Flop
As told earlier, J and K will be given as external inputs to S and R. As shown in the logic diagram
below, S and R will be the outputs of the combinational circuit.
The truth tables for the flip flop conversion are given below. The present state is represented
by Qp and Qp+1 is the next state to be obtained when the J and K inputs are applied.
For two inputs J and K, there will be eight possible combinations. For each combination of J, K
and Qp, the corresponding Qp+1 states are found. Qp+1 simply suggests the future values to be
obtained by the JK flip flop after the value of Qp. The table is then completed by writing the
values of S and R required to get each Qp+1 from the corresponding Qp. That is, the values of S
and R that are required to change the state of the flip flop from Qp to Qp+1 are written.
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JK Flip Flop to SR Flip Flop
This will be the reverse process of the above explained conversion. S and R will be the external
inputs to J and K. As shown in the logic diagram below, J and K will be the outputs of the
combinational circuit. Thus, the values of J and K have to be obtained in terms of S, R and Qp.
The logic diagram is shown below.
A conversion table is to be written using S, R, Qp, Qp+1, J and K. For two inputs, S and R, eight
combinations are made. For each combination, the corresponding Qp+1 outputs are found ut.
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The outputs for the combinations of S=1 and R=1 are not permitted for an SR flip flop. Thus the
outputs are considered invalid and the J and K values are taken as “don’t cares”.
SR Flip Flop to D Flip Flop
As shown in the figure, S and R are the actual inputs of the flip flop and D is the external input
of the flip flop. The four combinations, the logic diagram, conversion table, and the K-map for S
and R in terms of D and Qp are shown below.
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D Flip Flop to SR Flip Flop
D is the actual input of the flip flop and S and R are the external inputs. Eight possible
combinations are achieved from the external inputs S, R and Qp. But, since the combination of
S=1 and R=1 are invalid, the values of Qp+1 and D are considered as “don’t cares”. The logic
diagram showing the conversion from D to SR, and the K-map for D in terms of S, R and Qp are
shown below.
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JK Flip Flop to T Flip Flop
J and K are the actual inputs of the flip flop and T is taken as the external input for conversion.
Four combinations are produced with T and Qp. J and K are expressed in terms of T and Qp. The
conversion table, K-maps, and the logic diagram are given below.
JK Flip Flop to D Flip Flop
D is the external input and J and K are the actual inputs of the flip flop. D and Qp make four
combinations. J and K are expressed in terms of D and Qp. The four combination conversion
table, the K-maps for J and K in terms of D and Qp, and the logic diagram showing the
conversion from JK to D are given below.
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D Flip Flop to JK Flip Flop
In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K
and Qp make eight possible combinations, as shown in the conversion table below. D is
expressed in terms of J, K and Qp.
The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing the
conversion from D to JK are given in the figure below.
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Synchronous
Asynchronous
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