FEDL6242B-02

OKI Semiconductor MSM6242B

OKI Semiconductor FEDL6242B-02
Issue Date: Jun. 17, 2002

MSM6242B
DIRECT BUS CONNECTED CMOS REAL TIME CLOCK/CALENDAR

DESCRIPTION

The MSM6242B is a silicon gate CMOS Real (STANDARD PULSE) output utilizing Con-
Time Clock/Calendar for use in direct bus- trol Register inputs T0, T1 and the ITRPT/
connection Microprocessor/Microcomputer STND (INTERRUPT/STANDARD). Mask-
applications. An on-chip 32.768 kHz crystal ing of the interrupt output (STD.P) can be
oscillator time base is divided to provide ad- accomplished via the MASK bit. The
dressable 4-bit I/O data for SECONDS, MIN- MSM6242B can operate in a 12/24 hour for-
UTES, HOURS, DAY OF WEEK, DATE, mat and Leap Year timing is automatic.
MONTH and YEAR. Data access is controlled
by 4-bit address, chip selects (CS0, CS1), The MSM6242B normally operates from a 5 V
WRITE, READ, and ALE. Control Registers ±10% supply at –40 to +85°C. Battery backup
D, E and F provide for 30 SECOND error operation down to 2.0 V allows continuation
adjustment, INTERRUPT REQUEST (IRQ of time keeping when main power is off. The
FLAG) and BUSY status bits, clock STOP, MSM6242B is offered in a 18-pin plastic DIP
HOLD, and RESET FLAG bits, 4 selectable and a 24-pin plastic Small Outline package.
INTERRUPTS rates are available at the STD.P

FEATURES

DIRECT MICROPROCESSOR/MICROCONTROLLER BUS CONNECTION

TIME MONTH DATE YEAR DAY OF WEEK

23:59:59 12 31 80 7

• 4-bit data bus • 12/24 hour format

• 4-bit address bus • Auto leap year
• READ, WRITE, ALE and CHIP SELECT • ±30 second error correction
INPUTS • Single 5 V supply
• Status registers – IRQ and BUSY • Battery backup down to VDD = 2.0 V
• Selectable interrupt outputs – 1/64 • Low power dissipation:
second, 1 second, 1 minute, 1 hour 20 µW max at VDD = 2 V
• Interrupt masking 150 µW max at VDD = 5 V
• 32.768 kHz crystal controlled operation
• Package: 18-pin plastic DIP (DIP18-P-300-2.54) (MSM6242BRS)
24-pin plastic SOP (SOP24-P-430-1.27-K) (MSM6242BGS-K)

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FUNCTIONAL BLOCK DIAGRAM

XT
1 Hz
32.768 kHz XT OSC COUNTER

RESET STOP 30 ADJ HOLD BUSY

bit bit bit bit bit

30 sec
ADJ bit 24/12 bit
D3
D2
GATE

D1 S1 S10 MI1 MI10 H1 H10 W

D0

WR
GATE

RD D1 D10 MO1MO10 Y1 Y10

A3
GATE & LATCH

64 Hz STD.P
DECODER

A2 S1
1-sec carry
A1 S CD CE CF 1-min carry
A0 CF 1-hour carry
CS0
ALE

CS1 • S1 to W and W to Y10 are time counter register

• C0 to CF are control register

PIN CONFIGURATION

STD.P 1 18 VDD STD.P 1 24 VDD A0-A3: Address input

CS0 2 23 XT D0-D3: Data input/output
CS0 2 17 XT NC 3 22 XT CS0 , CS1: CHIP SELECTS 0,1
ALE 3 16 XT ALE 4 21 NC RD: READ enable
A0 A0 5 20 CS1 WR: WRITE enable
4 15 CS1
NC 6 19 D0 ALE: Address latch enable
A1 5 14 D0 Standard pulse output
A1 7 18 NC STD.P:
A2 6 13 D1 NC 8 17 NC XT, XT: XTAL oscillator input/output
A3 7 12 D2 A2 9 16 D1 VDD: +5 V supply
A3 10 15 D2 VSS: ground
RD 8 11 D3 RD 11 14 D3
GND 9 10 WR GND 12 13 WR

18-pin Plastic DIP 24-pin Plastic Small Outline

Package

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REGISTER TABLE

Address Input Data Count

Address Register Description
Input A3 A2 A1 A0 Name Value
D3 D2 D1 D0

0 0 0 0 0 S1 S8 S4 S2 S1 0 to 9 1-second digit register

1 0 0 0 1 S10 * S40 S20 S10 0 to 5 10-second digit register

2 0 0 1 0 MI1 mi8 mi4 mi2 mi1 0 to 9 1-minute digit register

3 0 0 1 1 MI10 * mi40 mi20 mi10 0 to 5 10-minute digit register

4 0 1 0 0 H1 h8 h4 h2 h1 0 to 9 1-hour digit register

PM/ 0 to 2 PM/AM, 10-hour digit

5 0 1 0 1 H10 * h20 h10
AM or 0 to 1 register

6 0 1 1 0 D1 d8 d4 d2 d1 0 to 9 1-day digit register

7 0 1 1 1 D10 * * d20 d10 0 to 3 10-day digit register

8 1 0 0 0 MO1 mo8 mo4 mo2 mo1 0 to 9 1-month digit register

9 1 0 0 1 MO10 * * * MO10 0 to 1 10-month digit register

A 1 0 1 0 Y1 y8 y4 y2 y1 0 to 9 1-year digit register

B 1 0 1 1 Y10 y80 y40 y20 y10 0 to 9 10-year digit register

C 1 1 0 0 W * w4 w2 w1 0 to 6 Week register

30
IRQ
D 1 1 0 1 CD sec. BUSY HOLD — Control Register D
FLAG
ADJ

ITRPT/
E 1 1 1 0 CE t1 t0 MASK — Control Register E
STND

F 1 1 1 1 CF TEST 24/12 STOP REST — Control Register F

REST = RESET
ITRPT/STND = INTERRUPT/STANDARD
Note 1) Bit * does not exist (unrecognized during a write and held at "0" during a read).
Note 2) Be sure to mask the AM/PM bit when processing 10's of hour's data.
Note 3) BUSY bit is read only. The IRQ FLAG bit can only be set to a "0". Setting the IRQ FLAG to a "1" is done by
hardware.
Note 4) PM at 1 and AM at 0 for PM/AM bit.

Figure 1 Register Table

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OSCILLATOR FREQUENCY DEVIATIONS

0 1
Ta = 25°C
0
∆f/f (PPM)

∆f/f (PPM)
–1
–50
–2

5V –3
2V
–100 –4
–60 –40 –20 0 20 40 60 80 0 1 2 3 4 5 6
Ta (°C) VDD (V)

Figure 2 Frequency Deviation (PPM) vs Temperature Figure 3 Frequency Deviation (PPM) vs Voltage

Note: 1. The graghs above showing frequency deviation vs temperature/voltage are primarily characteristic of the
MSM6242B with the oscillation circuit described below.

XT XT
Crystal: Type N0, P3 by kinseki (32.768 kHz)

CG CD CG, CD: 22 pF (Temperature Characteristics: 0)

VDD

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ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit

Power Supply Voltage VDD –0.3 to +7 V

Input Voltage VI Ta = 25°C –0.3 to VDD + 0.3 V

Output Voltage VO –0.3 to VDD + 0.3 V

Storage Temperature TSTG æ –55 to +150 °C

OPERATING CONDITIONS

Parameter Symbol Condition Rating Unit

Power Supply Voltage VDD — 4 to 6

V
Standby Supply Voltage VBAK — 2 to 6

Crystal Frequency f(XT) — 32.768 kHz

Operating Temperature TOP — –40 to +85 °C

DC Characteristics
(VDD = 5 V ±10%, Ta = –40 to +85)
Applicable
Parameter Symbol Condition Min. Typ. Max. Unit
Terminal
"H" Input Voltage VIH1 — 2.2 — — All input termin-
V
"L" Input Voltage VIL1 — — — 0.8 als except CS1, XT

Input terminals
Input Leak Current ILK1 — — 1/–1 other than
VI = VDD/0 V µA D0 to D3, XT

Input Leak Current ILK2 — — 10/–10 D0 to D3

"L" Output Voltage VOL1 IOL = 2.5 mA — — 0.4
V D0 to D3
"H" Output Voltage VOH IOH = –400 µA 2.4 — —
"L" Output Voltage VOL2 IOL = 2.5 mA — — 0.4 V
STD.P
OFF Leak Current IOFFLK V = VDD/0 V — — 10 µA
Input frequency All input
Input Capacitance CI — 5 — pF
1 MHz terminals
Current Con- f(xt) = VDD =
IDD1 — — 30
sumption 32.768 5V
kHz µA VDD
Current Con- VDD =
IDD2 CS1 ~~ 0 — — 10
sumption 2V

"H" Input Voltage VIH2 4/5VDD — —

VDD = 2 to 5.5 V V CS1
"L" Input Voltage VIL2 — — 1/5VDD
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SWITCHING CHARACTERISTICS
(1) WRITE mode (ALE = VDD)
(VDD = 5 V ±10% Ta = –40 to +85°C)
Parameter Symbol Condition Min. Max. Unit
CS1 Set up Time tC1S — 1000 —
CS1 Hold Time tC1H — 1000 —
Address Stable before
tAW — 20 —
WRITE
Address Stable after
tWA — 10 —
WRITE ns

WRITE Pulse Width tWW — 120 —

Data Set up Time tDS — 100 —

Data Hold Time tDH — 10 —

RD / WR Recovery Time tRCV — 60 —

CS1 VIH2 –
tC1S tC1H
A0 to A3 VIH1 –
CS0 VIL1 – VIH1 = 2.2 V
tAW tWW tWA VIL1 = 0.8 V
VIH1 –
WR tRCV VIH2 = 4/5VDD
tDS tDH VIL2 = 1/5VDD
D0 to D3 VIH1 –
(INPUT) VIL1 –

Figure 4 Write Cycle — (ALE = VDD)

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(2) WRITE mode (With use of ALE)

(VDD = 5 V ±10%, Ta = –40 to +85°C)

Parameter Symbol Condition Min. Max. Unit

CS1 Set up Time tC1S — 1000 —

Address Set up Time tAS — 25 —

Address Hold Time tAH — 25 —

ALE Pulse Width tAW — 40 —

ALE before WRITE tALW — — ns

10
WRITE Pulse Width tWW — 120 —

ALE after WRITE tWAL — 20 —

Data Set up Time tDS — 100 —
Data Hold Time tDH — 10 —

CS1 Hold Time tC1H — 1000 —

RD / WR Recovery Time tRCV — 60 —

tC1S
CS1 VIH2 –
tAS tC1H
A0 to A3 VIH1 –
CS0 VIL1 – VIH1 = 2.2 V
tAH VIL1 = 0.8 V
VIH1 –
ALE VIH2 = 4/5VDD
VIL1 –
tAW tALW tWAL VIL2 = 1/5VDD
VIH1 – tWW tRCV
WR
VIL1 – tDH
tDS
D0 to D3 VIH1 –
(INPUT) VIL1 –

Figure 5 Write Cycle — (With Use of ALE)

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(3) READ mode (ALE = VDD)

(VDD = 5 V ±10%, Ta = –40 to +85°C)

Parameter Symbol Condition Min. Max. Unit

CS1 Set up Time tC1S — 1000 —

CS1 Hold Time tC1H — 1000 —

Address Stable before
tAR — 20 —
READ
ns
Address Stable after
tRA — 0 —
READ

RD to Data tRD CL = 150 pF — 120

Data Hold tDR — 0 —

RD / WR Recovery Time tRCV — 60 —

CS1 VIH2 –
tC1S tAR tRA tC1H VIH1 = 2.2 V
A0 to A3 VIH1 –
VIL1 = 0.8 V
CS0 VIL1 – VIH2 = 4/5VDD
VIH1 – tRCV VIL2 = 1/5VDD
RD VIL1 – VOH = 2.2 V
tRD tDR
D0 to D3 VOH – VOL = 0.8 V
"Z"
(OUTPUT) VOL –

Figure 6 Read Cycle — (ALE = VDD)

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(4) READ mode (With use of ALE)
(VDD = 5 V ±10%, Ta = –40 to +85°C)
Parameter Symbol Condition Min. Max. Unit

CS1 Set up Time tC1S — 1000 —

Address Set up Time tAS — 25 —

Address Hold Time tAH — 25 —

ALE Pulse Width tAW — 40 —

— — ns
ALE before READ tALR 10

ALE after READ tRAL — 10 —

RD to Data tRD CL = 150 pF — 120

Data Hold tDR — 0 —

CS1 Hold Time tC1H — 1000 —

RD / WR Recovery Time tRCV — 60 —

CS1 VIH2 – tAH

tAS
tC1S tC1H
A0 to A3 VIH1 –
VIH1 = 2.2 V
CS0 VIL1 – VIL1 = 0.8 V
tAW
VIH1 – VIH2 = 4/5VDD
ALE
VIL1 – VIL2 = 1/5VDD
tALR tRAL
VIH1 – VOH = 2.2 V
RD tRCV
VIL1 – VOL = 0.8 V
tRD tDR
D0 to D3 VOH –
"Z"
(OUTPUT) VOL –

Figure 7 Read Cycle — (With Use of ALE)

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PIN DESCRIPTION

Pin No.
Name Description
RS GS-K
D0 14 19
Data Input/Output pins to be directly connected to a microcontroller bus for
D1 13 16
reading and writing of the clock/calendar's registers and control registers. D0 = LSB
D2 12 15 and D3 = MSB.
D3 11 14
A0 4 5 Address input pin for use by a microcomputer to select internal clock/calendar's
A1 5 7 registers and control registers for Read/Write operations (See Function Table
A2 6 9 Figure 1). Address input pins A0-A3 are used in combination with ALE for
A3 7 10 addressing registers.

Address Latch Enable pin. This pin enables writing of address data when ALE = 1
ALE 3 4 and CS0 = 0; address data is latched when ALE = 0 Microcontroller/Micro-
processors having an ALE output should connect to this pin; otherwise it should
be connected at VDD
Writing of data is performed by this pin.
WR 10 13 When CS1 = 1 and CS0 = 0, D0 to D3 data is written into the register at the rising
edge of WR.

Reading of register data is accomplished using this pin. When CS1 = 1, CS0 = 0
RD 8 11 and RD = 0, the data of this register is output to D0 to D3. If both RD and WR are
set at 0 simaltaneously, RD is to be inhibited.

CS0 2 2 Chip Select pins. These pins enable/disable ALE, RD and WR operation. CS0
and ALE work in combination with one another, while CS1 work independent
CS1 15 20 with ALE. CS1 must be connected to power failure detection as shown in Figure
18.

Output pin of N-CH OPEN DRAIN type. The output data is controlled by the
STD.P 1 1 D1 data content of CE register. This pin has a priority to CS0 and CS1.
Refer to Figure 9 and FUNCTIONAL DESCRIPTION OF REGISTERS.

XT 16 22 32.768 kHz crystal is to be connected to these pins.

When an external clock of 32.768 kHz is to be used for MSM6242B's oscillation
XT 17 23 source, either CMOS output or pull-up TTL output is to be input from XT, while
XT should be left open.
VDD 18 24 Power supply pin. +2 to +6 V power is to be applied to this pin.

GND 9 12 Ground pin.

RFB 5 MW VDD

XT
X'tal
C1 32.768 kHz STD.P OUTPUT

VDD or GND N-CH

C2 XT
C1 = C2 = 15 to 30 pF

The impedance of the crystal should be less than 30 kW

Figure 8 Oscillator Circuit Figure 9

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FUNCTIONAL DESCRIPTION OF REGISTERS

S1, S10, MI1, MI10, H1, H10, D1, D10, MO1, MO10, Y1, Y10, W

a) These are abbreviations for SECOND1, SECOND10, MINUTE1, MINUTE10, HOUR1,

HOUR10, DAY1, DAY10, MONTH1, MONTH10, YEAR1, YEAR10, and WEEK. These
values are in BCD notation.
b) All registers are logically positive. For example, (S8, S4, S2, S1) = 1001 which means 9
seconds.
c) If data is written which is out of the clock register data limits, it can result in erroneous clock
data being read back.
d) PM/AM, h20, h10
In the mode setting of 24-hour mode, PM/AM bit is ignored, while in the setting of 12-hour
mode h20 is to be set. Otherwise it causes a discrepancy. In reading out the PM/AM bit in
the 24-hour mode, it is continuously read out as 0. In reading out h20 bit in the 12-hour mode,
0 is written into this bit first, then it is continuously read out as 0 unless 1 is being written
into this bit.
e) Registers Y1, Y10, and Leap Year. The MSM6242B is designed exclusively for the Christian
Era and is capable of identifying a leap year automatically. The result of the setting of a non-
existant day of the month is shown in the following example: If the date February 29 or
November 31, 1985, was written, it would be changed automatically to March 1, or
December 1, 1985 at the exact time at which a carry pulse occurs for the day's digit.
f) The Register W data limits are 0 – 6 (Tabel 1 shows a possible data definition).

Table 1
w4 w2 w1 Day of Week
0 0 0 Sunday
0 0 1 Monday
0 1 0 Tuesday
0 1 1 Wednesday
1 0 0 Thursday
1 0 1 Friday
1 1 0 Saturday

Using HOLD Bit Not Using HOLD Bit

HOLD Bit ← 1 Read Register

First
S1 to W

Read BUSY Bit Data of

DATA ← S1 to W
Register
NO *
Busy Bit = 0?
Read Register
Second
HOLD Bit ← 0 S1 to W
YES

Write data into DATA1 = DATA2

* In the inside of LSI, the CLEAR of BUSY bit is performed when
or Read data from Idling Time HOLD bit = 0, but, if the period of HOLD bit = 0 is extermely
registers S1 to W narrow as compared with the period of HOLD bit = 1, there is
some case that the CLEAR of BUSY bit delays so that the NO
BUSY bit can be cleared by sampling HOLD bit = 0 at approximate DATA1 = DATA2
HOLD Bit ← 0 16 kHz. It is recommended to allow an idling time of 62 ms or more.
YES

Figure 10 Reading and Writing of Registers S1 to W

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Reading Method 2 when Not Using HOLD Bit Reading Method 3 when Not Using HOLD Bit
Initialization only at power ON Initialization only at power ON
• *1 and *2 represent the minimum required • *1 and *2 represent the minimum required
time out. time unit.
t1 *1 t1 *1
t0 *2 For example t0 *2 For example
ITRPT/STND 1 t1 = 0 and t0 = 1 when required to a ITRPT/STND 1 t1 = 0 and t0 = 1 when required to a
MASK 0 unit of second; MASK 0 unit of second;
t1 = 1 and t0 = 0 when required to a t1 = 1 and t0 = 0 when required to a
unit of minute; and CPU senses the unit of minute; and
t1 = 1 and t0 = 1 when required to a interruption. t1 = 1 and t0 = 1 when required to a
0 unit of hour; unit of hour;
IRQ FLAG
REGISTER CD READ

WAIT t
See Note NO
below Retried the reading, since a IRQ FLAG = 1
carry occurred during the The other IC causes
TIME DATA READ
operation. YES the interruption.
The interruption is caused by
REGISTER CD READ WAIT t this IC due to the occurrence
of a carry.

NO TIME DATA READ

IRQ FLAG = 0
(Note) Do this process within the following The IRQ FLAG is cleared to
time requirements by combination IRQ FLAG 0
YES read the next time data.
between t1 and t0:
Normal read
t1 = 0 and t0 = 1 . . . Less than 1 second END
t1 = 1 and t0 = 0 . . . Less than 1 minute
t1 = 1 and t0 = 1 . . . Less than 1 hour
t : 12 HOUR MODE . . . 35 µs
24 HOUR MODE . . . 3 µs

CD REGISTER (Control D Register)

a) HOLD (D0) – Setting this bit to a "1" inhibits the 1Hz clock to the S1 counter, at which
time the Busy status bit can be read. When Busy = 0, register's S1 to W
can be read or written. During this procedure if a carry occurs the S1
counter will be incremented by 1 second after HOLD = 0 (this condition
is guaranteed as long as HOLD = 1 does not exceed 1 second in
duration). If CS1 = 0 then HOLD = 0 irrespective of any condition.
b) BUSY (D1) – Status bit which shows the interface condition with microcontroller/
microprocessors. As for the method of writing into and reading from
S1 to W (address φ to C), refer to the flow chart described in Figure 10.
c) IRQ FLAG (D2) – This status bit corresponds to the output level of the STD.P output.
When STD.P = 0, then IRQ = 1; when STD.P = 1, then IRQ = 0. The IRQ
FLAG indicates that an interrupt has occurred to the microcomputer if
IRQ = 1. When D0 of register CE (MASK) = 0, then the STD.P output
changes according to the timing set by D3 (t1) and D2 (t0) of register E.
When D1 of register E (ITRPT/STND) = 1 (interrupt mode), the STD.P
output remains low until the IRQ FLAG is written to a "0". When IRQ
= 1 and timing for a new interrupt occurs, the new interrupt is ignored.
When ITRPT/STND = 0 (Standard Pulse Output mode) the STD.P
output remains low until either "0" is written to the IRQ FLAG;
otherwise, the IRQ FLAG automatically goes to "0" after 7.8125 ms.
When writing the HOLD or 30 second adjust bits of register D, it is
necessary to write the IRQ FLAG bit to a "1".
d) ±30 ADJ (D3) – When 30-second adjustment is necessary, a "1" is written to bit D3
during which time the internal clock registers should not be read from
or written to 125 µs after bit D3 = 1 it will automatically return to a "0",
and at that time reading or writing of registers can occur.

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START START

30-SECOND 30-SECOND
ADJ BIT = 1 ADJ BIT = 1

READ 30-SECOND
ADJ BIT NO
125 µs PASS?

NO YES
30-SECOND
ADJ BIT = 0?
END

YES (B)

END

(A)
Figure 11 Writing 30-Second Adj. bit (Two Ways A, B)

CE REGISTER (Control E Register)

a) MASK (D0) – This bit controls the STD.P output. When MASK = 1, then STD.P
= 1 (open); when MASK = 0, then STD.P = output mode. The
relationship between the MASK bit and STD.P output is shown
Figure 12.
b) ITRPT/STND (D1) – The ITRPT/STND input is used to switch the STD.P output
between its two modes of operation, interrupt and Standard
timing waveforms. When ITRPT/STND = 0 a fixed cycle wave-
form with a low-level pulse width of 7.8125 ms is present at the
STD.P output. At this time the MASK bit must equal 0, while the
period in either mode is determined by T0 (D2) and T1 (D3) of
Register E.
c) T0 (D2), T1 (D3) – These two bits determine the period of the STD.P output in both
interrupt and Fixed timing waveform modes. The tables below
show the timing associated with the T0, T1 inputs as well as their
relationship to INTRPT/STND and STD.P.

"INTERRUPT" DOES OUTPUT DOES NOT OCCUR

"1" "1" "1" "1"
NOT OCCUR BECAUSE AT LOW LEVEL BECAUSE
MASK BIT "0" "0" MASK BIT IS "1" MASK BIT "0" "0" MASK BIT IS "1"

OPEN STD.P OPEN

STD.P OUTPUT OUTPUT
LOW LEVEL LOW LEVEL
"INTERRUPT" TIMING OUTPUT TIMING
WRITE "0" INTO IRQ FLAG BIT AUTOMATIC RETURN
INTRT/STND BIT = "1" INTRT/STND BIT = "0"

Figure 12

Table 2
Duty CYCLE of "0" level when
t1 t0 Period
ITRPT/STND bit is "0".
0 0 1/64 second 1/2
0 1 1 second 1/128
1 0 1 minute 1/7680
1 1 1 hour 1/460800

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The timing of the STD.P output designated by T1 and T0 occurs the moment that a carry occurs to a clock digit.
(EXAMPLE) WHEN t1 = 1, t0 = 1 and MASK = 0.

PM12:00 PM1:00

OPEN
WHEN ITRPT/STND
BIT is "1" STD.P OUTPUT LOW LEVEL

WHEN ITRPT/STND OPEN

BIT is "0" LOW LEVEL

d) The low-level pulse width of the fixed cycle waveform (ITRPT/STND = 0) is 7.8125 ms
independent of T0/T1 inputs.
e) The fixed cycle waveform mode can be used for adjustment of the oscillator frequency time
base. (See Figure 14).
f) During ±30 second adjustment a carry can occur that will cause the STD.P output to go low
when T0/T1 = 1, 0 or 1, 1. However, when T1/T0 = 0, 0 and ITRPT/STND = 0, carry does
not occur and the STD.P output resumes normal operation.
g) The STD.P output is held (frozen) at the point at which STOP = 1 while ITRPT/STND = 0.
h) No STD.P output change occurs as a result of writing data to registers S1 to H1.

CF REGISTER (Control F Register)

a) REST (D0) – This bit is used to clear the clock's internal divider/counter of less than a
"RESET" second. When REST = 1, the counter is Reset for the duration of REST. In
order to release this counter from Reset, a "0" must be written to the REST
bit. If CSI = 0 then REST = 0 automatically.
b) STOP (D1) – The STOP FLAG Only inhibits carries into the 8192 Hz divider stage.
There may be up to 122 µs delay before timing starts or stops after
changing this flag; 1 = STOP/0 = RUN.

"1" "1" "1"

STOP BIT
"0" "0" "0" "0"

TIMING OF
"CARRY"
TO 8192 Hz
"CARRY" EXECUTED

"CARRY" NOT EXECUTED

Figure 13

c) 24/12 (D2) – This bit is for selection of 24/12 hour time modes. If D2 = 1–24 hour mode
is selected and the PM/AM bit is invalid. If D2 = 0–12 hour mode is
selected and the PM/AM bit is valid.
"24/HOUR/ Setting of the 24/12 hour bit is as follows:
12 HOUR" 1) REST bit = 1
2) 24/12 hour bit = 0 or 1
3) REST bit = 0
* REST bit must = 1 to write to the 24/12 hour bit.
d) TEST (D3) – When the TEST flag is a "1", the input to the SECONDS counter comes
from the counter/divider stage instead of the 15th divider stage. This
makes the SECONDS counter count at 5.4163 kHz instead of 1 Hz. When
TEST = 1 (Test Mode) the STOP & REST (Reset) flags do not inhibit internal
counting. When Hold = 1 during Test (Test = 1) internal counting is
inhibited; however, when the HOLD FLAG goes inactive (Hold = 0)
counter updating is not guaranteed.

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TYPICAL APPLICATION INTERFACE WITH MSM6242B AND

MICROCONTROLLERS

8085 MSM6242B 8085 MSM6242B

AD3 D3 A/D D3
AD2 D2 D2
AD1 D1 A8 to A12 D1
AD0 D0 D0

A3 A3
A2 A8 to A15 A2
DECODER

DECODER
A8 to A15
S1 A1 S1 A1
S0 A0 S0 A0
IO/M CS0 IO/M CS0

ALE ALE ALE

R1 R1
RD RD RD RD
R2 R2
WR WR WR WR

MEMORY MAPPED I/O MAPPED

Note : If 8085 does not enter into the state of HALT or HOLD during CS1 = "H" of
MSM6242B, R1 and R2 are not required.

Figure 15

Z80 MSM6242B MSC48 MSM6242B

D3 D3 BUS3 D3
D2 D2 BUS2 D2
D1 D1 BUS1 D1
D0 D0 BUS0 D0

A3 A3 A3
A2 A2 A2
A1 A1 A1
A0 A0 A0
DECODER DECODER

A4 to A15 CS0
VDD BUS 4-7 CS0
IORQ
ALE
MREQ G1 ALE ALE
RD RD RD RD
WR WR WR WR
G2
Note : It depends upon the switching
characterisrics decided by a X'tal used
for a Z80 that either of IORQ and MREQ
is used.

Figure 16 Figure 17

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TYPICAL APPLICATIONS — INTERFACE WITH MSM80C49

100 µF
3.9 V ★
4.7 µF (tantalum)
LITHIUM
BATTERY
★ (VFWD ≤ 0.3 V)
★ i.e. GERMANIUM
26 DIODE
18 kW 18
22 pF VDD VDD 17 15 pF
2 6 1
X1 INT SDT.P XT
11 3
ALE ALE
4.553 kHz 8 8 32.768 kHz
RD RD
3 10 10 16
X2 WR WR XT
22 pF MSM MSM 5 to 35 pF
80C49RS 6242BRS
12 4/14
DB0 A/D0
40 13 5/13
VCC DB1 A/D1
14 6/12
DB2 A/D2
15 7/11
DB3 A/D3
1 19 2
T0 DB7 CS0
38 15
P27 CS1
34 TR1 10 9
P17 VSS
kW
VSS 820
W
20

1.8 kW TR1 = 2N2907

1.8 kW
TR2 = 2N2907
1.8 kW TR2
★ TR3 = 2N2222
TR3
★ = 1N4148
220 W
2
RS232 3
1.8 kW 1.8 kW
DB25 7 ★
CONNECTOR 5
20 10 µF
220 W RS232
INTERFACE

5.2 V

Figure 18

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APPLICATION NOTE
1. Power Supply

START VDD = 5 V

STD.P
Power On
Output = undifined

TEST Bit ← 0
REST Bit ← 0 1* = 2*
24/12 Bit ← 1* (1 or 0)
STOP Bit ← 1

REST Bit ← 0
24/12 Bit ← 2*

Set the current

time

HOLD Bit ← 0
STOP Bit ← 0

Start Operation

2. Adjustment of Frequency

VDD
Screwdriver

18 17 16
VDD XT XT
CD, CF = (0, 0, 0, 0)
CE = (t1, t0, 0, 0)
SDT.P
VDD 1 2 3 d c

b 0.1 INCH
Frequency
counter 2 1
Eye

CD to CF are to be set at as described in the

figure and the capacitor is to be adjusted VDD XT XT
to meet the settle frequency of t0 and t1.
If the right oscillation can not be obtained,
1. Check the waveform of XT
1 ≥ 0.3 INCH
2. Check CD to CF content
a 2 ≥ 0.2 INCH
3. Check the noise
a b : INHIBIT

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3. CH1 (Chip Select)

VIH and VIL of CH1 has 3 functions.

a) To accomplish the interface with a microcontroller/microprocessor.
b) To inhibit the control bus, data bus and address bus and to reduce input gate pass
current in the stand-by mode.
c) To protect internal data when the mode is moved to and from standby mode.

To realize the above functions:

a) More than 4/5 VDD shoud be applied to the MSM6242B for the interface with a
microcontroller/microprocessor in 5 V operation.
b) In moving to the standby mode, 1/5 VDD should be applied so that all data buses should
be disabled. In the standby mode, approx. 0 V should be applied.
c) To and from the standby mode, obey following Timing chart.

To Standby Mode From Standby Mode

4 to 6 V
VDD 4V 4V
2 to 4 V 2 µs (MIN)
2 µs (MIN)
CS1 2V 4V
DD DD
5 1 5
V
5 DD

CS0 : H
or WR : H

4. Set SDT.P at Alarm Mode

Set alarm at 9:00

MASK BIT ← 0
ITRPT/STND BIT ← 1
t1, t0 ← 1
Start interruption
CPU Activation
Read Register CD

NO
D2 = 1?

YES

Read H10 and Repeat

H10 Cotent

NO
AM 9:00?

YES CPU HALT

or
CPU STAND BY

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TYPICAL APPLICATION — POWER SUPPLY CIRCUIT

RIPPLE
OPERATING: 20 mV P-P
VCE (SAT.) = 0.1 V
BATTERY BACKUP: 0 mV RL
+5 V +5 V
RL M
22 4.7 µF C 100 Ω
µF
VDD 4.7
µF VDD
51 kΩ 10 kΩ 100 Ω MSM B
6242B 1.5 ¥ 2 = 3 V MSM
1.2 ¥ 3 = 3.6 V 6242B
DRY CELLS
Ni – Cd VSS
VSS
10 kΩ

Figure 19 Figure 20

220 Ω
~ 6.5 V

VDD 100 Ω D1
MSM RL +5 V
4.7 µF
6242B
1.2 ¥ 3 = 3.6 V
VSS Ni – Cd

Figure 21
4.7 µF: tantalum

SUPPLEMENTARY DESCRIPTION

• When "0" is written to the IRQ FLAG bit, the IRQ FLAG bit is cleared. However, if "0" is
assigned to the IRQ FLAG bit when written to the other bits, the 30-sec ADJ bit and the
HOLD bit, the IRQ FLAG = 1 and was generated before the writing and IRQ FLG = 1
generated in a moment then will be cleared. To avoid this, always set "1" to the IRQ
FLAG unless "0" is written to it intentionally. By writing "1" to it, the IRQ FLAG bit
does not become "1".
• Since the IRQ FLAG bit becomes "1" in some cases when rewriting either of the t1, t0, or
ITRPT/STND bit of register CE, be sure to write "0" to the IRQ FLAG bit after writing to
make valid the IRQ FLAG = 1 to be generated after it.
* The relationship between SDT.P OUT and IRQ FLAG bit is shown below:

open
STD.P OUT "L"
IRQ FLAG bit 1
0
approx. 1.95 ms

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PACKAGE DIMENSIONS

(Unit : mm)

DIP18-P-300-2.54

Package material Epoxy resin

Lead frame material 42 alloy
Pin treatment Solder plating (≥5 mm)
Oki Electric Industry Co., Ltd. Package weight (g) 1.30 TYP.
Rev. No./Last Revised 2/Dec. 11, 1996

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(Unit : mm)
SOP24-P-430-1.27-K

Mirror finish

Package material Epoxy resin

Lead frame material 42 alloy
Pin treatment Solder plating (≥5 mm)
Oki Electric Industry Co., Ltd. Package weight (g) 0.58 TYP.
Rev. No./Last Revised 5/Oct. 13, 1998

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting
conditions (reflow method, temperature and times).

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REVISION HISTORY

Page
Document
Date Previous Current Description
No.
Edition Edition
— Apr. 1995 — — First edition
FEDL6242B-02 Jun. 17, 2002 1 1 Partially changed contents of "Package" of
the FEATURES section.
— 20 Added the Package Dimensions section and
— 21 the Contents.

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NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual

or unexpected operation resulting from misuse, neglect, improper installation, repair,
alteration or accident, improper handling, or unusual physical or electrical stress includ-
ing, but not limited to, exposure to parameters beyond the specified maximum ratings or
operation outside the specified operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual
property right, etc. is granted by us in connection with the use of the product and/or the
information and drawings contained herein. No responsibility is assumed by us for any
infringement of a third party’s right which may result from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and
reliability characteristics nor in any system or application where the failure of such system
or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and
life-support systems.

7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at
their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our
prior permission.

Copyright 2002 Oki Electric Industry Co., Ltd.

Printed in Japan
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