DRV8808

www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

COMBINATION MOTOR DRIVER WITH DC-DC CONVERTER

Check for Samples: DRV8808

1FEATURES • One Integrated LDO Regulator

2• Three DC Motor Drivers – Output Configurable With External Resistor
– Up to 2.5-A Current Chopping Network from 1 V to 2.5 V
– Low Typical ON Resistance (RDSON = 0.5 Ω – 550-mA Output Capability
at TJ = 25°C) • 7-V to 40-V Operating Range
• Three Integrated DC-DC Converters • Serial Interface for Communications
– ON/OFF Selectable Using CSELECT Pin • Thermally-Enhanced Surface-Mount Package
and Serial Interface 48-Pin HTSSOP With PowerPAD™
– Outputs Configurable With External (Eco-Friendly: RoHS and No Sb/Br )
Resistor Network From 1 V to 90% of VM • Power-Down Function (Deep-Sleep Mode)
Capability for All Three Channels • Reset Signal Output (Active Low)
– 1.35-A Output Capability for All Three • Reset (All Clear) Control Input
Channels

DESCRIPTION
The DRV8808 provides the integrated motor driver solution for printers. The chip has three full H-bridges and
three buck DC-DC converters.
The output driver block for each consists of N-channel power MOSFETs configured as full H-bridges to drive the
motor windings. The device can be configured to utilize internal or external current sense for winding current
control.
The SPI input pins are 3.3-V compatible and have 5-V-tolerant inputs.
The DRV8808 has three dc-dc switch-mode buck converters to generate a programmable output voltage from
1 V up to 90% of VM, with up to 1.35-A load current capability.
The device is configured using the CSELECT terminal at start up, and serial interface during run time.
An internal shutdown function is provided for overcurrent protection, short-circuit protection, undervoltage lockout,
and thermal shutdown. Also, the device has the reset function at power on, and the input on nReset pin.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

BLOCK DIAGRAM
VM

Cstorage 0.1 µF
VM
Cbkt
0.1 µF
A_CONT CSELECT Th_out VCP CP2 CP1

Temperature
VM
Sensor: To High-Side
OD_A Pre-TSD or Voltage Gate Drive
Tsens (Analog) A+
Charge
Vout1 Pump
DC-DC
Converter Motor Drive VM
Thermal Output DC
Ch-A Motor
Shut Down Control A
FB_A A–

RSA Optional

VM
OD_B
B+
Vout2
DC-DC
Converter
Motor Drive VM DC
Ch-B
VM Output Motor
Control B
FB_B B–
Regulator
Voltage Internal
Supervisory Supply Optional
Predrive, RSB
OD_C Latch Registers, VM
and
Vout3
DC-DC Control C+
Converter Circuitry
Ch-C
Motor Drive VM DC
Output Motor
FB_C
Control C
nReset C–
nORT
Optional
RSC
LOGIC_OUT

LDO IN
LDO OUT LDO
Regulator
LDO FB

nSLEEP
nWAKEUP

Serial Interface
GND V3p3

0.1 µF

Enable_A Enable_B Enable_C Phase_A Phase_B Phase_C

STROBE CLK DATA GND GND

2 Copyright © 2009–2011, Texas Instruments Incorporated

 DRV8808
www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

DCA PACKAGE
(TOP VIEW)

OD_A 1 48 FB_A
OD_C 2 47 GND
GND 3 46 COA
FB_C 4 45 CP2
CSELECT 5 44 VCP
TH_OUT 6 43 VM
LOGIC_OUT 7 42 C–
nORT 8 41 RSC/GND
ENABLE_A/STROBE 9 40 RSC/GND
PHASE_A/CLK 10 39 C+
ENABLE_B 11 38 VM
PHASE_B 12 37 VM
ENABLE_C 13 36 B–
PHASE_C/DATA 14 35 RSB/GND
A_CONT 15 34 RSB/GND
NC 16 33 B+
V3P3 17 32 VM
nSLEEP 18 31 A+
nRESET 19 30 RSA/GND
nWAKEUP 20 29 RSA/GND
VLDO_OUT 21 28 A–
VLDO_FB 22 27 VM
VLDO_IN 23 26 GND
FB_B 24 25 OD_B

TERMINAL FUNCTIONS
TERMINAL SHUNT
I/O PU/PD DESCRIPTION
NO. NAME R
1 OD_A O Output for DC-DC switch mode regulator A
2 OD_C O Output for DC-DC switch mode regulator C
3 GND - Ground
4 FB_C I Feedback signal for DC-DC converter C
5 CSELECT I Up 200k DC-DC converter startup selector
6 TH_OUT O Temperature warning output (open drain)
7 LOGIC_OUT O Information monitoring output (open drain)
8 nORT O Reset output (open drain)
9 ENA / STB I Down 100k Enable input for DC motor A control / SPI STROBE
10 PHA / CLK I Down 100k Phase input for DC motor A control / SPI CLOCK
11 ENB I Down 100k Enable input for DC motor B control
12 PHB I Down 100k Phase input for DC motor B control
13 ENC I Down 100k Enable input for DC motor C control
14 PHC / DATA I Down 100k Phase input for DC motor C control / SPI DATA
15 A_CONT I Down 100k DC-DC A converter control (L = Enable)
16 NC NC Do not connect
17 V3p3 O Bypass for internal 3.3-V regulator
18 nSLEEP I Down 100k Enable/disable, SPI selector
19 nReset I Up 200k Reset input (L: reset, H/open: normal operation)
20 nWAKEUP I Up 200k Wake-up pin for DeepSleep mode (L = WAKEUP)
21 VLDO_OUT O LDO voltage regulator output

Copyright © 2009–2011, Texas Instruments Incorporated 3

DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

TERMINAL FUNCTIONS (continued)

TERMINAL SHUNT
I/O PU/PD DESCRIPTION
NO. NAME R
22 VLDO_FB I LDO voltage regulator feed back
23 VLDO_IN I LDO voltage regulator input
24 FB_B I Feedback signal for DC-DC converter B
25 OD_B O Output for DC-DC switch mode regulator B
26 GND - Ground
27 VM - Voltage supply for motors and regulators
28 A- O Motor drive output for winding A-
29 RSKA / GND I Motor drive current sensing resistor A / GND Kelvin
30 RSA / GND O Motor drive current sensing resistor A / GND power
31 A+ O Motor drive output for winding A+
32 VM - Voltage supply for motors and regulators
33 B+ O Motor drive output for winding B+
34 RSKB / GND I Motor drive current sensing resistor B / GND Kelvin
35 RSB / GND O Motor drive current sensing resistor B / GND power
36 B- O Motor drive output for winding B-
37 VM - Voltage supply for motors and regulators
38 VM - Voltage supply for motors and regulators
39 C+ O Motor drive output for winding C+
40 RSKC / GND I Motor drive current sensing resistor C / GND Kelvin
41 RSC / GND O Motor drive current sensing resistor C / GND power
42 C- O Motor drive output for winding C-
43 VM - Voltage supply for motors and regulators
44 VCP O Charge pump output
45 CP2 O Charge pump bucket capacitor output (high side)
46 CP1 O Charge pump bucket capacitor output (low side)
47 GND - Ground
48 FB_A I Feedback signal for DC-DC converter A

4 Copyright © 2009–2011, Texas Instruments Incorporated

 DRV8808
www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

Internal
3.3-V
Supply
200 kW
(±40%)
1) Pin open, 3 V to 3.3 V
A /OFF, B /ON, C /ON
2) External R to GND (200 kW ± 10%)
# CSELECT 1.3 V to 2 V Soft-Start
A /OFF, B /ON, C /OFF Control
3) GND, 0 V to 0.3 V
A /OFF, B /OFF, C /OFF

GND

# Enable_X
# Phase _X
Hysteresis Serial Interface
# nSLEEP
# A_CONT 100 kW
(±30%)

GND GND

Internal
3.3-V
Supply
200 kW
(±40%)

# nWAKEUP Hysteresis
Reset Control
# nReset Deglitch

Deglitch is for nReset only.

nReset pulled up to 3.3 V internal.
GND nWAKEUP pulled up to 8 V internal.

Figure 1. Input Pin Configuration

External
3.3-V
Supply

1 kW
# TH_OUT (External)
# LOGIC_OUT
# nORT

GND

Figure 2. Open-Drain Output Pin Configuration

Copyright © 2009–2011, Texas Instruments Incorporated 5

DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
MAX UNIT
VM Supply voltage 40 V
(2)
Logic input voltage range, serial I/F, A_CONT, nReset, etc. –0.3 to 5.5 V
TH_OUT, nORT, LOGIC_OUT, CSELECT –0.3 to 3.6 V
nWAKEUP –0.3 to 8 V
Continuous total power dissipation (in case θJA = 20°C/W) 4 W
Continuous motor-drive output current for each H-bridge (100 ms) 2.5 A
Continuous dc-dc converter output current (3) 1.35 A
TJ Operating junction temperature (1 hour) 190 °C
Tstg Storage temperature range –65 to 150 °C
Lead temperature 1.6 mm (1/16 in) from case for 10 s 260 °C
ESD levels on every pin, Human-Body Model (HBM) 2 kV

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The negative spike less than –5 V and narrower than 50-ns width should not cause any problem.
(3) May shut down due to regulator OCP.

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT
Supply voltage range, VM for motor control 18 27 38 V
Supply voltage range for dc-dc converter (VM) 7 27 38 V
Operating ambient temperature range –10 85 °C
Operating junction temperature range 0 135 °C

ELECTRICAL CHARACTERISTICS
TJ = 0°C to 135°C, VM = 7 V to 38 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply (Sleep) Current
ISLEEP1 Supply (sleep) current 1 nSLEEP = L, dc-dc all off 3 5.5 mA
ISLEEP2 Supply (sleep) current 2 nSLEEP = L, VM = 8 V, 6 8 mA
Regulators enabled No load
ISLEEP3 Supply (sleep) current 3 nSLEEP = L, VM = 38 V, 6 8 mA
Regulators enabled No load
IDEEP_SL Supply (deep sleep) current (1) VM = 38 V 0.7 1 mA
Digital Interface Circuit
VIH Digital high-level input voltage Digital inputs 2 3.6 V
IIH Digital high-level input current Digital inputs 100 μA
VIL Digital low-level input voltage Digital inputs 0.8 V
IIL Digital low-level input current Digital inputs 100 μA
Vhys Digital input hysteresis Digital inputs 0.45 V
Tdeg_nReset nReset input deglitch time 2.5 7.5 μs
Tfilt_ACONT A_CONT filter time (2) 30 70 μs
Charge-pump VCP (CP = 0.1 μF to 0.47 μF, Cblk = 0.01 μF ±20%)
VO(CP) Output voltage ILOAD = 0 mA, VM > 15 V VM + 10 VM + 13 V
f(CP) Switching frequency 1.6 MHz

(1) Deep Sleep shuts down majority of the device and runs minimal circuits (internal bias circuits and the nWAKEUP pin). Deep Sleep is
entered by writing 1 to Setup Register, Bank 1, Bit 11. Device is restarted by pulling nWAKEUP pin low or power cycling VM. Deep
Sleep functionality only available for VM > VthVM+.
(2) A_CONT is filtered for both high and low levels.
6 Copyright © 2009–2011, Texas Instruments Incorporated
 DRV8808
www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

ELECTRICAL CHARACTERISTICS (continued)

TJ = 0°C to 135°C, VM = 7 V to 38 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tstart Start-up time CStorage = 0.1 μF, VM ≥ 15 V 0.5 2 ms
V3p3 Output
V3p3 Output voltage (3) 3 3.3 3.6 V
Cbypass Output capacitor 0.08 0.1 10 μF
Internal Clock OSCi
fOSCi System clock rrequency 5.76 6.4 7.04 MHz
CSELECT for DC-DC Startup Selection
VCS0 dc-dc all off 0 0.3 V
VCS1 Turn ON ODB Pull down by external 200-kΩ resistor 1.3 2 V
VCS2 Turn ON ODB then ODC As pin open 3 3.6 V
(4) (5) (6)
VLDO Regulator
VLDOIN LDO input voltage 3 3.6 V
VLDOFB Feedback voltage 1 V
1 V ≤ VLDOOUT ≤ 1.8 V ±5 %
VLDOOUT Output voltage range
1.8 V ≤ VLDOOUT ≤ 2.5 V ±3
IOUT Load capability 500 mA
IOCP OCP current 725 1100 mA
tIdeg OCP deglitch 3 8 13 μs
% to nominal Voutx detected at VFB
Vovp Overvoltage protection 25 30 35 %
(VFB increasing)
% to nominal Voutx detected at VFB
Vuvp Undervoltage protection –25 –30 –35 %
(VFB decreasing)
tVdeg UVP/OVP deglitch time 3 8 13 μs
CL1 Electrolytic load capacitance 27 120 μF
CESR1 Load bypass configuration 1 ESR of load capacitance 0.05 2 Ω
CC1 Ceramic load capacitance 0 0.4 μF
CL2 Electrolytic load capacitance 80 100 120 μF
CESR2 Load bypass configuration 2 ESR of load capacitance 0.05 0.2 Ω
CC2 Ceramic load capacitance 0 3 μF
Three, DC-DC Converter
VM OPE_X Operating supply voltage range IO < 0.6 A Vth VM- < VM < 7 V 0.8 x V
ratio to VOUT VM
20 V < VM < 38 V 0.9 x
VM
ODx Regulator output voltage 20 V < VM < 40 V 0℃ < TJ < 125℃ -3 VO 3 %
125℃ < TJ < 135℃ -4 VO 4
6.5 V < VM < 20 V -5 VO 5
VM = 7 V, VO = 5.5 V -5 VO 5
VM = 7 V, VO = 1 V 0℃ < TJ < 125℃ -3 VO 3
125℃ < TJ < 135℃ -4 VO 4
VthVM- < VM < 6.5 V , VO ≤ 3.3 V -5 VO 5
FBx FBx pin voltage 1 V
IO ODx Output current (DC) VM > 15 V 1.35 A
IO ODx2 Output current (DC) at low VM VM = 7 V, VO = 5.5 V 0.6 A

(3) V3p3 bypass pin is not meant to be used as a supply.

(4) LDO can be bypassed by either load configuration 1 or 2.
(5) Typical values for external components should be chosen such that when the tolerance is added to the typical, the values remain
between the maximum and minimum specifications listed.
(6) When LDO is not used, recommend connecting VLDO_IN to GND, VLDO_OUT to GND, and VLDO_FB to FB_B.
Copyright © 2009–2011, Texas Instruments Incorporated 7
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

TJ = 0°C to 135°C, VM = 7 V to 38 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IO ODx3 Output current (DC) at low VM VM = 7 V, VO = 3.3 V 1.2 A
RDSON (7) FET on-resistance at 0.8 A for TJ = 70 °C 0.85 1.05 Ω
OD_x VM > 15 V
TJ = 135 °C 1 1.2
L Inductor VOUT = 1.0 V 150 μH
VOUT ≥ 3.3 V 330
C Capacitor VOUT = 1.0 V 270 330 μF
VOUT ≥ 3.3 V 220
Three DC-DC Converter Protection
IO DD ODx Overcurrent detect for OD_x Peak current in each ON cycle 1.35 2.7 A
source
tODXdeg Cycle by cycle Idetect deglitch 100 200 400 ns
tODXSD dc-dc shutdown filter Number of consecutive cycles with Idetect 4 chop
cycles
Vovpx Overvoltage protection % to nominal Voutx detected at VFB 25 30 35 %
(VFB increasing)
Vuvpx Undervoltage protection % to nominal Voutx detected at VFB –25 –30 –35 %
(VFB decreasing)
tVXdeg UVP/OVP deglitch time 3 8 13 μs
tsst Start-up time with soft start 56 ms
Vstover Start-up overshoot Ratio to Vo 3 %
VM Supervisory (8) (9)

VthVM– nORT, for VM low threshold VM decreasing 4.5 5 6 V

VthVM+ nORT, for VM high threshold VM increasing 5.5 6 6.79 V
VthVMh nORT, for VM detect hysteresis VthVM+ – VthVM– 0.5 1 V
(10)
VthVM2 For motor driver off 15 V
tVMfilt Vth VM monitor filtering time For Vth VM detect 4 30 μs
tVM2filt Vth VM2 monitor filtering time For Vth VM2 detect 30 60 ms
(11) (12)
Thermal Shutdown: TSD
TTSD Thermal shutdown set points 150 170 190 °C
tTSDdeg TSD deglitch time 30 60 90 μs
Temperature Warning: Pre-TSD (13) (12)

PreTSD Temperature warning Assert at TH_OUT pin 115 135 155 °C

Open-drain outputs (nORT, Logic_OUT, TH_OUT)
VOH High-state voltage RL = 1 kΩ to 3.3 V 3 V
(14)
VOL Low-state voltage RL = 1 kΩ to 3.3 V 0.3 V
IOL (14) Low-state sink current Vo = 0.25 V 2 mA
tr (15) Rise time 10% to 90% 1 μs
tf (15) Fall time 90% to 10% 50 ns

(7) RDSON at T = 135°C guaranteed by characterization. Production test will be done at T = 25°C/70°C.
(8) VM must be VM > VthVM+ to start up internal dc-dc converter.
(9) When VM goes down below VthVM+, the VUVPx (undervoltage protection in dc-dc) are masked. The dc-dc converter is shut off by nORT
assertion at VthVM –.
(10) No nORT assertion to VthVM2 detection.
(11) TSD does not need thermal hysteresis.
(12) Parametric guaranteed by characterization. Not tested in production.
(13) PreTSD does not need thermal hysteresis.
(14) Production test only measures Vol and Iol to ensure timing.
(15) tr and tf dominated by external capacitance, pullup resistance, and open-drain NMOS RDSON.

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 DRV8808
www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

ELECTRICAL CHARACTERISTICS (continued)

TJ = 0°C to 135°C, VM = 7 V to 38 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(16) (17)
nORT Delay: Startup Sequence
Tord1 nORT delay 1 Reset deassertion from VthVM+ < VM, for 200 300 390 ms
DC/DC wake up failing
Tord3 dc-dc turn on delay From one dc-dc wake up to following dc-dc to 5 10 15 ms
go soft-start sequence
Tord4 nORT delay 4 Reset deassertion from 2nd dc-dc wake up 60 120 180 ms
nReset Input (16)
Treset nReset assertion to nORT nReset falling to nORT failing 5 10 μs
assertion delay
(18)
H-Bridge Drivers (OUTX+ and OUTX–) Condition: VM = 15 V to 38 V
IOUT1(max) Peak output current 1 Less than 500-ns period 6.8 A
IOUT2(max) Peak output current 2 Less than 100-ms period 2.42 A
RDSON FET ON resistance at 0.8 A TJ = 70°C 0.55 0.65 Ω
TJ = 135°C 0.7 0.85
ICEX Output leakage current VOUTX = 0 V or 10 10 μA
IOC Motor Motor overcurrent threshold for 3 8 A
each H-bridge (18)
Fchop Motor chopping frequency = 90 100 110 kHz
FOSCM/8
DC Motor Drivers
tr Rise time VM = 35 V 50 200 nS
20% to 80%
tf Fall time VM = 35 V 50 200 nS
20% to 80%
tPDOFF Enable or strobe detection 50 150 400 nS
to sink or source gate OFF delay
tCOD Crossover delay time to prevent 100 (19) 600 1000 nS
shoot through
tPDON Enable or strobe detection 750 nS
to sink or source gate ON delay
tIdeg MISD BLANK [00] (20) 1.80 2.25 2.95 μs
(21)
[01] 1.20 1.50 2.30
(22)
[10] 2.35 3.00 3.65
(23)
[11] 2.95 3.75 4.30
(24)
Tblank TBLANK [00] 3.05 3.45 5.50 μs
(25)
[01] 1.90 2.20 4.15
(26)
[10] 4.15 4.70 6.75
[11] (27) 5.30 5.95 8.25

(16) This includes asynchronous timing deviation between the event to the timer clock.
(17) nORT assertion delay is configurable and defined in the serial register section.
(18) When the overcurrent is detected, all the H-bridges are shut down and assert nORT per shutdown configuration.
(19) tCOD, Pminp, and Pmine not production tested.
(20) 3 to 4 periods Fosc/4 + 1 Fosc
(21) 2 to 3 periods Fosc/4 + 1 Fosc
(22) 4 to 5 periods Fosc/4 + 1 Fosc
(23) 5 to 6 periods Fosc/4 + 1 Fosc
(24) 3 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
(25) 2 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
(26) 4 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
(27) 5 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
Copyright © 2009–2011, Texas Instruments Incorporated 9
DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

TJ = 0°C to 135°C, VM = 7 V to 38 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRSTRIP Internal current trip 00 1.18 1.4 1.62 A
01 1.48 1.7 1.92
10 1.68 1.9 2.12
11 1.98 2.2 2.42
External resistor sense voltage 00 165 185 205 mV
trip threshold
01 190 210 230
10 240 260 280
11 290 310 330
(19)
Pminp Minimum pulse width (phase) 1 μs
(19)
Pmine Minimum pulse width (enable) 1 μs
(28)
Serial Interface
f(CLK) Clock frequency 25 MHz
twh(CLK) Minimum high-level pulse width 10 ns
twl(CLK) Minimum low-level pulse width 10 ns
tdcs Setup time, DATA to CLK↓ 10 ns
tdch Hold time, CLK↓ to DATA 10 ns
tdss Setup time, DATA to STROBE↑ 10 ns
tdsh Hold time, STROBE↑ to DATA 10 ns
tcss Setup time, CLK↓ to STROBE↑ 20 (29) ns
tcsh Hold time, STROBE↑ to CLK↓ 20 (29) ns
(30)
tnss Setup time, nSLEEP↓ to 4 μs
STROBE↑
tnsh Hold time, STROBE↑ to 10 ns
nSLEEP↑
tw(STRB) Minimum strobe pulse width 20 ns
(31)
Serial Interface: ID Monitor Function at Logic_out Pin, Extended Setup Mode
tODL 0 data output delay bit 3 to 0 From strobe rise to Logic_out 4000 ns
(ext-setup) = (1100) (1 kΩ to external 3.3 V)
tODH 1 data output delay bit 3 to 0 4000 ns
(ext-setup) = (1111)

(28) Serial interface timing will not be tested parametrically in production.

(29) DATA value at STROBE is address bit for Setup and Extended Setup register so setup and hold times apply to DATA relative to
STROBE. CLK and DATA also require setup and hold times relative to each other. Therefore, CLK and STROBE setup and hold timing
is the summation of both.
(30) Internal filter on nSLEEP to STROBE drives this specification.
(31) Serial interface timing will not be tested parametrically in production.

Serial Interface
The device has a serial interface port (SIP) circuit block to control dc motor H-bridges, dc-dc regulators, and
other functions, such as blanking time, OFF time, etc. Since the SIP shares its three lines with three of the motor
control signals, the SIP is only available when nSLEEP is low.

Table 1. Serial Interface

nSLEEP PIN 9 PIN 10 PIN 14 SIP FUNCTIONALITY
L STB CLK DATA Yes
H ENA PHA PHC No

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Sixteen-bit serial data is shifted least significant bit (LSB) first into the serial data input (DATA) shift register on
the falling edge of the serial clock (CLK). After 16-bit data transfer, the strobe signal (Strobe) rising edge latches
all the shifted data. During the data transferring, Strobe voltage level is ok with L level or H level.

DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

CLK

Strobe

NOTE
During startup (VM rising), nSLEEP input is set HI, suppressing false data latching caused
by a rising edge on the STB signal. nSLEEP will remain HI until nORT is released (120 ms
after dc-dc regulators come up).

Setup Mode, Extended Setup Mode, Power-Down Mode

The motor output mode is configured through the SIP (DATA, CLK and STROBE) when nSLEEP = L. After set
up, the nSLEEP pin must be pulled high for normal motor drive control. The value on the DATA line at the
positive edge of STROBE when nSLEEP is low, selects whether the data is written to the Setup or Extended
Setup registers. Setup is selected for DATA = L; Extended Setup is selected for DATA = H.
The condition, which the device requires for set up (initialize), is after the nORT (Reset) output goes H level from
L level (power on, recovery from VM < 7 V). During nSLEEP in L level, all the motor-drive functions are shut
down and their outputs are high-impedance state. This device forces motor-driver functions to shut down for the
power-down mode, and is not damaged even if nSLEEP is asserted during motor driving.
Data is shifted at all times, regardless of nSLEEP. Care must be taken to ensure valid data has been shifted into
the internal shift register, before the STROBE rising edge, occurs while nSLEEP is LO.

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DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

nSLEEP = L (Bit 16 = L): Setup Mode

Data Bit 0 Bit 1 Bit 16 Bit 16 = L

tsu th

Clock
tcs
twl(clk) twh(clk)
Strobe
tw(STRB)

tss_min
nSLEEP Don’t Care (see Note A)

nSLEEP = L (Bit 16 = H): Extended Setup Mode

Data Bit 0 Bit 1 Bit 16 Bit 16 = H

tsu th

Clock
tcs
twl(clk) twh(clk)
Strobe
tw(STRB)

tss_min
nSLEEP Don’t Care (see Note A)

A. For initial setup, nSleep state can be "Don't care" before the tss_min timing prior to the strobe.

Figure 3. Serial Interface Timing

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 DRV8808
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SETUP REGISTER
nSLEEP
EXTENDED SETUP REGISTER

ENABLEA /
STROBE When STROBE goes HI

SDATA
DATA SHIFT REGISTER

Register is initialized after power up reset

SCLK
Register isNOT initialized after power up reset
.
An SPI write command is recommended .

A. It is recommended that after initial power up sequence, a serial command be performed to clear undefined data in the
internal shift register. This will help avoid latching undefined data into SETUP and EXTENDED SETUP registers.
SETUP and EXTENDED SETUP registers are properly initialized during power up, but internal shift register is not
initialized.

Figure 4. Serial Peripheral Interface Block Diagram

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SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

VM
nPUC
(internal)
nORT

nSLEEP_ext

nSLEEP_int is forced HI until nORT is HI.

Once nORT is HI, nSLEEP_int follows nSLEEP_ext.

nSLEEP_int
[internal only]

STB (or) ENA

STB (or) ENA going high when nSLEEP_int is LO causes

data transfer from shift registers to set up registers
??? Valid Data ??? Valid Data Set Up regs
Undefined
??? Valid Data Shift Regs
Shift Register data is valid and defined only
after a serial command
A. During startup (VM rising), internally nSLEEP de-asserted to HI, suppressing false data latching caused by a rising
edge on the STB signal. nSLEEP will remain HI until nORT is released (120 ms after dc-dc regulators come up).

Figure 5. Serial Peripheral Interface STROBE Blocking During Power Up

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 DRV8808
www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

Operation Setup Register Bit Assignment

(1) (2) (3)
Table 2. Setup Registers
BANK BIT FUNCTION DEFAULT COMMENT
0 Tblank A 0 0 00: 3.75 μs, 01: 2.50 μs
1 Tblank A 1 0 10: 5.00 μs, 11: 6.25 μs
2 Tblank B 0 0 00: 3.75 μs, 01: 2.50 μs
3 Tblank B 1 0 10: 5.00 μs, 11: 6.25 μs
4 Tblank C 0 0 00: 3.75 μs, 01: 2.50 μs
5 Tblank C 1 0 10: 5.00 μs, 11: 6.25 μs
6 DC-DC A Minoff Time 0 0: 2.2 μs, 1: 6.6 μs
7 DC-DC A SW 1
0 0: On
8 DC-DC B SW CSELECT
1: Off
9 DC-DC C SW CSELECT
10 MOTOR CHOPPING 0 0 00: 100 kHz, 01: 50 kHz
11 MOTOR CHOPPING 1 0 10: 133 kHz, 11: 200 kHz
12 RESET DELAY CONTROL 0 0: Disable, 1: Enable
13 LDO ENABLE Note 1 0: On, 1: Off
14 DC-DC B Minoff Time 0 0: 2.2 μs, 1: 6.6 μs
15 Bank Change 0 0: Bank0, 1: Bank1
0 MISD BLANK AB 0 0 00: 2.25 μs, 01: 1.50 μs
1 MISD BLANK AB 1 0 10: 3.00 μs, 11: 3.75 μs
2 MISD BLANK C 0 0 00: 2.25 μs, 01: 1.50 μs
3 MISD BLANK C 1 0 10: 3.00 μs, 11: 3.75 μs
4 VRS A 0 0: Disable, 1: Enable
VRSA = 0:
5 VRS A Level 0 0 00: 1.4 A, 01: 1.7 A
10: 1.9 A, 11: 2.2 A
VRSA = 1:
6 VRS A Level 1 0 00: 185 mV, 01: 210 mV
10: 260 mV, 11: 310 mV
7 DC-DC C Minoff Time 0 0: 2.2 μs, 1: 6.6 μs
8 VRS B 0 0: Disable, 1: Enable
1 VRSB = 0:
9 VRS B Level 0 0 00: 1.4 A, 01: 1.7 A
10: 1.9 A, 11: 2.2 A
VRSB = 1:
10 VRS B Level 1 0 00: 185 mV, 01: 210 mV
10: 260 mV, 11: 310 mV
11 DEEP SLEEP 0 0: Disable, 1: Enable
12 VRS C 0 0: Disable, 1: Enable
VRSC = 0:
13 VRS C Level 0 0 00: 1.4 A, 01: 1.7 A
10: 1.9 A, 11: 2.2 A
VRSC = 1:
14 VRS C Level 1 0 00: 185 mV, 01: 210 mV
10: 260 mV, 11: 310 mV
15 Bank Change 0 0: Bank0, 1: Bank1

(1) The LDO default follows the DC/DC B default value based on CSELECT.
(2) All bits go to default for VM < VthVM, nReset = L.
(3) RESET DELAY CONTROL set to 1 delays nORT assertion by 100 us typical. Range is 85 us to 125 us.

Copyright © 2009–2011, Texas Instruments Incorporated 15

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SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

Operation Extended Setup Register Bit Assignment

(1) (2)
Table 3. Extended Setup Register
BANK BIT FUNCTION DEFAULT COMMENT
NA 0 Signal Select 0 0 See Logic_Out Table
1 Signal Select 1 0
2 Signal Select 2 0
3 Signal Select 3 0
4 DCDC/LDO ISD Mask 0 0: Disable, 1: Enable
5 DCDC/LDO VSD Mask 0 0: Disable, 1: Enable
6 Motor ISD Mask 0 0: Disable, 1: Enable
7 TSD Mask 0 0: Disable, 1: Enable
8 Reset Mask C 0 0: Disable, 1: Enable
9 Reset Mask B 0 0: Disable, 1: Enable
10 Reset Mask A 0 0: Disable, 1: Enable
11 Reset Mask SR 0 0: Disable, 1: Enable
12 Pre TSD 0 0: TSD-20C, 1: Analog output
13 TSD Cont0 0 See TSD Control Table
14 TSD Cont1 0
15 MISD Cont 0 See MISD Control Table

(1) All bits go to default for VM < VthVM–, nReset = L.

(2) Bits [11:8] are selective shutdown bits. Setting to a 1 makes faults on the associated regulator only shutdown that regulator and allows
restart on an nSLEEP L > H transition. Setting to 0 shuts everything down and restarts only for VM < VthVM– or nReset = L.

Table 4. TSD Control – Operation After Detected TSD

TSD Cont1 TSD Cont0 DC-DC MOTORS nORT LDO RELEASED BY
0 0 OFF OFF LOW OFF VM < VthVM– or nReset = L
0 1 ON OFF HIGH ON VM < VthVM– or nReset = L or nSLEEP L > H transition
1 0 ON OFF PULSE ON VM < VthVM– or nReset = L or nSLEEP L > H transition
1 1 OFF OFF LOW OFF VM < VthVM– or nReset = L

Table 5. MISD Control – Operation After Detected Motor OCP

MISD Cont DC-DC MOTORS nORT LDO RELEASED BY
(1)
0 ON OFF PULSE ON VM < VthVM– or nReset = L or nSLEEP L > H transition
1 OFF OFF LOW OFF VM < VthVM– or nReset = L

(1) PULSE in Control Tables is 40-ms duration.

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Table 6. Logic_Out
SIGNAL SELECT FUNCTION (Logic_out OUTPUT)
0000 Detect OCP/UVP/OVP on A, output L
0001 Detect OCP/UVP/OVP on B, output L
0010 Detect OCP/UVP/OVP on C, output L
0011 Detect OCP on DC-DC/LDO regulator, output L
0100 Detect UVP, output L
0101 Detect OVP, output L
0110 Detect OCP on motor, output L
0111 Detect TSD, output L
1000 Revision code bit 0
1001 Revision code bit 1
1010 Revision code bit 2
1011 Device code bit 0
1100 Device code bit 1
1101 N/A
1110 Detect OCP/UVP/OVP on LDO regulator, output L
1111 Fix, output H

Deep Sleep Mode

Deep sleep mode can be entered by setting the deep sleep bit (bit 11) on the Setup register to HI. Once deep
sleep mode is entered, every single subsystem is disabled, except the block necessary to regain power by
making the nWAKEUP input pin LO.

Normal
DEEP SLEEP Bit (SETUP
REGISTER) = 0 Operation /
Idle State

nWAKEUP = LO
DEEP SLEEP Bit (SETUP
REGISTER) = 1

Deep Sleep nWAKEUP = HI

Figure 6. Deep Sleep Mode

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SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

DC Motor Drive
H-bridges A, B, and C can be controlled by using the ENABLE_X and PHASE_X control lines.
The H-bridge driver operation is available for VM > 15 V.
Internal current sense functionality is present by default. External sensing can be enabled through the serial
interface. If enabled, the sense resistor must be placed externally.

NOTE
A capacitor, not larger than 2200 pF, can be placed between each H-bridge output to
GND for EMI suppression purposes. It will increase the peak current but will have no
impact on the operation.

Enable or Phase Reversal

or Trip Reduction

tPDON
Sink or Source Gate
OFF to ON

tPDOFF tCOD

Sink or Source Gate

ON to OFF

Current Sense tBLANK: DC Motor

Blanking Time

Figure 7. Crossover and Blanking Timing for H-Bridge

The dc motor H-bridges include a tBLANK period to ignore huge current spike due to rush current to varistor
capacitance.

Short/Open for Motor Outputs

When a short/open situation happens, the protection circuit prevents device damage under certain conditions
(short at start-up, etc).
Shutdown is released based on MISD Control in the Extended Setup register.
(1)
Table 7. DC Motor-Drive Truth Table
FAULT
nSleep Enablex Phasex + HIGH SIDE + LOW SIDE – HIGH SIDE – LOW SIDE
CONDITION
0 0 X X OFF OFF OFF OFF
0 1 0 X OFF OFF OFF OFF
0 1 1 0 OFF ON ON OFF
0 1 1 1 ON OFF OFF ON
Motor OCP X X X OFF OFF OFF OFF
TSD X X X OFF OFF OFF OFF

(1) X = Don't care

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Charge Pump
The charge-pump voltage generator circuit utilizes, external storage, and bucket capacitors. It provides the
necessary voltage to drive the high-side switches, for both dc-dc regulators and motor driver. The charge-pump
circuit is driven at a frequency of 1.6 MHz (nom). Recommended bucket capacitance (connected from CP1 to
CP2) is 10 nF, rated at 55 V (minimum), and storage capacitance is 0.1 μF, at 16 V (minimum). The
charge-pump storage capacitor, Cstorage, should be connected from the CP output to VM.
For power save in sleep mode, the charge pump is stopped when N_SLEEP = L and all three regulators are
turned OFF. When the part is powered up, the charge pump is started first after the CSELECT capture and, 10
ms later from the CP startup, the first regulator is started up.
(1) (2)
Table 8. Charge Pump
FAULT CONDITION DC-DC Ch-A DC-DC Ch-B DC-DC Ch-C nSleep CHARGE PUMP
X OFF OFF OFF 0 OFF
X ON X X X ON
X X ON X X ON
X X X ON X ON
0 X X X 1 ON
Motor OCP X X X 1 ON
TSD OFF OFF OFF X OFF

(1) X = Don't care

(2) DC=DC status in fault condition is determined by serial register settings, TSD Control table, and MISD Control table. These tables define
status of charge pump.

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VM

Charge
Pump

Overcurrent
A_CONT Sense
(Regulator A Only)

OD_x
Control Logic
and
Vref Predriver
1V

Current Limit
Output
Voltage FBx
Supervisor
Overcurrent Protect
Disable Detect Disable
(Mask)

UVP OVP
(–30%) (+30%)

External catch diode

Soft Start, Vf < 1.2 V at peak current,
Protection Control, (1.25 ´ Iout) assuming
and 330-µH inductor
C_SELECT nORT Assertion

Setup/Extended Setup
Register

Figure 8. DC-DC Converter

This is a switch-mode regulator with integrated switches, to provide a programmed output set by the feedback
terminal. The dc-dc converter has a variable duty cycle topology. External filtering (inductor and capacitor) and
external catch diode are required. The output voltage is short circuit protected.
The regulator has a soft-start function to limit the rush current during start-up. It is achieved by using VFB ramp
during soft start.
For unused dc-dc converter channels, the external components can be removed if the channel is set to inactive
by the CSELECT pin and register bits. Recommend connecting unused FB pin to GND or V3p3 (pin 17).

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www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

3.3V
LDO_IN

NC LDO_OUT
LDO Regulator

LDO_FB

FB_B

Figure 9. Unused LDO Recommended Connections

For proper termination, it is recommended that, if left unused, the LDO terminals be connected in the following
fashion:
1. LDO IN must be powered by an input voltage greater than 1 V.
2. LDO OUT must be left disconnected.
LDO Feed Back must be connected to the DC/DC Converter Channel B Feed Back terminal.
(1) (2) (3)
Table 9. CSELECT for Start-Up
CSELECT PIN VOLTAGE DCDC_A DCDC_B DCDC_C
Gnd 0 V to 0.3 V OFF OFF OFF
Pull down (by external 200 kΩ) 1.3 V to 2.0 V OFF ON OFF
OPEN 3.0 V to 3.3 V OFF ON ON

(1) The CSELECT pin is connected to internal 3.3-V supply through 200-kΩ resister.
(2) This CSELECT pin control is valid after the PowerON Reset is initiated. Once the Setup Register is set, the dc-dc control follows the bits
7 to 9 on the Setup Register, bank 0, until the next PowerON Reset event occurred.
(3) For OPEN case, B starts up 1st and C follows after 10-ms delay.

Table 10. Regulator A Control

SETUP REGISTER BANK 0, BIT 7 A_CONT DCDC_A
0 0 ON
0 1 OFF
1 0 OFF
1 1 OFF

nReset: Input for System Reset

nReset pin assertion stops all the dc-dc converters and H-bridges. It also resets all the register contents to
default values. After deassertion of input, device follows the initial start-up sequence. The CSELECT state is
captured after the nReset deassertion (L > H).
The input is pulled up to internal 3.3 V by a 200-kΩ resistor. When the pin is H or left open, the reset function is
released. Also it has deglitch filter of 2.5 μs to 7.5 μs.

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SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

VM VthVM+
(CSELECT = Open) (VM = 6 V) Capture CSELECT
VthVM– Then Start Charge Pump
(VM = 5 V)

VCP

DCDC_A CP Start to DC-DC Delay

DCDC_B 10 ms
(Note A)

DCDC_C

120 ms

DLY
(10 ms)

nORT
L

H
Protection Mask
(UVP, OVP)

A. Charge-pump wakeup delay, from 10 ms to 20 ms due to asynchronous event capture.

B. When VM crosses the VthVM+ (about 6.0 V), the CSELECT state is captured. In case of the CSELECT being open
(pulled up to internal 3.3 V), dc-dc regulator channels B and C are turned on.
C. LDO OCP is masked during protection M\mask time.
D. In order to avoid false SPI data latching caused by a rising edge on the STB signal, nSLEEP will remain high during
the power up stage (VM rising) and until nORT is released.
E. DC/DC Channel A follows the Regulator A Control table. During power up, DC/DC Channel A starts up disabled
(SETUP BANK 0 [7] = 1).

Figure 10. Power-up Timing (Power up With DC-DC Turn on by CSELECT)

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www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

VM VthVM+
(CSELECT = 200k to GND) (VM = 6 V) Capture CSELECT
VthVM– Then Start Charge Pump
(VM = 5 V)

VCP CP Start to DC-DC Delay

DCDC_B 10 ms
(3.3 V to LDO_IN) (Note A)

LDO
(1.2 V)

120 ms
(20 ms + 100 ms)

nORT L

H
Protection Mask
(OVP, UVP for Ch-A/B/C and LDO)

A. Charge-pump wakeup delay, from 10 ms to 20 ms due to asynchronous event capture.

B. LDO Enable follows DC/DC B Enable during power up and can be controlled using the SETUP register after power
up.

Figure 11. Power-up Timing (Power up With LDO, Supplied by DCDC_B)

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DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

VM VthVM+
(CSELECT = Open) (VM = 6 V) Capture CSELECT
VthVM– Then Start Charge Pump
(VM = 5 V)

VCP CP Start to DC-DC Delay

10 ms
DCDC_B (Note A)

40 ms
DCDC_C
(3.3 V to LDO_IN)

LDO
(1.2 V)

120 ms
(20 ms + 100 ms)

nORT
L

Protection Mask
(OVP, UVP for Ch-A/B/C and LDO) H

A. Charge-pump wakeup delay, from 10 ms to 20 ms due to asynchronous event capture.

B. LDO Enable follows DC/DC B Enable during power up and can be controlled using the SETUP register after power
up. In this case, since LDO_IN is driven by DC/DC Channel C, LDO_OUT will follow DC/DC Channel C.

Figure 12. Power-up Timing (Power up With LDO, Supplied by DCDC_C)

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www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

VM VthVM+
(CSELECT = GND) (VM = 6 V)
VthVM–
(VM = 5 V)

300 ms

DCDC_B
(Off)

DCDC_C
(Off)

nORT L

Protection Mask H
(UVP, OVP)

A. When VM crosses the VthVM+ (about 6 V) with CSELECT = GND, none of three regulators are turned ON. The nORT
output is released to H after 300 ms from VthVM+ crossing.
B. LDO OCP is masked during protection mask time.

Figure 13. Power-up Timing (Power up Without DC-DC Turn on, CSELECT = GND)

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SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

VM
(CSELECT = GND)

VthVM+
VM = 6 V

VCP VM + 11 V
VM – 0.7 V

DCDC_A
(Off®On)
Note B

DCDC_B
(Off)

DCDC_C
(Off)
120 ms
(Note A)

Setup Register Setup

Strobe (9, 8, 7) = (1, 1, 0)

nORT H

Protection Mask
L

A. The regulator is started from the strobe input, same as the charge pump. No 10-ms waiting, because the VCP pin
already reached to VM – 0.7 V.
B. LDO OCP is masked during protection mask time.
C. A_CONT must be LOW or OPEN for regulator A to turn on.

Figure 14. Power-up Timing (DC-DC Regulator Wakeup by Setup Register)

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 DRV8808
www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

VM
(CSELECT = GND)

VthVM+
VM = 6 V

DCDC_B
(Off)

10 ms
DCDC_C
(Off)

10 ms
DCDC_A
(Off®On)

Note A 120 ms

Setup Register Setup

Strobe (9, 8, 7) = (0, 0, 0)

nORT H

Protection Mask
(UVP, OVP) L

A. A_CONT must be LOW or OPEN for regulator A to turn on.

B. LDO OCP is masked during protection mask time.

Figure 15. Power-up Timing (DC-DC Regulator Wakeup by Setup Register, All Three Channels ON)

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DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

VM Start-up/Power-Down and Glitch Condition

1. Start up with VM glitch (not below VthVM–)

VM
(CSELECT = Open) VM = 6 V VthVM+

VM = 5 V
VthVM–

DCDC_B

10 ms
(Note A)
DCDC_C

120 ms
10 ms

nORT

Protection Mask
(UVP, OVP)

A. LDO OCP is masked during protection mask time.

Figure 16.

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www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

2. Start up with VM glitch (below VthVM–)

VM VthVM+
(CSELECT = Open) VM = 6 V

VM = 5 V
VthVM–
Restart
Shut Down

10 ms 10 ms
DCDC_B (Note A) (Note A)

DCDC_C
120 ms

10 ms t 10 ms
(in Case
t < 120 ms)
nORT
L

Protection Mask H
(UVP, OVP)

A. LDO OCP is masked during protection mask time.

Figure 17.

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SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

3. Power down (normal)

VthVM+
VM VM = 6 V
VthVM–
VM = 5 V Mask

Shut Down

DCDC_B

DCDC_C

nORT

Protection Mask
(UVP, OVP) Masks UVP, OVP on All DC-DC.
Masks UVP, OVP, and OCP on LDO.

Figure 18.

4. Power down (glitch on VM)

VthVM+
VM = 6 V
VM
VthVM–
VM = 5 V Mask

DCDC_B

DCDC_C

nORT

Masks UVP, OVP on All DC-DC.

Protection Mask Masks UVP, OVP, and OCP on LDO.
(UVP, OVP)

Figure 19.

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www.ti.com SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011

5. Power down (glitch on VM below VthVM–)

VthVM+ VthVM+
VM VM = 6 V
(CSELECT = Open) VthVM–

Restart

Shut Down

10 ms
DCDC_B (Note A)

10 ms

DCDC_C

nORT

Protection Mask
(UVP, OVP)

A. LDO OCP is masked during protection mask time.

Figure 20.

nReset

nORT
See Note A
A. 2.5 μs < (nReset Deglitch + Output Delay) < 10 μs

Figure 21. Shut Down by nReset

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SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011 www.ti.com

Blanking Time Insertion Timing for DC Motor Driving

For the dc motor-driving H-bridge, tBlank is inserted at each phase reversal and following each chopping cycle
(once in every eight OSCM clocks).
For a large n number (5 or 6), tBlank setup may decrease the Itrip detect window. Care must be taken when
optimizing this in the system.
Case A: Phase duty = 25%
• A*1 for setup bit = (1,0)
• A*2 for setup bit = (0,1)
OSCM

Phase

Resync Resync Resync Resync

fChop
8 ´ OSCM Clocks
tBlank (0,1)
(see Note A) 2.5 µs 2.5 µs 2.5 µs 2.5 µs 2.5 µs

tBlank (1,0)
(see Note B)
5 µs 5 µs 5 µs <5 µs 5 µs
A. Setup register bit <1:0> = (1,0), tBlank = 5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)
B. Setup register bit <1:0> = (0,1), tBlank = 2.5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)

Case B: Phase duty = 40%

• B*1 for setup bit = (1,0)
• B*2 for setup bit = (0,1)
OSCM

Phase

Resync Resync Resync Resync

fChop
8 ´ OSCM Clocks 8 ´ OSCM Clocks
tBlank (0,1)
(see Note A) 2.5 µs 2.5 µs 2.5 µs 2.5 µs
<2.5 µs

tBlank (1,0)
(see Note B) 5 µs 5 µs 5 µs 5 µs
<5 µs
A. Setup register bit <1:0> = (1,0), tBlank = 5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)
B. Setup register bit <1:0> = (0,1), tBlank = 2.5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)

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Function Table in nORT, Power Down, VM Conditions

The following is valid only when the protection control bits (in Extended Setup register) are all 0.

Table 11.
DEVICE STATUS CHARGE PUMP OSCM nORT MODE SETTING
nSleep Active Active Inactive Available
nORT Inactive Active Active Depend on power down
VM < 6 V during power down Active Active See timing chart Depend on power down
4.5 V < VM Inactive Inactive Active Unavailable

Table 12. Shutdown Functions

FAULT CONDITION DCDC_A DCDC_B DCDC_C MOTOR nORT
DCDC_A UVP/OVP/OCP Shut down Shut down Shut down Shut down Asserted (low)
DCDC_B UVP/OVP/OCP Shut down Shut down Shut down Shut down Asserted (low)
DCDC_C UVP/OVP/OCP Shut down Shut down Shut down Shut down Asserted (low)
Motor OCP See MISD Control See MISD Control See MISD Control See MISD Control See MISD Control
Table Table Table Table Table
TSD See TSD Control See TSD Control See TSD Control See TSD Control See TSD Control
Table Table Table Table Table
• Table is valid when the Protection and Reset Mask bits in the Extended Setup register are all 0.
• If Reset Mask (selective shutdown) bits are set, shutdown and release description is in the note following the
Extended Setup register definition.
• DC-DC regulators are released at VM > VthVM+ when VM increasing. When VM decreasing, regulators are shut
down when VM < VthVM–. When VthVM+ > VM > VthVM–, OVP and UVP are masked.
• Motor OCP shutdown release is specified in MISD Control Table.
• TSD shutdown release is specified in TSD Control Table.

Copyright © 2009–2011, Texas Instruments Incorporated 33

 PACKAGE OPTION ADDENDUM

www.ti.com 22-Feb-2010

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
DRV8808DCA ACTIVE HTSSOP DCA 48 40 TBD Call TI Call TI
DRV8808DCAR ACTIVE HTSSOP DCA 48 2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

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Addendum-Page 1
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